IDT PCI Express 89HPES32NT24xG2, User Manual, Page: 638 / 744

IDT DMA Function Registers
PES32NT24xG2 User Manual 23 - 50 January 30, 2013
Notes
DMA Channel Registers
DMAC[1:0]CTL - DMA Channel Control (0x500/600)
DMAC[1:0]CFG - DMA Channel Configuration (0x504/604)
Bit
Field
Field
Name
Type Default
Value
Description
0 RUN RW 0x0 Run.
Writing a one into this bit position initiates DMA descriptor
processing if the DMA channel is idle and the E bit in the
DMACxSTS register is cleared. In addition, under certain
circumstances this bit is automatically set to a one when a
DMA operation is initiated as a side effect of other events
(e.g., when a value is written to the DMAxDPTRL register).
Writing a one into this bit position while the DMA channel is
suspended, resumes DMA channel operation if the E bit in
the DMACxSTS register is cleared.
Writing a one into this bit position while the DMA channel is
running (i.e., the bit is already a one) can be used to per-
form dynamic appending of descriptor lists (refer to section
Dynamic Appending of Descriptor Lists on page 15-19).
Writing a zero to this bit position has no effect on the opera-
tion of the DMA channel.
This bit is automatically cleared when DMA descriptor pro-
cessing halts or is aborted.
In the case that software sets this bit in the same clock
cycle that it is cleared by hardware, the bit is set (i.e., soft-
ware is given priority).
1 ABORT RW 0x0 Abort.
Writing a one into this bit position causes the DMA control-
ler to abort the DMA operation currently in progress. The
abortion of a DMA operation is acknowledged when the
Abort (A) bit is set in the DMACxSTS register.
Writing a zero to this bit position has no effect on the opera-
tion of the DMA channel.
2 SUSPEND RW 0x0 Suspend.
Writing a one to this bit position suspends DMA descriptor
processing.
31:3 Reserved RO 0x0 Reserved field.
Bit
Field
Field
Name
Type Default
Value
Description
0 DISDPTRL RW 0x1 Disable DMACxDPTRL Descriptor Processing Initia-
tion.
When this bit is set, initiation of DMA descriptor processing
as a side-effect writing to the DMCAxDPTRL register is dis-
abled.