IDT PCI Express 89HPES32NT24xG2, User Manual, Page: 584 / 744

IDT NT Endpoint Registers
PES32NT24xG2 User Manual 22 - 92 January 30, 2013
Notes
Punch-Through Configuration Registers
Refer to section Punch-Through Configuration Requests on page 14-18 for a detailed description of
punch-through configuration requests.
PTCCTL0 - Punch-Through Configuration Control 0 (0x510)
15 HLO RW 0x0
SWSticky
Header Log Overflow Trigger.
Writing a one to this bit causes the corresponding error bit
to get set in the AERCES register. This bit always returns
0x0 when read.
31:16 Reserved RO 0x0 Reserved field.
Bit
Field
Field
Name
Type Default
Value
Description
1:0 Reserved RO 0x0
Reserved field.
7:2 REG RW 0x0 Register Number
This field selects the configuration register number (as
defined by Section 7.2.2 of the PCI Express Base Specifi-
cation) in the punch-through configuration request
11:8 EREG RW 0x0 Extended Register Number
This field selects the extended configuration register num-
ber (as defined by Section 7.2.2 of the PCI Express Base
Specification) in the punch-through configuration request.
15:12 Reserved RO 0x0
Reserved field.
18:16 FUNC RW 0x0 Function Number
This field selects the function number (as defined by Sec-
tion 7.2.2 of the PCI Express Base Specification) in the
punch-through configuration request completer ID field.
23:19 DEV RW 0x0 Device Number
This field selects the device number (as defined by Section
7.2.2 of the PCI Express Base Specification) in the configu-
ration request completer ID field.
31:24 BUS RW 0x0 Bus Number
This field selects the bus number (as defined by Section
7.2.2 of the PCI Express Base Specification) in the configu-
ration request completer ID field.
Bit
Field
Field
Name
Type Default
Value
Description