IDT PCI Express 89HPES32NT24xG2, User Manual, Page: 476 / 744

IDT Proprietary Port Specific Registers
PES32NT24xG2 User Manual 21 - 28 January 30, 2013
Notes
Physical Layer Control and Status Registers
This section describes the port’s physical layer control and status registers. As described in section
SerDes Numbering and Port Association on page 8-1, a port’s association with a SerDes quad depends on
the configuration of the corresponding stack. SerDes configuration and status registers listed in this section
apply to the SerDes quad lane(s) associated with the port.
Also, a port’s maximum supported link width also depends on the product option. Register fields which
have per-lane control or status bits are only valid for lanes included within the port’s maximum supported
link width. For example, if a port’s maximum link width is set to x2 (i.e., the port’s MAXLNKWDTH field in the
PCIELCAP register is set to 0x2), lane control and status bits for lanes 0 and 1 are valid, while lane control
and status bits for lanes 2 and above are invalid and may take on undefined values.
SERDESCFG - SerDes Configuration (0x510)
LANESTS0 - Lane Status 0 (0x51C)
Bit
Field
Field
Name
Type Default
Value
Description
7:0 RCVD_OVRD RW 0x0
SWSticky
Receiver Detect Override.
Each bit in this register corresponds to a lane associated
with this port. Setting this bit causes the lane associated
with this bit to indicate that a receiver has been detected on
the line.
This field is not valid when the port operates in SerDes Test
Mode.
15:8 Reserved RO 0x0 Reserved field.
16 LSE RW 0x0
SWSticky
Low-Swing Mode Enable.
When set, this bit enables Low-Swing mode operation at
the SerDes Transmit logic for the lanes associated with the
port. Please refer to section Low-Swing Transmitter Voltage
Mode on page 8-12 for further details.
0x0 - Full-Swing Mode
0x1 - Low-Swing Mode
31:17 Reserved RO 0x0 Reserved field.
Bit
Field
Field
Name
Type Default
Value
Description
7:0 PDE RW1C 0x0 Phy Disparity Error.
Each bit in this field corresponds to a lane associated with
the port. A bit is set when an 8B10B coding violation has
resulted in a running disparity error in the received data
stream.
A bit can only be set when the LTSSM is in the L0 state.
15:8 Reserved RO 0x0 Reserved field.
23:16 E8B10B RW1C 0x0 8B10B Error.
Each bit in this field corresponds to a lane associated with
the port. A bit is set when an 8B10B decode error is
detected in the received data stream.
A bit can only be set when the LTSSM is in the L0, Configu-
ration, Disabled, or Hot Reset states.
31:24 Reserved RO 0x0 Reserved field.