IDT PCI Express 89HPES32NT24xG2, User Manual, Page: 138 / 744

IDT Link Operation
PES32NT24xG2 User Manual 7 - 10 January 30, 2013
Notes
• May be automatically entered (i.e., ASPM) or directed by software by placing the device in the
D3
hot
state
– L2/L3 Ready
• The L2/L3 state is entered after the acknowledgement of a Power Management Event Turn Off
(PME_Turn_Off) Message.
• There is no TLP or DLLP communications over a link in this state.
• The L2/L3 Ready state can only be exited when the port is reset (i.e., as a result of a switch
fundamental reset, a partition fundamental reset, or a port reset caused by an operating mode
change on the port).
• In the PES32NT24xG2, the link is considered link-down in the L2/L3 Ready state.
This allows a power management turn-off event in a partition to be signaled via the event signal-
ing mechanism (see Chapter 16, Switch Events).
In an upstream port, a link-down due to L2/L3 Ready does not cause a hot reset on the port.
– L3
• Link is completely unpowered and off
– Link-Down
• A transitional link-down pseudo-state prior to L0. This pseudo-state is associated with the
LTSSM Detect, Polling, Configuration (when coming from Detect
→
Polling
→
Configuration),
Disabled, Loopback, and Hot Reset states. In these states, the data-link is in the DL_Inactive
state and reports a DL_Down condition to the higher layers.
Figure 7.4 PES32NT24xG2 ASPM Link State Transitions
Link Down Handling
When an upstream port’s data-link indicates a DL_Down status, it triggers a hot reset in the partition
associated with the port, as described in section Partition Hot Reset on page 3-12. In addition:
– All TLPs queued in the port’s ingress frame buffer (IFB) are silently discarded.
– All TLPs queued in the port’s replay buffer (EFB) are silently discarded.
L0
L0s L1
L2/L3 Ready
L3
Link-down
Fundamental Reset
Hot Reset
Etc.