10. Registers > Packet Generation and Capture Registers
CPS-1848 User Manual
303
June 2, 2014
Formal Status
This document is confidential and is subject to an NDA.
Integrated Device Technology
10.11.2 Port {0..17} Packet Generation and Capture Mode Configuration Register
For base address information, see
Packet Generation and Capture Base Addresses
Register Name: PORT_{0..17}_PGC_MODE
Reset Value: 0x0000_0000
Register Offset: 0x (0x10 * port_num)
Bits
0
1
2
3
4
5
6
7
00:07
Reserved
08:15
Reserved
START
16:23
RX_DONE
EN
END_PORT
START_PO
RT
EOP
SOP
FLOW_TYPE
24:31
FLOW_TYPE
Bits
Name
Description
Type
Reset
Value
0:14
Reserved
Reserved
RO
0
15
START
1 = Start the data transmission from the Start port to End port.
RW
0
16
RX_DONE
The transmitted packet is ready to be read from the destination
port’s Final Buffer.
RO
0
17
EN
1 = Enable data structure access for internal data structure. Write
access for the Start port. Read access for End port.
RW
0
18
END_PORT
0 = This port is not the End port for the PGC test.
1 = This port is the End port for the PGC test.
RW
0
19
START_PORT
0 = This port is not the Start port for the PGC test.
1 = This port is the Start port for the PGC test.
RW
0
20
EOP
0 = This data word does not represent the last word in a PGC
packet.
1 = This data word represents the last word in a PGC packet.
RW
0
21
SOP
0 = This data word does not represent the first word in a PGC
packet.
1 = This data word represents the first word in a PGC packet.
RW
0
22:31
FLOW_TYPE
0b0000000001 = VC0 PRI 0 CRF 0
0b0000000010 = VC0 PRI 0 CRF 1
0b0000000100 = VC0 PRI 1 CRF 0
0b0000001000 = VC0 PRI 1 CRF 1
0b0000010000 = VC0 PRI 2 CRF 0
0b0000100000 = VC0 PRI 2 CRF 1
0b0001000000 = VC0 PRI 3 CRF 0
0b0010000000 = VC0 PRI 3 CRF 1
RW
0