IDT CPS-1848, User Manual

Page: 256 / 450

10. Registers > Error Management Extensions Block Registers
CPS-1848 User Manual 256 June 2, 2014
Formal Status This document is confidential and is subject to an NDA.
Integrated Device Technology
10.7.10 Port {0..17} Error Rate Enable CSR
The broadcast version of this register is Broadcast Port Error Rate Enable Register , which will write the same value to all ports.
For base address information, see Port Error Management Register Base Addresses .
Register Name: PORT_{0..17}_ERR_RATE_EN_CSR
Reset Value: 0x0000_00000 Register Offset: 0x (0x40 * port_num)
Bits 0 1 2 3 4 5 6 7
00:07 IMP_SPEC
_ERR_EN
Reserved
08:15 Reserved CS_CRC_E
RR_EN
UNEXP_AC
KID_EN
CS_NOT_A
CC_EN
PKT_ILL_A
CKID_EN
PKT_CRC_
ERR_EN
PKT_ILL_SI
ZE_EN
Reserved
16:23 IDLE1_ER
R_EN
Reserved
24:31 Reserved LR_ACKID
_ILL_EN
PRTCL_ER
R_EN
Reserved DELIN_ER
R_EN
CS_ACK_IL
L_EN
LINK_TIME
OUT_EN
Bits Name Description Type
Reset
Value
0 IMP_SPEC_ERR_EN 1 = Enable the capture and counting of the corresponding
error in the Port {0..17} Error Detect CSR .
RW 0
1:8 Reserved Reserved RO 0
9 CS_CRC_ERR_EN 1 = Enable the capture and counting of the corresponding
error in the
Port {0..17} Error Detect CSR .
RW 0
10 UNEXP_ACKID_EN 1 = Enable the capture and counting of the corresponding
error in the
Port {0..17} Error Detect CSR .
RW 0
11 CS_NOT_ACC_EN 1 = Enable the capture and counting of the corresponding
error in the
Port {0..17} Error Detect CSR .
RW 0
12 PKT_ILL_ACKID_EN 1 = Enable the capture and counting of the corresponding
error in the Port {0..17} Error Detect CSR .
RW 0
13 PKT_CRC_ERR_EN 1 = Enable the capture and counting of the corresponding
error in the
Port {0..17} Error Detect CSR .
RW 0
14 PKT_ILL_SIZE_EN 1 = Enable the capture and counting of the corresponding
error in the
Port {0..17} Error Detect CSR .
RW 0
15 Reserved Reserved RO 0
16 IDLE1_ERR_EN 1 = Enable the capture and counting of the corresponding
error in the
Port {0..17} Error Detect CSR .
RW 0
17:25 Reserved Reserved RO 0