7. I2C Interface > Temporary Master Mode
CPS-1848 User Manual
171
June 2, 2014
Formal Status
This document is confidential and is subject to an NDA.
Integrated Device Technology
7.3.1
Obtaining Configuration in Master Mode
If the Master mode signal, MM_N, is tied to GND, the CPS-1848 will attempt to load its configuration registers after the device
reset sequence has completed. The CPS-1848 uses a 7-bit address of 1010[ID2][ID1][ID0] as the slave address of the device
from which it will obtain its configuration. [ID2][ID1][ID0] are external signals to the device, and are the same three lower bits
that would be used for the device’s I
2
C address when configured as a slave. When configured to come out of reset as an I
2
C
master, the device supports communication only with an external device that has a 7-bit address. 10-bit I
2
C addressing is not
supported in this mode. The data includes a CRC value that the CPS-1848 uses to compare against its own calculated value to
determine the validity of the registers load. The registers are loaded from the EEPROM regardless of the value of the
checksum, but a flag is set (
I2C Master Status and Control Register
.CHKSUM_FAIL) if the CRC fails.
When in this mode, the state of the external ADS signal is ignored. Once the CPS-1848 completes its configuration sequence
(successfully or unsuccessfully), it reverts to Slave mode (where the ADS signal becomes active).
7.3.2
Commanded Master Mode
The CPS-1848 can be commanded into temporary Master mode using a maintenance write to the
and
I2C Master Status and Control Register
. In this scenario, the device has come out of reset in Slave mode with the Master
mode external signal left floating, or optionally tied to V
DD3
(3.3V). Writing to START_READ in the
causes the device to transition from Slave to temporary Master mode and read the EEPROM from the
address specified in the EPROM_START_ADDR.
Commanded Master mode provides more configuration sequence flexibility. In this scenario the EEPROM slave address, and
the EEPROM start address for the download, are both programmable. Whether or not a checksum comparison is performed to
validate the download is also programmable. These configuration sequence options are established by writes to the
and
I2C Master Status and Control Register
.
During (and after) the configuration sequence, the CPS-1848 provides status information about the operation. This status
includes whether any I
2
C errors occurred, whether the operation is active or finished (see
.READING), and whether the operation was successful (see
I2C Master Status and Control Register
.SUCCESS). The
ability to abort the operation using a maintenance write to the
I2C Master Status and Control Register
is also provided.
When the device is in temporary Master mode, the state of the external ADS signal is ignored. Once the device completes its
configuration sequence (successfully or unsuccessfully), it reverts to slave mode (where the ADS signal will become active).
7.3.3
Master Clock Frequency
While in Master mode, the CPS-1848 can be configured to supply a clock of either 100 kHz (Standard mode) or 400 kHz
(Fast mode). For more information, see
.SPD_SEL.
7.3.4
EEPROM Format
The device’s register map is based on the concept of configuration blocks whose definition and accompanying data is located
at specific places in the EEPROM address map. The definition of the register map is as follows:
1. Byte addresses 0x0000 and 0x0001 contain the version number to be used as an initial verification of the registers (see
). Each address must contain the value 0xAA, otherwise the EEPROM contents will not be loaded.
2. Byte addresses 0x0002 and 0x0003 define the number of configuration blocks that are in the register map. This value is one
less than the number of configuration blocks in the device. For one image, the value should be 0x00 for each address.
3. Byte address 0x0004 is the start of the first block. All blocks have the same format.
4. The first byte in the block encodes the lower 8 bits [7:0] of a 10-bit word defining the number of registers represented in this
block. A value of 0 = 1 register, 1 = 2 registers, and so on.
5. The first two bits in the second byte (bits 7 and 6) are the upper two bits of the number of registers loaded. The lower 6 bits
are the upper bits of the address (bits [21:16]).
