2
©2018 Integrated Device Technology, Inc.
March 7, 2018
9FGV1005 Register Descriptions and Programming Guide
I
2
C Interface and Register Access
When powered up in I
2
C mode, the device allows access to internal RAM registers. The default device address is 0xD0 for 8 bits or 0x68
for 7 bits. The device can be preprogrammed for addresses in the range 0xD0-D2-D4-D6 for 8 bits or 0x68-69-6A-6B for 7 bits. The
device acts as a slave device on the I
2
C bus using one of the four I
2
C addresses to allow multiple devices to be used in the system. The
interface accepts byte-oriented block write and block read operations. Two address bytes specify the register address of the byte position
of the first register to write or read. Data bytes (registers) are accessed in sequential order from the lowest to the highest byte (most
significant bit first). Read and write block transfers can be stopped after any complete byte transfer. During a write operation, data will not
be moved into the registers until the STOP signal is received, at which point, all data received in the block write will be written
simultaneously in the registers.
For full electrical I
2
C compliance, it is recommended to use external pull-up resistors for SDATA and SCLK. The internal pull-up resistors
have a size of 100k
Ω
typical.
Figure 2. I
2
C R/W Sequence
Table 1. Power-Up Setting of Hardware Select Pin vs I
2
C Mode, and Default OTP Configuration Register
OUT0_SEL_I2CB Strap at
Power-Up
SEL1/SDA pin
SEL0/SCL pin
Function
10k
Ω
pull-up
0
0
OTP bank CFG0 used to initialize RAM configuration registers.
0
1
OTP bank CFG1 used to initialize RAM configuration registers.
1
0
OTP bank CFG2 used to initialize RAM configuration registers.
1
1
OTP bank CFG3 used to initialize RAM configuration registers.
10k
Ω
pull-down or floating
SDA
SCL
I
2
C
bus enabled to access registers.
OTP bank CFG0 used to initialize RAM configuration registers.