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©2018 Integrated Device Technology, Inc
September 12, 2018
8A3xxxx Family Programming Guide
DPLL_FREQ_0.DPLL_WR_FREQ
Set DPLL frequency offset in write frequency mode.
Module: DPLL_PHASE_PULL_IN_0
Configures the DPLL phase pull-in.
Table 295: DPLL_FREQ_0.DPLL_WR_FREQ Bit Field Locations and Descriptions
Offset
Address
(Hex)
DPLL_FREQ_0.DPLL_WR_FREQ Bit Field Locations
D7
D6
D5
D4
D3
D2
D1
D0
000h
DPLL_WR_FREQ[7:0]
001h
DPLL_WR_FREQ[15:8]
002h
DPLL_WR_FREQ[23:16]
003h
DPLL_WR_FREQ[31:24]
004h
DPLL_WR_FREQ[39:32]
005h
RESERVED[47:42]
DPLL_WR_FREQ[41:40]
DPLL_FREQ_0.DPLL_WR_FREQ Bit Field Descriptions
Bit Field Name
Field Type Default Value
Description
RESERVED
N/A
-
This field must not be modified from the read value
DPLL_WR_FREQ[41:0]
R/W
0
Signed 42-bit FFO in units of 2^(-53).
Used when DPLL_n.DPLL_MODE.PLL_MODE = write frequency mode.
Table 296: DPLL_PHASE_PULL_IN_0 Register Index
Offset
(Hex)
Register Module Base Address: C880h
a
a. This register module is instantiated multiple times. This is the base address of the first instantiation of this module. For later instantiations,
use the appropriate module base address.
Individual Register Name
Register Description
000h
DPLL_PHASE_PULL_IN_0.DPLL_PHASE_PUL
L_IN_OFFSET
Phase pull-in offset.
004h
DPLL_PHASE_PULL_IN_0.DPLL_PHASE_PUL
L_IN_SLOPE_LIMIT
Phase pull-in slope limit.
007h
DPLL_PHASE_PULL_IN_0.DPLL_PHASE_PUL
L_IN_CTRL
Phase pull-in configuration.