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IDT 8A3 Series, Programming Manual

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©2018 Integrated Device Technology, Inc

September 12, 2018

8A3xxxx Family Programming Guide

DPLL_0.DPLL_CTRL_0

Enable revertive switching, hitless switching and global sync mode.

Table 174: DPLL_0.DPLL_CTRL_0 Bit Field Locations and Descriptions

Offset 

Address 

(Hex)

DPLL_0.DPLL_CTRL_0 Bit Field Locations

D7

D6

D5

D4

D3

D2

D1

D0

002h

FORCE_LOCK_INPUT[7:3]

GLOBAL_SY

NC_EN[2]

REVERTIVE

_EN[1]

HITLESS_E

N[0]

DPLL_0.DPLL_CTRL_0 Bit Field Descriptions

Bit Field Name

Field Type Default Value

Description

FORCE_LOCK_INPUT[7:3

]

R/W

0

DPLL reference input index when force lock applied. 
0x00 = CLK0
0x01 = CLK1
0x02 = CLK2
0x03 = CLK3
0x04 = CLK4
0x05 = CLK5
0x06 = CLK6
0x07 = CLK7
0x08 = CLK8
0x09 = CLK9
0x0A = CLK10
0x0B = CLK11
0x0C = CLK12
0x0D = CLK13
0x0E = CLK14
0x0F = CLK15
0x10 = write-phase input
0x11 = write-frequency input (NA in this mode)
0x12 = XO_DPLL.

GLOBAL_SYNC_EN[2]

R/W

0

Enable global sync trigger to synchronize multiple DPLLs.
When this bit is set to 1, the phase of this DPLL's outputs will be aligned with the 
phase of other DPLLs' outputs, whose global_sync_en bit is also set to 1. When 
one of the DPLLs with this bit set to 1 requires phase synchronization, all DPLLs 
with this bit set to 1 will perform a phase synchronization procedure.
0 = disabled
1 = enabled

REVERTIVE_EN[1]

R/W

0

Enable revertive mode.
0 = disabled
1 = enabled

HITLESS_EN[0]

R/W

0

Enable hitless switch mode.
0 = disabled
1 = enabled

Summary of Contents for 8A3 Series

Page 1: ...he device name datasheet to check the version used by that device All devices that use this version number use some subset of this register map as indicated in their device specific Programming Guide Addendum document Evaluation Board Reference Manual Describes the Evaluation Board Evaluation boards are available for the 8A34001 144BGA or 8A34002 72QFN devices These devices contain a superset of t...

Page 2: ...s function overall device memory map and register addresses I2C Slave Operation discusses register accessing topics related to I2C operation on a serial port SPI Operation discusses register accessing topics related to SPI operation on a serial port Register Table Overview discusses register table format and abbreviations Register Set Descriptions describes a set of registers that is made availabl...

Page 3: ...an be reconfigured over either serial port at any time by accessing the appropriate registers This includes both configuration options with each protocol or switching between protocols I2C to SPI or vice versa However it is recommended that the full operating mode configuration including page sizes for registers for each serial port be set in the initial configuration data read from OTP or externa...

Page 4: ...rs In 1B mode the lower 8 bits of the register offset address come from the Offset Addr byte and the upper 8 bits come from the page register see Table 2 for description of the 8 bit I2 C Page Register The page register can be accessed at any time no matter what page the serial port is currently on using an offset byte value of FCh This 4 byte register must be written in a single burst write trans...

Page 5: ...in I2C transaction itself and so have no meaning PAGE_ADDR 15 8 R W 00h Select which register page to access Forms the upper 8 bits of the 16 bit register address Only values of 80h or higher should be used Lower addresses are not user accessible PAGE_ADDR 23 16 R W 10h Must be set to 10h in all cases PAGE_ADDR 31 24 R W 20h Must be set to 20h in all cases Table 3 I2 C 2B Mode Page Register Bit Fi...

Page 6: ... EEPROM configuration loaded at reset 1 byte 1B or 2 byte 2B offset addressing see Figure 1 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 R W D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 Hi Z CS SCLK SDI 4 wire SDIO 4 wire 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 3...

Page 7: ...ction to set it The page register is replicated on every register page to always be accessible Data sampling on falling or rising edge of SCLK Output read data positioning relative to active SCLK edge 4 wire SCLK SCSb SDATA SDO or 3 wire SCLK SCSb SDATA operation In 3 wire mode SDATA is a bi directional data pin Output signal protocol compatibility drive strength and termination voltage Table 4 SP...

Page 8: ...ad from 0xC024 7F FD 80 10 20 Set Page register C0 24 00 MSB is set so this is a read command Table 5 SPI 2B Mode Page Register Bit Field Locations and Descriptions Offset Address Hex SPI 2B Mode Page Register Bit Field Locations D7 D6 D5 D4 D3 D2 D1 D0 7FFD1 PAGE_ADDR 15 PAGE_ADDR 14 8 7FFE PAGE_ADDR 23 16 7FFF PAGE_ADDR 31 24 1 Burst access must begin at this non aligned offset and all 3 bytes m...

Page 9: ...ds may occupy a single byte When there are multiple bit fields within a single byte all bit fields are read from or written to during an access to that byte address over the serial port When a bit field spans multiple byte addresses all bytes should be read or written in the same serial port burst transaction to ensure consistency For bit fields spanning multiple bytes the least significant bits o...

Page 10: ...at module a brief description of the register and a link to that register s detailed description This is shown in Figure 4 Figure 4 Finding a Register s Detailed Description in this Document Many register modules include a trigger register at the end of the module that must be written to for any other register changes within that module to take effect This allows multiple parameters to be setup th...

Page 11: ...section see blue arrows in Figure 5 Please ensure that when addressing a register that the base address of the correct instantiation of the module is used see red arrows in Figure 5 Note that the base address indicated in the table description is for the first instantiation of the module only see green arrow in Figure 5 For example as shown below to access the DPLL_MANUAL_HOLDOVER_VALUE bit field ...

Page 12: ... W indicates a register is readable and write able by the user R O indicates that a register should only be read by the user Writing to a R O register has an undefined effect W O indicates that a register should only be written to by the user The read value is undefined and has no associated meaning RW1C indicates a register that can be read but a 1 needs to be written to the bit to clear it back ...

Page 13: ...dule must not be modified from the read value C180h RESERVED This module must not be modified from the read value C188h Module ALERT_CFG Notification configuration C194h Module SYS_DPLL_XO System DPLL XO configuration C19Ch Module SYS_APLL System APLL configuration C1B0h Module INPUT_0 Input 0 configuration C1C0h INPUT_1 Input 1 configuration Same as INPUT_0 C1D0h INPUT_2 Input 2 configuration Sam...

Page 14: ...N_3 Reference monitor 3 Same as REF_MON_0 C318h REF_MON_4 Reference monitor 4 Same as REF_MON_0 C324h REF_MON_5 Reference monitor 5 Same as REF_MON_0 C330h REF_MON_6 Reference monitor 6 Same as REF_MON_0 C33Ch REF_MON_7 Reference monitor 7 Same as REF_MON_0 C348h REF_MON_8 Reference monitor 8 Same as REF_MON_0 C354h REF_MON_9 Reference monitor 9 Same as REF_MON_0 C360h REF_MON_10 Reference monitor...

Page 15: ...LL registers C600h Module DPLL_CTRL_0 DPLL 0 control registers C63Ch DPLL_CTRL_1 DPLL 1 control registers Same as DPLL_CTRL_0 C680h DPLL_CTRL_2 DPLL 2 control registers Same as DPLL_CTRL_0 C6BCh DPLL_CTRL_3 DPLL 3 control registers Same as DPLL_CTRL_0 C700h DPLL_CTRL_4 DPLL 4 control registers Same as DPLL_CTRL_0 C73Ch DPLL_CTRL_5 DPLL 5 control registers Same as DPLL_CTRL_0 C780h DPLL_CTRL_6 DPLL...

Page 16: ...te frequency Same as DPLL_FREQ_0 C858h DPLL_FREQ_4 DPLL 4 write frequency Same as DPLL_FREQ_0 C860h DPLL_FREQ_5 DPLL 5 write frequency Same as DPLL_FREQ_0 C868h DPLL_FREQ_6 DPLL 6 write frequency Same as DPLL_FREQ_0 C870h DPLL_FREQ_7 DPLL 7 write frequency Same as DPLL_FREQ_0 C880h Module DPLL_PHASE_PULL_IN_0 DPLL 0 phase pull in control C888h DPLL_PHASE_PULL_IN_1 DPLL 1 phase pull in control Same...

Page 17: ...gisters Same as GPIO_0 C924h GPIO_5 GPIO 5 registers Same as GPIO_0 C936h GPIO_6 GPIO 6 registers Same as GPIO_0 C948h GPIO_7 GPIO 7 registers Same as GPIO_0 C95Ah GPIO_8 GPIO 8 registers Same as GPIO_0 C980h GPIO_9 GPIO 9 registers Same as GPIO_0 C992h GPIO_10 GPIO 10 registers Same as GPIO_0 C9A4h GPIO_11 GPIO 11 registers Same as GPIO_0 C9B6h GPIO_12 GPIO 12 registers Same as GPIO_0 C9C8h GPIO_...

Page 18: ...egister Same as OUTPUT_0 CAD0h OUTPUT_11 Output 11 register Same as OUTPUT_0 CAE0h Module SERIAL Serial Interfaces registers CB00h Module PWM_ENCODER_0 PWM 0 encoder registers CB08h PWM_ENCODER_1 PWM 1 encoder registers Same as PWM_ENCODER_0 CB10h PWM_ENCODER_2 PWM 2 encoder registers Same as PWM_ENCODER_0 CB18h PWM_ENCODER_3 PWM 3 encoder registers Same as PWM_ENCODER_0 CB20h PWM_ENCODER_4 PWM 4 ...

Page 19: ...R_0 CB90h PWM_DECODER_9 PWM 9 decoder registers Same as PWM_DECODER_0 CB98h PWM_DECODER_10 PWM 10 decoder registers Same as PWM_DECODER_0 CBA0h PWM_DECODER_11 PWM 11 decoder registers Same as PWM_DECODER_0 CBA8h PWM_DECODER_12 PWM 12 decoder registers Same as PWM_DECODER_0 CBB0h PWM_DECODER_13 PWM 13 decoder registers Same as PWM_DECODER_0 CBB8h PWM_DECODER_14 PWM 14 decoder registers Same as PWM_...

Page 20: ...ead TOD 1 secondary registers Same as TOD_READ_SECONDARY_0 CCB0h TOD_READ_SECONDARY_2 Read TOD 2 secondary registers Same as TOD_READ_SECONDARY_0 CCC0h TOD_READ_SECONDARY_3 Read TOD 3 secondary registers Same as TOD_READ_SECONDARY_0 CCD0h Module OUTPUT_TDC_CFG Output TDC global configuration CD00h Module OUTPUT_TDC_0 Output TDC 0 CD08h OUTPUT_TDC_1 Output TDC 1 Same as OUTPUT_TDC_0 CD10h OUTPUT_TD...

Page 21: ...ISION REV_ID Bit Field Descriptions Bit Field Name Field Type Default Value Description REV_ID 7 0 R O 2 Hardware Revision Register 1 RevA 2 RevB Table 9 RESET_CTRL Register Index Offset Hex Register Module Base Address C000h Individual Register Name Register Description 000h RESERVED This register must not be modified from the read value 001h RESERVED This register must not be modified from the r...

Page 22: ...ot be modified from the read value 011h RESERVED This register must not be modified from the read value 012h RESET_CTRL SM_RESET Reset state machine Table 10 RESET_CTRL SM_RESET Bit Field Locations and Descriptions Offset Address Hex RESET_CTRL SM_RESET Bit Field Locations D7 D6 D5 D4 D3 D2 D1 D0 012h RESET 7 0 RESET_CTRL SM_RESET Bit Field Descriptions Bit Field Name Field Type Default Value Desc...

Page 23: ...he read value 00Eh RESERVED This register must not be modified from the read value 00Fh RESERVED This register must not be modified from the read value 010h GENERAL_STATUS MAJ_REL Major release number 011h GENERAL_STATUS MIN_REL Minor release number 012h GENERAL_STATUS HOTFIX_REL Hotfix release number 014h RESERVED This register must not be modified from the read value 015h RESERVED This register ...

Page 24: ...is register must not be modified from the read value 026h GENERAL_STATUS EEPROM_CONFIG_STAT US EEPROM soft CSR configuration status Table 12 GENERAL_STATUS OTP_STATUS Bit Field Locations and Descriptions Offset Address Hex GENERAL_STATUS OTP_STATUS Bit Field Locations D7 D6 D5 D4 D3 D2 D1 D0 004h OTP_STATUS 7 0 005h OTP_STATUS 15 8 006h OTP_STATUS 23 16 007h OTP_STATUS 31 24 Table 11 GENERAL_STATU...

Page 25: ...edundant cluster invalid index 0x100007 redundant cluster program fail 0x100008 cluster program fail 0x100009 cluster read fail 0x10000A main memory program fail 0x10000B no header available 0x10000C not enough space 0x10000D header fail 0x10000E invalid boot row index 0x10000F invalid header index 0x100010 header not found 0x100011 more data available 0x100012 wrong confirmation code 0x100013 OTP...

Page 26: ...ERAL_STATUS MAJ_REL Bit Field Locations and Descriptions Offset Address Hex GENERAL_STATUS MAJ_REL Bit Field Locations D7 D6 D5 D4 D3 D2 D1 D0 010h MAJOR 7 1 PR_BUILD 0 GENERAL_STATUS MAJ_REL Bit Field Descriptions Bit Field Name Field Type Default Value Description MAJOR 7 1 R O 0 Numeric major release e g X 0 0 PR_BUILD 0 R O 0 Product release status 1 if a product release or 0 if a development ...

Page 27: ...pe Default Value Description HOTFIX 7 0 R O 0 Hotfix release number e g 1 2 Z Table 17 GENERAL_STATUS JTAG_DEVICE_ID Bit Field Locations and Descriptions Offset Address Hex GENERAL_STATUS JTAG_DEVICE_ID Bit Field Locations D7 D6 D5 D4 D3 D2 D1 D0 01Ch JTAG_DEVICE_ID 7 0 01Dh JTAG_DEVICE_ID 15 8 GENERAL_STATUS JTAG_DEVICE_ID Bit Field Descriptions Bit Field Name Field Type Default Value Description...

Page 28: ...set Address Hex GENERAL_STATUS TEMPERATURE Bit Field Locations D7 D6 D5 D4 D3 D2 D1 D0 020h TEMP_CELSIUS 7 0 021h TEMP_CELSIUS 15 8 GENERAL_STATUS TEMPERATURE Bit Field Descriptions Bit Field Name Field Type Default Value Description TEMP_CELSIUS 15 0 R O 0 Device temperature as measured by the device s internal temperature sensor 2s complement number in degrees Celsius Table 20 GENERAL_STATUS OTP...

Page 29: ...ptions Bit Field Name Field Type Default Value Description OTP_SCSR_CONFIG_ST ATUS 7 0 R O 0 Status code 0 success 1 not found 2 incomplete 3 wrong offset 4 wrong length 5 SCSR out of range 6 CRC error Table 22 GENERAL_STATUS OTP_CSR_CONFIG_STATUS Bit Field Locations and Descriptions Offset Address Hex GENERAL_STATUS OTP_CSR_CONFIG_STATUS Bit Field Locations D7 D6 D5 D4 D3 D2 D1 D0 024h OTP_CSR_CO...

Page 30: ... 0x6 CRC error 0xA corrupt header 0xB EEPROM out of range Table 24 STATUS Register Index Offset Hex Register Module Base Address C03Ch Individual Register Name Register Description 000h STATUS I2CM_STATUS I2C master status 001h RESERVED This register must not be modified from the read value 002h STATUS SER0_STATUS Status of serial interface 0 003h STATUS SER0_SPI_STATUS Status of serial interface ...

Page 31: ...9h STATUS DPLL1_STATUS DPLL 1 status 01Ah STATUS DPLL2_STATUS DPLL 2 status 01Bh STATUS DPLL3_STATUS DPLL 3 status 01Ch STATUS DPLL4_STATUS DPLL 4 status 01Dh STATUS DPLL5_STATUS DPLL 5 status 01Eh STATUS DPLL6_STATUS DPLL 6 status 01Fh STATUS DPLL7_STATUS DPLL 7 status 020h STATUS DPLL_SYS_STATUS System DPLL status 021h STATUS SYS_APLL_STATUS System APLL status 022h STATUS DPLL0_REF_STAT DPLL 0 i...

Page 32: ... reference monitor frequency status and unit 098h STATUS IN6_MON_FREQ_STATUS Input 6 reference monitor frequency status and unit 09Ah STATUS IN7_MON_FREQ_STATUS Input 7 reference monitor frequency status and unit 09Ch STATUS IN8_MON_FREQ_STATUS Input 8 reference monitor frequency status and unit 09Eh STATUS IN9_MON_FREQ_STATUS Input 9 reference monitor frequency status and unit 0A0h STATUS IN10_MO...

Page 33: ...rom the read value 0E4h STATUS DPLL1_PHASE_STATUS Phase offset at output of decimator 0E9h RESERVED This register must not be modified from the read value 0EAh RESERVED This register must not be modified from the read value 0EBh RESERVED This register must not be modified from the read value 0ECh STATUS DPLL2_PHASE_STATUS Phase offset at output of decimator 0F1h RESERVED This register must not be ...

Page 34: ...h RESERVED This register must not be modified from the read value 11Bh RESERVED This register must not be modified from the read value 11Ch STATUS DPLL0_PHASE_PULL_IN_STATUS DPLL0 phase pull in status 11Dh STATUS DPLL1_PHASE_PULL_IN_STATUS DPLL1 phase pull in status 11Eh STATUS DPLL2_PHASE_PULL_IN_STATUS DPLL2 phase pull in status 11Fh STATUS DPLL3_PHASE_PULL_IN_STATUS DPLL3 phase pull in status 1...

Page 35: ...tes the pins the I2C master is connected to 0 I2C master 1 serial interface 0 2 serial interface 1 Table 26 STATUS SER0_STATUS Bit Field Locations and Descriptions Offset Address Hex STATUS SER0_STATUS Bit Field Locations D7 D6 D5 D4 D3 D2 D1 D0 002h RESERVED 7 3 ADDRESS_S IZE 2 MODE 1 0 STATUS SER0_STATUS Bit Field Descriptions Bit Field Name Field Type Default Value Description RESERVED N A This...

Page 36: ...SDO driving edge delayed half cycle of SCLK SPI_CLOCK_SELECTION 3 R O 0 SPI Clock Selection for SDI sampling Indicates if the SPI clock selection is on a rising or falling edge 0 rising edge 1 falling edge SPI_DUPLEX_MODE 2 R O 0 SPI 4 wire or 3 wire Indicates if the SPI is in full duplex or half duplex mode 0 full duplex 1 half duplex RESERVED N A This field must not be modified from the read val...

Page 37: ...1_STATUS Bit Field Descriptions Bit Field Name Field Type Default Value Description RESERVED N A This field must not be modified from the read value ADDRESS_SIZE 2 R O 0 Serial interface 1 address size Indicates the SSI address size 0 1 byte 1 2 byte MODE 1 0 R O 0 Serial interface 1 mode Indicates the SSI protocol 0 undefined 1 I2C 2 SPI 3 disabled Table 30 STATUS SER1_SPI_STATUS Bit Field Locati...

Page 38: ...uplex or half duplex mode 0 full duplex 1 half duplex RESERVED N A This field must not be modified from the read value Table 31 STATUS SER1_I2C_STATUS Bit Field Locations and Descriptions Offset Address Hex STATUS SER1_I2C_STATUS Bit Field Locations D7 D6 D5 D4 D3 D2 D1 D0 007h RESERVED 7 DEVICE_ADDRESS 6 0 STATUS SER1_I2C_STATUS Bit Field Descriptions Bit Field Name Field Type Default Value Descr...

Page 39: ... signal was detected for input 0 0 no change 1 live status changed RESERVED N A This field must not be modified from the read value IN0_FREQ_OFFS_LIM_LI VE 2 R O 0 Frequency offset limit live status Indicates that the current frequency offset exceeds the limit for input 0 0 inactive 1 active IN0_NO_ACTIVITY_LIVE 1 R O 0 No activity live status Indicates no activity on input 0 0 inactive 1 active I...

Page 40: ... signal was detected for input 1 0 no change 1 live status changed RESERVED N A This field must not be modified from the read value IN1_FREQ_OFFS_LIM_LI VE 2 R O 0 Frequency offset limit live status Indicates that the current frequency offset exceeds the limit for input 1 0 inactive 1 active IN1_NO_ACTIVITY_LIVE 1 R O 0 No activity live status Indicates no activity on input 1 0 inactive 1 active I...

Page 41: ... signal was detected for input 2 0 no change 1 live status changed RESERVED N A This field must not be modified from the read value IN2_FREQ_OFFS_LIM_LI VE 2 R O 0 Frequency offset limit live status Indicates that the current frequency offset exceeds the limit for input 2 0 inactive 1 active IN2_NO_ACTIVITY_LIVE 1 R O 0 No activity live status Indicates no activity on input 2 0 inactive 1 active I...

Page 42: ... signal was detected for input 3 0 no change 1 live status changed RESERVED N A This field must not be modified from the read value IN3_FREQ_OFFS_LIM_LI VE 2 R O 0 Frequency offset limit live status Indicates that the current frequency offset exceeds the limit for input 3 0 inactive 1 active IN3_NO_ACTIVITY_LIVE 1 R O 0 No activity live status Indicates no activity on input 3 0 inactive 1 active I...

Page 43: ... signal was detected for input 4 0 no change 1 live status changed RESERVED N A This field must not be modified from the read value IN4_FREQ_OFFS_LIM_LI VE 2 R O 0 Frequency offset limit live status Indicates that the current frequency offset exceeds the limit for input 4 0 inactive 1 active IN4_NO_ACTIVITY_LIVE 1 R O 0 No activity live status Indicates no activity on input 4 0 inactive 1 active I...

Page 44: ... signal was detected for input 5 0 no change 1 live status changed RESERVED N A This field must not be modified from the read value IN5_FREQ_OFFS_LIM_LI VE 2 R O 0 Frequency offset limit live status Indicates that the current frequency offset exceeds the limit for input 5 0 inactive 1 active IN5_NO_ACTIVITY_LIVE 1 R O 0 No activity live status Indicates no activity on input 5 0 inactive 1 active I...

Page 45: ... signal was detected for input 6 0 no change 1 live status changed RESERVED N A This field must not be modified from the read value IN6_FREQ_OFFS_LIM_LI VE 2 R O 0 Frequency offset limit live status Indicates that the current frequency offset exceeds the limit for input 6 0 inactive 1 active IN6_NO_ACTIVITY_LIVE 1 R O 0 No activity live status Indicates no activity on input 6 0 inactive 1 active I...

Page 46: ... signal was detected for input 7 0 no change 1 live status changed RESERVED N A This field must not be modified from the read value IN7_FREQ_OFFS_LIM_LI VE 2 R O 0 Frequency offset limit live status Indicates that the current frequency offset exceeds the limit for input 7 0 inactive 1 active IN7_NO_ACTIVITY_LIVE 1 R O 0 No activity live status Indicates no activity on input 7 0 inactive 1 active I...

Page 47: ... signal was detected for input 8 0 no change 1 live status changed RESERVED N A This field must not be modified from the read value IN8_FREQ_OFFS_LIM_LI VE 2 R O 0 Frequency offset limit live status Indicates that the current frequency offset exceeds the limit for input 8 0 inactive 1 active IN8_NO_ACTIVITY_LIVE 1 R O 0 No activity live status Indicates no activity on input 8 0 inactive 1 active I...

Page 48: ...nal was detected for input 9 0 no change 1 live status changed RESERVED N A This field must not be modified from the read value IN9_FREQ_OFFS_LIM_LI VE 2 R O 0 Frequency offset limit live status Indicates that the current frequency offset exceeds the limit for input 9 0 inactive 1 active IN9_NO_ACTIVITY_LIVE 1 R O 0 No activity live status Indicates no activity on input 9 0 inactive 1 active IN9_L...

Page 49: ...nal was detected for input 10 0 no change 1 live status changed RESERVED N A This field must not be modified from the read value IN10_FREQ_OFFS_LIM_L IVE 2 R O 0 Frequency offset limit live status Indicates that the current frequency offset exceeds the limit for input 10 0 inactive 1 active IN10_NO_ACTIVITY_LIVE 1 R O 0 No activity live status Indicates no activity on input 10 0 inactive 1 active ...

Page 50: ...nal was detected for input 11 0 no change 1 live status changed RESERVED N A This field must not be modified from the read value IN11_FREQ_OFFS_LIM_L IVE 2 R O 0 Frequency offset limit live status Indicates that the current frequency offset exceeds the limit for input 11 0 inactive 1 active IN11_NO_ACTIVITY_LIVE 1 R O 0 No activity live status Indicates no activity on input 11 0 inactive 1 active ...

Page 51: ...nal was detected for input 12 0 no change 1 live status changed RESERVED N A This field must not be modified from the read value IN12_FREQ_OFFS_LIM_L IVE 2 R O 0 Frequency offset limit live status Indicates that the current frequency offset exceeds the limit for input 12 0 inactive 1 active IN12_NO_ACTIVITY_LIVE 1 R O 0 No activity live status Indicates no activity on input 12 0 inactive 1 active ...

Page 52: ...nal was detected for input 13 0 no change 1 live status changed RESERVED N A This field must not be modified from the read value IN13_FREQ_OFFS_LIM_L IVE 2 R O 0 Frequency offset limit live status Indicates that the current frequency offset exceeds the limit for input 13 0 inactive 1 active IN13_NO_ACTIVITY_LIVE 1 R O 0 No activity live status Indicates no activity on input 13 0 inactive 1 active ...

Page 53: ...nal was detected for input 14 0 no change 1 live status changed RESERVED N A This field must not be modified from the read value IN14_FREQ_OFFS_LIM_L IVE 2 R O 0 Frequency offset limit live status Indicates that the current frequency offset exceeds the limit for input 14 0 inactive 1 active IN14_NO_ACTIVITY_LIVE 1 R O 0 No activity live status Indicates no activity on input 14 0 inactive 1 active ...

Page 54: ...dicates that loss of signal was detected for input 15 0 no change 1 live status changed RESERVED N A This field must not be modified from the read value IN15_FREQ_OFFS_LIM_L IVE 2 R O 0 Frequency offset limit live status Indicates that the current frequency offset exceeds the limit for input 15 0 inactive 1 active IN15_NO_ACTIVITY_LIVE 1 R O 0 No activity live status Indicates no activity on input...

Page 55: ... occurred 0 no transition to or from Locked state 1 transition to or from Locked state DPLL0_STATE 3 0 R O 0 Current state of DPLL0 0 freerun 1 lockacq 2 lockrec 3 locked 4 holdover 5 open loop Table 49 STATUS DPLL1_STATUS Bit Field Locations and Descriptions Offset Address Hex STATUS DPLL1_STATUS Bit Field Locations D7 D6 D5 D4 D3 D2 D1 D0 019h RESERVED 7 6 DPLL1_HOL DOVER_STA TE_CHANG E_STICKY 5...

Page 56: ... DPLL2_LOC K_STATE_C HANGE_STI CKY 4 DPLL2_STATE 3 0 STATUS DPLL2_STATUS Bit Field Descriptions Bit Field Name Field Type Default Value Description RESERVED N A This field must not be modified from the read value DPLL2_HOLDOVER_STAT E_CHANGE_STICKY 5 R O 0 Holdover state change sticky bit Indicates whether any transition to or from Holdover state occurred 0 no transition to or from Holdover state ...

Page 57: ...VER_STAT E_CHANGE_STICKY 5 R O 0 Holdover state change sticky bit Indicates whether any transition to or from Holdover state occurred 0 no transition to or from Holdover state 1 transition to or from Holdover state DPLL3_LOCK_STATE_CH ANGE_STICKY 4 R O 0 Lock state change sticky bit Indicates whether any transition to or from Locked state occurred 0 no transition to or from Locked state 1 transiti...

Page 58: ... occurred 0 no transition to or from Locked state 1 transition to or from Locked state DPLL4_STATE 3 0 R O 0 Current state of DPLL4 0 freerun 1 lockacq 2 lockrec 3 locked 4 holdover 5 open loop Table 53 STATUS DPLL5_STATUS Bit Field Locations and Descriptions Offset Address Hex STATUS DPLL5_STATUS Bit Field Locations D7 D6 D5 D4 D3 D2 D1 D0 01Dh RESERVED 7 6 DPLL5_HOL DOVER_STA TE_CHANG E_STICKY 5...

Page 59: ... DPLL6_LOC K_STATE_C HANGE_STI CKY 4 DPLL6_STATE 3 0 STATUS DPLL6_STATUS Bit Field Descriptions Bit Field Name Field Type Default Value Description RESERVED N A This field must not be modified from the read value DPLL6_HOLDOVER_STAT E_CHANGE_STICKY 5 R O 0 Holdover state change sticky bit Indicates whether any transition to or from Holdover state occurred 0 no transition to or from Holdover state ...

Page 60: ... E_CHANGE_STICKY 5 R O 0 Holdover state change sticky bit Indicates whether any transition to or from Holdover state occurred 0 no transition to or from Holdover state 1 transition to or from Holdover state DPLL7_LOCK_STATE_CH ANGE_STICKY 4 R O 0 Lock state change sticky bit Indicates whether any transition to or from Locked state occurred 0 no transition to or from Locked state 1 transition to or...

Page 61: ... from Locked state 1 transition to or from Locked state DPLL_SYS_STATE 3 0 R O 0 Current state of SYS_DPLL 0 freerun 1 lockacq 2 lockrec 3 locked 4 holdover 5 open loop Table 57 STATUS SYS_APLL_STATUS Bit Field Locations and Descriptions Offset Address Hex STATUS SYS_APLL_STATUS Bit Field Locations D7 D6 D5 D4 D3 D2 D1 D0 021h RESERVED 7 5 SYS_APLL_ LOSS_LOCK _STICKY 4 RESERVED 3 1 SYS_APLL_ LOSS_...

Page 62: ...TUS DPLL0_REF_STAT Bit Field Descriptions Bit Field Name Field Type Default Value Description RESERVED N A This field must not be modified from the read value DPLL0_INPUT 4 0 R O 0 Current reference input for DPLL 0 0x00 CLK0 0x01 CLK1 0x02 CLK2 0x03 CLK3 0x04 CLK4 0x05 CLK5 0x06 CLK6 0x07 CLK7 0x08 CLK8 0x09 CLK9 0x0A CLK10 0x0B CLK11 0x0C CLK12 0x0D CLK13 0x0E CLK14 0x0F CLK15 0x10 write phase i...

Page 63: ...ied from the read value DPLL1_INPUT 4 0 R O 0 Current reference input for DPLL 1 0x00 CLK0 0x01 CLK1 0x02 CLK2 0x03 CLK3 0x04 CLK4 0x05 CLK5 0x06 CLK6 0x07 CLK7 0x08 CLK8 0x09 CLK9 0x0A CLK10 0x0B CLK11 0x0C CLK12 0x0D CLK13 0x0E CLK14 0x0F CLK15 0x10 write phase input 0x11 write frequency input 0x12 XO_DPLL 0x1F no reference Table 60 STATUS DPLL2_REF_STAT Bit Field Locations and Descriptions Offs...

Page 64: ...ied from the read value DPLL2_INPUT 4 0 R O 0 Current reference input for DPLL 2 0x00 CLK0 0x01 CLK1 0x02 CLK2 0x03 CLK3 0x04 CLK4 0x05 CLK5 0x06 CLK6 0x07 CLK7 0x08 CLK8 0x09 CLK9 0x0A CLK10 0x0B CLK11 0x0C CLK12 0x0D CLK13 0x0E CLK14 0x0F CLK15 0x10 write phase input 0x11 write frequency input 0x12 XO_DPLL 0x1F no reference Table 61 STATUS DPLL3_REF_STAT Bit Field Locations and Descriptions Offs...

Page 65: ...ied from the read value DPLL3_INPUT 4 0 R O 0 Current reference input for DPLL 3 0x00 CLK0 0x01 CLK1 0x02 CLK2 0x03 CLK3 0x04 CLK4 0x05 CLK5 0x06 CLK6 0x07 CLK7 0x08 CLK8 0x09 CLK9 0x0A CLK10 0x0B CLK11 0x0C CLK12 0x0D CLK13 0x0E CLK14 0x0F CLK15 0x10 write phase input 0x11 write frequency input 0x12 XO_DPLL 0x1F no reference Table 62 STATUS DPLL4_REF_STAT Bit Field Locations and Descriptions Offs...

Page 66: ...ied from the read value DPLL4_INPUT 4 0 R O 0 Current reference input for DPLL 4 0x00 CLK0 0x01 CLK1 0x02 CLK2 0x03 CLK3 0x04 CLK4 0x05 CLK5 0x06 CLK6 0x07 CLK7 0x08 CLK8 0x09 CLK9 0x0A CLK10 0x0B CLK11 0x0C CLK12 0x0D CLK13 0x0E CLK14 0x0F CLK15 0x10 write phase input 0x11 write frequency input 0x12 XO_DPLL 0x1F no reference Table 63 STATUS DPLL5_REF_STAT Bit Field Locations and Descriptions Offs...

Page 67: ...ied from the read value DPLL5_INPUT 4 0 R O 0 Current reference input for DPLL 5 0x00 CLK0 0x01 CLK1 0x02 CLK2 0x03 CLK3 0x04 CLK4 0x05 CLK5 0x06 CLK6 0x07 CLK7 0x08 CLK8 0x09 CLK9 0x0A CLK10 0x0B CLK11 0x0C CLK12 0x0D CLK13 0x0E CLK14 0x0F CLK15 0x10 write phase input 0x11 write frequency input 0x12 XO_DPLL 0x1F no reference Table 64 STATUS DPLL6_REF_STAT Bit Field Locations and Descriptions Offs...

Page 68: ...ied from the read value DPLL6_INPUT 4 0 R O 0 Current reference input for DPLL 6 0x00 CLK0 0x01 CLK1 0x02 CLK2 0x03 CLK3 0x04 CLK4 0x05 CLK5 0x06 CLK6 0x07 CLK7 0x08 CLK8 0x09 CLK9 0x0A CLK10 0x0B CLK11 0x0C CLK12 0x0D CLK13 0x0E CLK14 0x0F CLK15 0x10 write phase input 0x11 write frequency input 0x12 XO_DPLL 0x1F no reference Table 65 STATUS DPLL7_REF_STAT Bit Field Locations and Descriptions Offs...

Page 69: ... from the read value DPLL7_INPUT 4 0 R O 0 Current reference input for DPLL 7 0x00 CLK0 0x01 CLK1 0x02 CLK2 0x03 CLK3 0x04 CLK4 0x05 CLK5 0x06 CLK6 0x07 CLK7 0x08 CLK8 0x09 CLK9 0x0A CLK10 0x0B CLK11 0x0C CLK12 0x0D CLK13 0x0E CLK14 0x0F CLK15 0x10 write phase input 0x11 write frequency input 0x12 XO_DPLL 0x1F no reference Table 66 STATUS DPLL_SYS_REF_STAT Bit Field Locations and Descriptions Offs...

Page 70: ...09 CLK9 0x0A CLK10 0x0B CLK11 0x0C CLK12 0x0D CLK13 0x0E CLK14 0x0F CLK15 0x10 write phase input 0x11 write frequency input 0x12 XO_DPLL 0x1F no reference Table 67 STATUS DPLL0_FILTER_STATUS Bit Field Locations and Descriptions Offset Address Hex STATUS DPLL0_FILTER_STATUS Bit Field Locations D7 D6 D5 D4 D3 D2 D1 D0 044h FILTER_STATUS 7 0 045h FILTER_STATUS 15 8 046h FILTER_STATUS 23 16 047h FILTE...

Page 71: ...S DPLL1_FILTER_STATUS Bit Field Descriptions Bit Field Name Field Type Default Value Description FILTER_STATUS 47 0 R O 0 DPLL loop filter status Fine phase measurement in units of 50 128 picoseconds Table 69 STATUS DPLL2_FILTER_STATUS Bit Field Locations and Descriptions Offset Address Hex STATUS DPLL2_FILTER_STATUS Bit Field Locations D7 D6 D5 D4 D3 D2 D1 D0 054h FILTER_STATUS 7 0 055h FILTER_ST...

Page 72: ...S DPLL3_FILTER_STATUS Bit Field Descriptions Bit Field Name Field Type Default Value Description FILTER_STATUS 47 0 R O 0 DPLL loop filter status Fine phase measurement in units of 50 128 picoseconds Table 71 STATUS DPLL4_FILTER_STATUS Bit Field Locations and Descriptions Offset Address Hex STATUS DPLL4_FILTER_STATUS Bit Field Locations D7 D6 D5 D4 D3 D2 D1 D0 064h FILTER_STATUS 7 0 065h FILTER_ST...

Page 73: ...S DPLL5_FILTER_STATUS Bit Field Descriptions Bit Field Name Field Type Default Value Description FILTER_STATUS 47 0 R O 0 DPLL loop filter status Fine phase measurement in units of 50 128 picoseconds Table 73 STATUS DPLL6_FILTER_STATUS Bit Field Locations and Descriptions Offset Address Hex STATUS DPLL6_FILTER_STATUS Bit Field Locations D7 D6 D5 D4 D3 D2 D1 D0 074h FILTER_STATUS 7 0 075h FILTER_ST...

Page 74: ...DPLL7_FILTER_STATUS Bit Field Descriptions Bit Field Name Field Type Default Value Description FILTER_STATUS 47 0 R O 0 DPLL loop filter status Fine phase measurement in units of 50 128 picoseconds Table 75 STATUS DPLL_SYS_FILTER_STATUS Bit Field Locations and Descriptions Offset Address Hex STATUS DPLL_SYS_FILTER_STATUS Bit Field Locations D7 D6 D5 D4 D3 D2 D1 D0 084h FILTER_STATUS 7 0 085h FILTE...

Page 75: ...3_LEV EL 3 GPIO2_LEV EL 2 GPIO1_LEV EL 1 GPIO0_LEV EL 0 STATUS USER_GPIO0_TO_7_STATUS Bit Field Descriptions Bit Field Name Field Type Default Value Description GPIO7_LEVEL 7 R O 0 Level of GPIO pin 7 0 low 1 high GPIO6_LEVEL 6 R O 0 Level of GPIO pin 6 0 low 1 high GPIO5_LEVEL 5 R O 0 Level of GPIO pin 5 0 low 1 high GPIO4_LEVEL 4 R O 0 Level of GPIO pin 4 0 low 1 high GPIO3_LEVEL 3 R O 0 Level o...

Page 76: ...EV EL 3 GPIO10_LEV EL 2 GPIO9_LEV EL 1 GPIO8_LEV EL 0 STATUS USER_GPIO8_TO_15_STATUS Bit Field Descriptions Bit Field Name Field Type Default Value Description GPIO15_LEVEL 7 R O 0 Level of GPIO pin 15 0 low 1 high GPIO14_LEVEL 6 R O 0 Level of GPIO pin 14 0 low 1 high GPIO13_LEVEL 5 R O 0 Level of GPIO pin 13 0 low 1 high GPIO12_LEVEL 4 R O 0 Level of GPIO pin 12 0 low 1 high GPIO11_LEVEL 3 R O 0...

Page 77: ...ld Descriptions Bit Field Name Field Type Default Value Description FFO_UNIT 15 14 R O 0 Input clock FFO unit enumeration 0 1 ppb 1 10 ppb 2 100 ppb 3 1 ppm FFO 13 0 R O 0 Signed 14 bit input clock fractional frequency offset Table 79 STATUS IN1_MON_FREQ_STATUS Bit Field Locations and Descriptions Offset Address Hex STATUS IN1_MON_FREQ_STATUS Bit Field Locations D7 D6 D5 D4 D3 D2 D1 D0 08Eh FFO 7 ...

Page 78: ...ld Descriptions Bit Field Name Field Type Default Value Description FFO_UNIT 15 14 R O 0 Input clock FFO unit enumeration 0 1 ppb 1 10 ppb 2 100 ppb 3 1 ppm FFO 13 0 R O 0 Signed 14 bit input clock fractional frequency offset Table 81 STATUS IN3_MON_FREQ_STATUS Bit Field Locations and Descriptions Offset Address Hex STATUS IN3_MON_FREQ_STATUS Bit Field Locations D7 D6 D5 D4 D3 D2 D1 D0 092h FFO 7 ...

Page 79: ...ld Descriptions Bit Field Name Field Type Default Value Description FFO_UNIT 15 14 R O 0 Input clock FFO unit enumeration 0 1 ppb 1 10 ppb 2 100 ppb 3 1 ppm FFO 13 0 R O 0 Signed 14 bit input clock fractional frequency offset Table 83 STATUS IN5_MON_FREQ_STATUS Bit Field Locations and Descriptions Offset Address Hex STATUS IN5_MON_FREQ_STATUS Bit Field Locations D7 D6 D5 D4 D3 D2 D1 D0 096h FFO 7 ...

Page 80: ...ld Descriptions Bit Field Name Field Type Default Value Description FFO_UNIT 15 14 R O 0 Input clock FFO unit enumeration 0 1 ppb 1 10 ppb 2 100 ppb 3 1 ppm FFO 13 0 R O 0 Signed 14 bit input clock fractional frequency offset Table 85 STATUS IN7_MON_FREQ_STATUS Bit Field Locations and Descriptions Offset Address Hex STATUS IN7_MON_FREQ_STATUS Bit Field Locations D7 D6 D5 D4 D3 D2 D1 D0 09Ah FFO 7 ...

Page 81: ...ld Descriptions Bit Field Name Field Type Default Value Description FFO_UNIT 15 14 R O 0 Input clock FFO unit enumeration 0 1 ppb 1 10 ppb 2 100 ppb 3 1 ppm FFO 13 0 R O 0 Signed 14 bit input clock fractional frequency offset Table 87 STATUS IN9_MON_FREQ_STATUS Bit Field Locations and Descriptions Offset Address Hex STATUS IN9_MON_FREQ_STATUS Bit Field Locations D7 D6 D5 D4 D3 D2 D1 D0 09Eh FFO 7 ...

Page 82: ...ield Descriptions Bit Field Name Field Type Default Value Description FFO_UNIT 15 14 R O 0 Input clock FFO unit enumeration 0 1 ppb 1 10 ppb 2 100 ppb 3 1 ppm FFO 13 0 R O 0 Signed 14 bit input clock fractional frequency offset Table 89 STATUS IN11_MON_FREQ_STATUS Bit Field Locations and Descriptions Offset Address Hex STATUS IN11_MON_FREQ_STATUS Bit Field Locations D7 D6 D5 D4 D3 D2 D1 D0 0A2h FF...

Page 83: ...ield Descriptions Bit Field Name Field Type Default Value Description FFO_UNIT 15 14 R O 0 Input clock FFO unit enumeration 0 1 ppb 1 10 ppb 2 100 ppb 3 1 ppm FFO 13 0 R O 0 Signed 14 bit input clock fractional frequency offset Table 91 STATUS IN13_MON_FREQ_STATUS Bit Field Locations and Descriptions Offset Address Hex STATUS IN13_MON_FREQ_STATUS Bit Field Locations D7 D6 D5 D4 D3 D2 D1 D0 0A6h FF...

Page 84: ...ield Descriptions Bit Field Name Field Type Default Value Description FFO_UNIT 15 14 R O 0 Input clock FFO unit enumeration 0 1 ppb 1 10 ppb 2 100 ppb 3 1 ppm FFO 13 0 R O 0 Signed 14 bit input clock fractional frequency offset Table 93 STATUS IN15_MON_FREQ_STATUS Bit Field Locations and Descriptions Offset Address Hex STATUS IN15_MON_FREQ_STATUS Bit Field Locations D7 D6 D5 D4 D3 D2 D1 D0 0AAh FF...

Page 85: ...tput TDC is ready to be used Output TDC is by default disabled Need to enable with OUTPUT_TDC_CFG_GBL_2 enable After enabling it takes time for the output TDC clock to stabilize Output TDC is ready for use when in Ready state 0 disabled 1 initializing 2 ready Table 95 STATUS OUTPUT_TDC0_STATUS Bit Field Locations and Descriptions Offset Address Hex STATUS OUTPUT_TDC0_STATUS Bit Field Locations D7 ...

Page 86: ...ror condition encountered 0 disabled 1 idle 2 in progress 3 error invalid source target 4 error non uniform master divider freq 5 error start failed 6 error measurement timeout Table 96 STATUS OUTPUT_TDC1_STATUS Bit Field Locations and Descriptions Offset Address Hex STATUS OUTPUT_TDC1_STATUS Bit Field Locations D7 D6 D5 D4 D3 D2 D1 D0 0AEh VALID 7 RESERVED 6 4 STATUS 3 0 STATUS OUTPUT_TDC1_STATUS...

Page 87: ...ror condition encountered 0 disabled 1 idle 2 in progress 3 error invalid source target 4 error non uniform master divider freq 5 error start failed 6 error measurement timeout Table 97 STATUS OUTPUT_TDC2_STATUS Bit Field Locations and Descriptions Offset Address Hex STATUS OUTPUT_TDC2_STATUS Bit Field Locations D7 D6 D5 D4 D3 D2 D1 D0 0AFh VALID 7 RESERVED 6 4 STATUS 3 0 STATUS OUTPUT_TDC2_STATUS...

Page 88: ...ror condition encountered 0 disabled 1 idle 2 in progress 3 error invalid source target 4 error non uniform master divider freq 5 error start failed 6 error measurement timeout Table 98 STATUS OUTPUT_TDC3_STATUS Bit Field Locations and Descriptions Offset Address Hex STATUS OUTPUT_TDC3_STATUS Bit Field Locations D7 D6 D5 D4 D3 D2 D1 D0 0B0h VALID 7 RESERVED 6 4 STATUS 3 0 STATUS OUTPUT_TDC3_STATUS...

Page 89: ...bled 1 idle 2 in progress 3 error invalid source target 4 error non uniform master divider freq 5 error start failed 6 error measurement timeout Table 99 STATUS OUTPUT_TDC0_MEASUREMENT Bit Field Locations and Descriptions Offset Address Hex STATUS OUTPUT_TDC0_MEASUREMENT Bit Field Locations D7 D6 D5 D4 D3 D2 D1 D0 0B4h PHASE 7 0 0B5h PHASE 15 8 0B6h PHASE 23 16 0B7h PHASE 31 24 0B8h PHASE 39 32 0B...

Page 90: ...SE 39 32 0C9h PHASE 47 40 STATUS OUTPUT_TDC1_MEASUREMENT Bit Field Descriptions Bit Field Name Field Type Default Value Description PHASE 47 0 R O 0 Output TDC measurement Signed 48 bit integer in picoseconds Measurement sum of samples number of samples A sample is collected every 100us Positive value indicates the target edge leads the source edge i e source edge is to the left of the target edge...

Page 91: ...ource edge is to the left of the target edge Table 102 STATUS OUTPUT_TDC3_MEASUREMENT Bit Field Locations and Descriptions Offset Address Hex STATUS OUTPUT_TDC3_MEASUREMENT Bit Field Locations D7 D6 D5 D4 D3 D2 D1 D0 0D4h PHASE 7 0 0D5h PHASE 15 8 0D6h PHASE 23 16 0D7h PHASE 31 24 0D8h PHASE 39 32 0D9h PHASE 47 40 STATUS OUTPUT_TDC3_MEASUREMENT Bit Field Descriptions Bit Field Name Field Type Defa...

Page 92: ...Bit Field Descriptions Bit Field Name Field Type Default Value Description RESERVED N A This field must not be modified from the read value DPLL0_PHASE_STATUS 35 0 R O 0 Signed 36 bit phase offset in ITDC_UIs Table 104 STATUS DPLL1_PHASE_STATUS Bit Field Locations and Descriptions Offset Address Hex STATUS DPLL1_PHASE_STATUS Bit Field Locations D7 D6 D5 D4 D3 D2 D1 D0 0E4h DPLL1_PHASE_STATUS 7 0 0...

Page 93: ...Bit Field Descriptions Bit Field Name Field Type Default Value Description RESERVED N A This field must not be modified from the read value DPLL2_PHASE_STATUS 35 0 R O 0 Signed 36 bit phase offset in ITDC_UIs Table 106 STATUS DPLL3_PHASE_STATUS Bit Field Locations and Descriptions Offset Address Hex STATUS DPLL3_PHASE_STATUS Bit Field Locations D7 D6 D5 D4 D3 D2 D1 D0 0F4h DPLL3_PHASE_STATUS 7 0 0...

Page 94: ...Bit Field Descriptions Bit Field Name Field Type Default Value Description RESERVED N A This field must not be modified from the read value DPLL4_PHASE_STATUS 35 0 R O 0 Signed 36 bit phase offset in ITDC_UIs Table 108 STATUS DPLL5_PHASE_STATUS Bit Field Locations and Descriptions Offset Address Hex STATUS DPLL5_PHASE_STATUS Bit Field Locations D7 D6 D5 D4 D3 D2 D1 D0 104h DPLL5_PHASE_STATUS 7 0 1...

Page 95: ...Bit Field Descriptions Bit Field Name Field Type Default Value Description RESERVED N A This field must not be modified from the read value DPLL6_PHASE_STATUS 35 0 R O 0 Signed 36 bit phase offset in ITDC_UIs Table 110 STATUS DPLL7_PHASE_STATUS Bit Field Locations and Descriptions Offset Address Hex STATUS DPLL7_PHASE_STATUS Bit Field Locations D7 D6 D5 D4 D3 D2 D1 D0 114h DPLL7_PHASE_STATUS 7 0 1...

Page 96: ...l remaining time is between remaining_time and remaining_time 1 seconds If the value 255 it implies the actual remaining time 255 seconds Table 112 STATUS DPLL1_PHASE_PULL_IN_STATUS Bit Field Locations and Descriptions Offset Address Hex STATUS DPLL1_PHASE_PULL_IN_STATUS Bit Field Locations D7 D6 D5 D4 D3 D2 D1 D0 11Dh REMAINING_TIME 7 0 STATUS DPLL1_PHASE_PULL_IN_STATUS Bit Field Descriptions Bit...

Page 97: ... 11Fh REMAINING_TIME 7 0 STATUS DPLL3_PHASE_PULL_IN_STATUS Bit Field Descriptions Bit Field Name Field Type Default Value Description REMAINING_TIME 7 0 R O 0 Unsigned 8 bit phase pull in time to finish in seconds If the value of this field 255 the actual remaining time is between remaining_time and remaining_time 1 seconds If the value 255 it implies the actual remaining time 255 seconds Table 11...

Page 98: ...l remaining time is between remaining_time and remaining_time 1 seconds If the value 255 it implies the actual remaining time 255 seconds Table 117 STATUS DPLL6_PHASE_PULL_IN_STATUS Bit Field Locations and Descriptions Offset Address Hex STATUS DPLL6_PHASE_PULL_IN_STATUS Bit Field Locations D7 D6 D5 D4 D3 D2 D1 D0 122h REMAINING_TIME 7 0 STATUS DPLL6_PHASE_PULL_IN_STATUS Bit Field Descriptions Bit...

Page 99: ...USER_CONTROL GPIO0_TO_7_OUT GPIO output control 001h GPIO_USER_CONTROL GPIO8_TO_15_OUT GPIO output control Table 120 GPIO_USER_CONTROL GPIO0_TO_7_OUT Bit Field Locations and Descriptions Offset Address Hex GPIO_USER_CONTROL GPIO0_TO_7_OUT Bit Field Locations D7 D6 D5 D4 D3 D2 D1 D0 000h GPIO7_DRIV E_LEVEL 7 GPIO6_DRIV E_LEVEL 6 GPIO5_DRIV E_LEVEL 5 GPIO4_DRIV E_LEVEL 4 GPIO3_DRIV E_LEVEL 3 GPIO2_D...

Page 100: ...pin 2 drive level Valid only if GPIO_FUNCTION is disabled and gpio_control_dir is output 0 drive low 1 drive high GPIO1_DRIVE_LEVEL 1 R W 0 GPIO pin 1 drive level Valid only if GPIO_FUNCTION is disabled and gpio_control_dir is output 0 drive low 1 drive high GPIO0_DRIVE_LEVEL 0 R W 0 GPIO pin 0 drive level Valid only if GPIO_FUNCTION is disabled and gpio_control_dir is output 0 drive low 1 drive h...

Page 101: ...PIO13_DRIVE_LEVEL 5 R W 0 GPIO pin 13 drive level Valid only if GPIO_FUNCTION is disabled and gpio_control_dir is output 0 drive low 1 drive high GPIO12_DRIVE_LEVEL 4 R W 0 GPIO pin 12 drive level Valid only if GPIO_FUNCTION is disabled and gpio_control_dir is output 0 drive low 1 drive high GPIO11_DRIVE_LEVEL 3 R W 0 GPIO pin 11 drive level Valid only if GPIO_FUNCTION is disabled and gpio_control...

Page 102: ...ICKY_STATUS_CLEAR ALL_STICKY_STAT US_CLEAR Clear all sticky status bits Table 123 STICKY_STATUS_CLEAR IN0_TO_7_MON_STICKY_STATUS_CLEAR Bit Field Locations and Descriptions Offset Address Hex STICKY_STATUS_CLEAR IN0_TO_7_MON_STICKY_STATUS_CLEAR Bit Field Locations D7 D6 D5 D4 D3 D2 D1 D0 000h IN7_MON_S TICKY_CLE AR 7 IN6_MON_S TICKY_CLE AR 6 IN5_MON_S TICKY_CLE AR 5 IN4_MON_S TICKY_CLE AR 4 IN3_MON...

Page 103: ...MON_ STICKY_CL EAR 3 IN10_MON_ STICKY_CL EAR 2 IN9_MON_S TICKY_CLE AR 1 IN8_MON_S TICKY_CLE AR 0 STICKY_STATUS_CLEAR IN8_TO_15_MON_STICKY_STATUS_CLEAR Bit Field Descriptions Bit Field Name Field Type Default Value Description IN15_MON_STICKY_CLE AR 7 RW1C 0 Write 1 to clear the sticky bits of input 15 IN14_MON_STICKY_CLE AR 6 RW1C 0 Write 1 to clear the sticky bits of input 14 IN13_MON_STICKY_CLE ...

Page 104: ...TUS_CLEAR Bit Field Descriptions Bit Field Name Field Type Default Value Description DPLL7_STICKY_CLEAR 7 RW1C 0 Write 1 to clear the sticky bits of DPLL 7 DPLL6_STICKY_CLEAR 6 RW1C 0 Write 1 to clear the sticky bits of DPLL 6 DPLL5_STICKY_CLEAR 5 RW1C 0 Write 1 to clear the sticky bits of DPLL 5 DPLL4_STICKY_CLEAR 4 RW1C 0 Write 1 to clear the sticky bits of DPLL 4 DPLL3_STICKY_CLEAR 3 RW1C 0 Wri...

Page 105: ...TATUS_CLEAR SYS_APLL_STICKY_STATUS_CLEAR Bit Field Locations D7 D6 D5 D4 D3 D2 D1 D0 004h RESERVED 7 1 SYS_APLL_ STICKY_CL EAR 0 STICKY_STATUS_CLEAR SYS_APLL_STICKY_STATUS_CLEAR Bit Field Descriptions Bit Field Name Field Type Default Value Description RESERVED N A This field must not be modified from the read value SYS_APLL_STICKY_CLE AR 0 RW1C 0 Write 1 to clear the sticky bit of system APLL Tab...

Page 106: ...x GPIO_TOD_NOTIFICATION_CLEAR GPIO0_TO_7_CLEAR Bit Field Locations D7 D6 D5 D4 D3 D2 D1 D0 000h GPIO7_CLE AR 7 GPIO6_CLE AR 6 GPIO5_CLE AR 5 GPIO4_CLE AR 4 GPIO3_CLE AR 3 GPIO2_CLE AR 2 GPIO1_CLE AR 1 GPIO0_CLE AR 0 GPIO_TOD_NOTIFICATION_CLEAR GPIO0_TO_7_CLEAR Bit Field Descriptions Bit Field Name Field Type Default Value Description GPIO7_CLEAR 7 RW1C 0 Write 1 to clear GPIO7 assertion GPIO6_CLEA...

Page 107: ...gister Description 000h ALERT_CFG IN1_0_MON_ALERT_MASK GPIO alert enable masks for reference monitors 0 and 1 001h ALERT_CFG IN3_2_MON_ALERT_MASK GPIO alert enable masks for reference monitors 2 and 3 002h ALERT_CFG IN5_4_MON_ALERT_MASK GPIO alert enable masks for reference monitors 4 and 5 003h ALERT_CFG IN7_6_MON_ALERT_MASK GPIO alert enable masks for reference monitors 6 and 7 004h ALERT_CFG IN...

Page 108: ...able mask If enabled GPIO alert becomes active when in1_freq_offs_lim_sticky bit is set 0 disabled 1 enabled IN1_NO_ACTIVITY_MASK 5 R W 0 Input 1 no activity enable mask If enabled GPIO alert becomes active when in1_no_activity_sticky bit is set 0 disabled 1 enabled IN1_LOS_MASK 4 R W 0 Input 1 LOS enable mask If enabled GPIO alert becomes active when in1_los_sticky bit is set 0 disabled 1 enabled...

Page 109: ...able mask If enabled GPIO alert becomes active when in3_freq_offs_lim_sticky bit is set 0 disabled 1 enabled IN3_NO_ACTIVITY_MASK 5 R W 0 Input 3 no activity enable mask If enabled GPIO alert becomes active when in3_no_activity_sticky bit is set 0 disabled 1 enabled IN3_LOS_MASK 4 R W 0 Input 3 LOS enable mask If enabled GPIO alert becomes active when in3_los_sticky bit is set 0 disabled 1 enabled...

Page 110: ...able mask If enabled GPIO alert becomes active when in5_freq_offs_lim_sticky bit is set 0 disabled 1 enabled IN5_NO_ACTIVITY_MASK 5 R W 0 Input 5 no activity enable mask If enabled GPIO alert becomes active when in5_no_activity_sticky bit is set 0 disabled 1 enabled IN5_LOS_MASK 4 R W 0 Input 5 LOS enable mask If enabled GPIO alert becomes active when in5_los_sticky bit is set 0 disabled 1 enabled...

Page 111: ...able mask If enabled GPIO alert becomes active when in7_freq_offs_lim_sticky bit is set 0 disabled 1 enabled IN7_NO_ACTIVITY_MASK 5 R W 0 Input 7 no activity enable mask If enabled GPIO alert becomes active when in7_no_activity_sticky bit is set 0 disabled 1 enabled IN7_LOS_MASK 4 R W 0 Input 7 LOS enable mask If enabled GPIO alert becomes active when in7_los_sticky bit is set 0 disabled 1 enabled...

Page 112: ...ble mask If enabled GPIO alert becomes active when in9_freq_offs_lim_sticky bit is set 0 disabled 1 enabled IN9_NO_ACTIVITY_MASK 5 R W 0 Input 9 no activity enable mask If enabled GPIO alert becomes active when in9_no_activity_sticky bit is set 0 disabled 1 enabled IN9_LOS_MASK 4 R W 0 Input 9 LOS enable mask If enabled GPIO alert becomes active when in9_los_sticky bit is set 0 disabled 1 enabled ...

Page 113: ...able mask If enabled GPIO alert becomes active when in11_freq_offs_lim_sticky bit is set 0 disabled 1 enabled IN11_NO_ACTIVITY_MAS K 5 R W 0 Input 11 no activity enable mask If enabled GPIO alert becomes active when in11_no_activity_sticky bit is set 0 disabled 1 enabled IN11_LOS_MASK 4 R W 0 Input 11 LOS enable mask If enabled GPIO alert becomes active when in11_los_sticky bit is set 0 disabled 1...

Page 114: ...able mask If enabled GPIO alert becomes active when in13_freq_offs_lim_sticky bit is set 0 disabled 1 enabled IN13_NO_ACTIVITY_MAS K 5 R W 0 Input 13 no activity enable mask If enabled GPIO alert becomes active when in13_no_activity_sticky bit is set 0 disabled 1 enabled IN13_LOS_MASK 4 R W 0 Input 13 LOS enable mask If enabled GPIO alert becomes active when in13_los_sticky bit is set 0 disabled 1...

Page 115: ...able mask If enabled GPIO alert becomes active when in15_freq_offs_lim_sticky bit is set 0 disabled 1 enabled IN15_NO_ACTIVITY_MAS K 5 R W 0 Input 15 no activity enable mask If enabled GPIO alert becomes active when in15_no_activity_sticky bit is set 0 disabled 1 enabled IN15_LOS_MASK 4 R W 0 Input 15 LOS enable mask If enabled GPIO alert becomes active when in15_los_sticky bit is set 0 disabled 1...

Page 116: ...pll3_holdover_state_change_sticky bit is set 0 disabled 1 enabled DPLL3_LOCK_MASK 6 R W 0 DPLL 3 lock state transition event enable mask If enabled GPIO alert becomes active when dpll3_lock_state_change_sticky bit is set 0 disabled 1 enabled DPLL2_HOLDOVER_MAS K 5 R W 0 DPLL 2 holdover state transition event enable mask If enabled GPIO alert becomes active when dpll2_holdover_state_change_sticky b...

Page 117: ...L DOVER_MA SK 7 DPLL7_LOC K_MASK 6 DPLL6_HOL DOVER_MA SK 5 DPLL6_LOC K_MASK 4 DPLL5_HOL DOVER_MA SK 3 DPLL5_LOC K_MASK 2 DPLL4_HOL DOVER_MA SK 1 DPLL4_LOC K_MASK 0 ALERT_CFG DPLL7_6_5_4_ALERT_MASK Bit Field Descriptions Bit Field Name Field Type Default Value Description DPLL7_HOLDOVER_MAS K 7 R W 0 DPLL 7 holdover state transition event enable mask If enabled GPIO alert becomes active when dpll7_...

Page 118: ..._LOCK_MASK 2 R W 0 DPLL 5 lock state transition event enable mask If enabled GPIO alert becomes active when dpll5_lock_state_change_sticky bit is set 0 disabled 1 enabled DPLL4_HOLDOVER_MAS K 1 R W 0 DPLL 4 holdover state transition event enable mask If enabled GPIO alert becomes active when dpll4_holdover_state_change_sticky bit is set 0 disabled 1 enabled DPLL4_LOCK_MASK 0 R W 0 DPLL 4 lock stat...

Page 119: ...SYS_APLL_LOSS_LOCK_ MASK 2 R W 0 System APLL loss lock event enable mask If enabled GPIO alert becomes active when sys_apll_loss_lock_sticky bit is set 0 disabled 1 enabled DPLL_SYS_HOLDOVER_ MASK 1 R W 0 System DPLL holdover transition event enable mask If enabled GPIO alert becomes active when dpll_sys_holdover_state_change_sticky bit is set 0 disabled 1 enabled DPLL_SYS_LOCK_MASK 0 R W 0 System...

Page 120: ...APLL Register Index Offset Hex Register Module Base Address C19Ch Individual Register Name Register Description 000h SYS_APLL SYS_APLL_CP_SS_CURRENT_1 System APLL charge pump current register 001h SYS_APLL SYS_APLL_CP_SS_CURRENT_2 System APLL charge pump current register 002h SYS_APLL SYS_APLL_CFG_1 System APLL configuration register 1 003h SYS_APLL SYS_APLL_CFG_2 System APLL configuration registe...

Page 121: ...this bit to apply the SCSR charge pump settings No changes will be applied while this bit is disabled RESERVED N A This field must not be modified from the read value CP_1_SS_CURRENT 5 3 R W 0 0x0 125uA 0x3 500uA 0x7 1000uA Reference current for Charge Pump 1 125uA steps For use in 3 3V VDDA operation cp_1_ss_current cp_2_ss_current cp_3_ss_current cp_4_ss_current total cp current used to set APLL...

Page 122: ...t Field Locations and Descriptions Offset Address Hex SYS_APLL SYS_APLL_CFG_1 Bit Field Locations D7 D6 D5 D4 D3 D2 D1 D0 002h PFD_FORCE _VC_LOW_C S 7 PFD_FORCE _VC_HIGH_ CS 6 CP_CS_OFF SET_ENABL E 5 XTAL_DOUB LE_CS 4 CP_CS_OTA _ENABLE 3 CP_CS_ENA BLE 2 PFD_RESET _CS 1 PFD_RESET _SS_1 0 SYS_APLL SYS_APLL_CFG_1 Bit Field Descriptions Bit Field Name Field Type Default Value Description PFD_FORCE_VC_...

Page 123: ... Type Default Value Description RESERVED N A This field must not be modified from the read value PFD_RESET_SS_2 6 R W 0 Reset to 3 3V source switching PFD 2 Reset must be high for 2 5V VDDA operation low for 3 3V VDDA operation CP_CS_500U_ENABLE 5 R W 0 Enable current steering charge pump 500uA gain control Enable 500uA current source for cs charge pump For use in 2 5V VDDA operation CP_CS_250U_EN...

Page 124: ...ster bit 0 When 1 PDCP and VCO regulators are set for 2 5V VDDA power supply application When 0 PDCP and VCO regulators are set for 3 3V VDDA application Table 152 SYS_APLL SYS_APLL_CP_CTRL_0 Bit Field Locations and Descriptions Offset Address Hex SYS_APLL SYS_APLL_CP_CTRL_0 Bit Field Locations D7 D6 D5 D4 D3 D2 D1 D0 005h CP_4_SS_E NABLE 7 CP_3_SS_E NABLE 6 CP_2_SS_E NABLE 5 CP_1_SS_E NABLE 4 SYS...

Page 125: ...ation 0 disabled 1 enabled SYS_APLL_CP_2_SS_500 U_ENABLE 1 R W 0 Enable source switching 500mA gain control for Charge Pump 2 For use in 3 3V VDDA operation 0 disabled 1 enabled SYS_APLL_CP_1_SS_500 U_ENABLE 0 R W 0 Enable source switching 500mA gain control for Charge Pump 1 For use in 3 3V VDDA operation 0 disabled 1 enabled Table 153 SYS_APLL SYS_APLL_CP_CTRL_1 Bit Field Locations and Descripti...

Page 126: ...use in 3 3V VDDA operation 0 disabled 1 enabled SYS_APLL_CP_1_SS_125 U_ENABLE 4 R W 0 Enable source switching 125mA gain control for Charge Pump 1 For use in 3 3V VDDA operation 0 disabled 1 enabled SYS_APLL_CP_4_SS_250 U_ENABLE 3 R W 0 Enable source switching 250mA gain control for Charge Pump 4 For use in 3 3V VDDA operation 0 disabled 1 enabled SYS_APLL_CP_3_SS_250 U_ENABLE 2 R W 0 Enable sourc...

Page 127: ..._ENABLE 7 R W 0 Enable source switching ota for Charge Pump 4 0 disabled 1 enabled SYS_APLL_CP_3_SS_OT A_ENABLE 6 R W 0 Enable source switching ota for Charge Pump 3 0 disabled 1 enabled SYS_APLL_CP_2_SS_OT A_ENABLE 5 R W 0 Enable source switching ota for Charge Pump 2 0 disabled 1 enabled SYS_APLL_CP_1_SS_OT A_ENABLE 4 R W 0 Enable source switching ota for Charge Pump 1 0 disabled 1 enabled SYS_A...

Page 128: ...h M 15 8 00Ah M 23 16 00Bh M 31 24 00Ch M 39 32 00Dh M 47 40 00Eh N 7 0 00Fh N 15 8 SYS_APLL SYS_APLL_XTAL_FREQ Bit Field Descriptions Bit Field Name Field Type Default Value Description N 15 0 R W 0 SYS_APLL crystal frequency N N is unsigned 16 bit N must not be configured to 0 M 47 0 R W 0 SYS_APLL crystal frequency M M is unsigned 48 bit Table 156 SYS_APLL SYS_APLL_CTRL Bit Field Locations and ...

Page 129: ... R W 0 Enable the crystal input frequency doubler Enable 1 Doubles the Input frequency of the SYS_APLL 0 disabled 1 enabled APLL_FBDIV_DIVIDER 13 0 R W 0 Feedback divider value Sets the divider value of the feedback divider Table 157 INPUT_0 Register Index Offset Hex Register Module Base Address C1B0ha a This register module is instantiated multiple times This is the base address of the first inst...

Page 130: ...03h M 31 24 004h M 39 32 005h M 47 40 006h N 7 0 007h N 15 8 INPUT_0 IN_FREQ Bit Field Descriptions Bit Field Name Field Type Default Value Description N 15 0 R W 0 Input frequency N N is unsigned 16 bit N must not be configured to 0 M 47 0 R W 0 Input frequency M M is unsigned 48 bit In differential mode maximum speed is 1 GHz In CMOS mode single ended maximum speed is 325 MHz Table 159 INPUT_0 I...

Page 131: ... to the DPLL is 200 MHz 0 and 1 both indicate bypass Table 160 INPUT_0 IN_PHASE Bit Field Locations and Descriptions Offset Address Hex INPUT_0 IN_PHASE Bit Field Locations D7 D6 D5 D4 D3 D2 D1 D0 00Ah IN_PHASE 7 0 00Bh IN_PHASE 15 8 INPUT_0 IN_PHASE Bit Field Descriptions Bit Field Name Field Type Default Value Description IN_PHASE 15 0 R W 0 Phase offset value Signed 16 bit phase offset value in...

Page 132: ...ns Bit Field Name Field Type Default Value Description FRAME_SYNC_PULSE_E N 7 R W 0 Enable or disable the frame pulse or sync pulse mode for this input Mode selection is determined by frame_sync_mode in SCSR_DPLL_CTRL_2 0 disabled 1 enabled FRAME_SYNC_RESAMPL E_EDGE 6 R W 0 Re sample edge selection 0 positive edge 1 negative edge ...

Page 133: ...ut that is a frame or sync pulse to this input Selects either the input clock or PPS from the PWM decoder Selecting itself puts the DPLL back to normal tracking mode i e not in frame pulse mode 0x00 CLK0 0x01 CLK1 0x02 CLK2 0x03 CLK3 0x04 CLK4 0x05 CLK5 0x06 CLK6 0x07 CLK7 0x08 CLK8 0x09 CLK9 0x0A CLK10 0x0B CLK11 0x0C CLK12 0x0D CLK13 0x0E CLK14 0x0F CLK15 0x10 PPS from PWM Decoder 0 0x11 PPS fro...

Page 134: ...abled in DPLL 0 pred0 1 pred1 MUX_GPIO_IN 6 R W 0 Select a GPIO pin to mux into the input divider instead of the input pin Only applicable to INPUT8 15 When set to 1 the following mapping applies GPIO0 pin INPUT8 GPIO15 pin INPUT9 GPIO14 pin INPUT10 GPIO13 pin INPUT11 GPIO12 pin INPUT12 GPIO11 pin INPUT13 GPIO10 pin INPUT14 GPIO3 pin INPUT15 Applied only on a per input module basis e g setting INP...

Page 135: ...address Individual Register Name Register Description 000h REF_MON_0 IN_MON_FREQ_CFG Reference monitor frequency configuration 001h REF_MON_0 IN_MON_FREQ_VLD_INTV Frequency validation short interval 002h REF_MON_0 IN_MON_TRANS_THRESHOLD Reference clock phase transient threshold 004h REF_MON_0 IN_MON_TRANS_PERIOD Reference clock phase transient detection period 006h REF_MON_0 IN_MON_ACT_CFG Activit...

Page 136: ...Frequency offset limit enumeration VLD_INTERVAL and FREQ_OFFS_LIM define the long term reference monitor parameters IN_MON_CFG MASK_FREQ enables disables the long term reference monitor 0 9 2 ppm A 12 ppm R 1 13 8 ppm A 18 ppm R 2 24 6 ppm A 32 ppm R 3 36 6 ppm A 47 5 ppm R 4 40 ppm A 52 ppm R 5 52 ppm A 67 5 ppm R 6 64 ppm A 83 ppm R 7 100 pm A 130 ppm R Table 165 REF_MON_0 IN_MON_FREQ_VLD_INTV B...

Page 137: ...criptions Bit Field Name Field Type Default Value Description IN_MON_TRANS_THRES HOLD 15 0 R W 0 Reference phase transient detection threshold in nanoseconds Table 167 REF_MON_0 IN_MON_TRANS_PERIOD Bit Field Locations and Descriptions Offset Address Hex REF_MON_0 IN_MON_TRANS_PERIOD Bit Field Locations D7 D6 D5 D4 D3 D2 D1 D0 004h IN_MON_TRANS_PERIOD 7 0 005h IN_MON_TRANS_PERIOD 15 8 REF_MON_0 IN_...

Page 138: ...3 50 ms ACT_LIM 2 0 R W 0 Activity limit 1000 ppm to 12 ppm 0 1000 ppm 1 260 ppm 2 130 ppm 3 83 ppm 4 65 ppm 5 52 ppm 6 18 ppm 7 12 ppm Table 169 REF_MON_0 IN_MON_LOS_TOLERANCE Bit Field Locations and Descriptions Offset Address Hex REF_MON_0 IN_MON_LOS_TOLERANCE Bit Field Locations D7 D6 D5 D4 D3 D2 D1 D0 008h IN_MON_LOS_TOLERANCE 7 0 009h IN_MON_LOS_TOLERANCE 15 8 REF_MON_0 IN_MON_LOS_TOLERANCE ...

Page 139: ...ON_LOS_CFG Bit Field Descriptions Bit Field Name Field Type Default Value Description RESERVED N A This field must not be modified from the read value LOS_GAP 2 1 R W 0 Number consecutive missing clocks to declare LOS 0 means short term monitor will use LOS_MARGIN to detect LOS 0 LOS gap disabled 1 1 2 2 3 5 LOS_MARGIN 0 R W 0 Configure the LOS detection margin Tight margin aims for 1 freq error L...

Page 140: ...qualification or disqualification 0 excluded 1 included MASK_LOS 1 R W 0 Include or exclude LOS from reference qualification or disqualification 0 excluded 1 included EN 0 R W 0 Enable or disable reference monitor When disabled and the corresponding input clock is enabled this input is always qualified to be a reference When enabled and MASK_ACTIVITY 0 MASK_FREQ 0 and MASK_LOS 0 this input is alwa...

Page 141: ...nput for priority 6 016h DPLL_0 DPLL_REF_PRIORITY_7 Select input for priority 7 017h DPLL_0 DPLL_REF_PRIORITY_8 Select input for priority 8 018h DPLL_0 DPLL_REF_PRIORITY_9 Select input for priority 9 019h DPLL_0 DPLL_REF_PRIORITY_10 Select input for priority 10 01Ah DPLL_0 DPLL_REF_PRIORITY_11 Select input for priority 11 01Bh DPLL_0 DPLL_REF_PRIORITY_12 Select input for priority 12 01Ch DPLL_0 DP...

Page 142: ...DPLL_PHASE_MEASUREMENT_CFG Phase measurement mode configuration 037h DPLL_0 DPLL_MODE DPLL operating modes a This register module is instantiated multiple times This is the base address of the first instantiation of this module For later instantiations use the appropriate module base address Table 173 DPLL_0 DPLL_DCO_INC_DEC_SIZE Bit Field Locations and Descriptions Offset Address Hex DPLL_0 DPLL_...

Page 143: ...K0 0x01 CLK1 0x02 CLK2 0x03 CLK3 0x04 CLK4 0x05 CLK5 0x06 CLK6 0x07 CLK7 0x08 CLK8 0x09 CLK9 0x0A CLK10 0x0B CLK11 0x0C CLK12 0x0D CLK13 0x0E CLK14 0x0F CLK15 0x10 write phase input 0x11 write frequency input NA in this mode 0x12 XO_DPLL GLOBAL_SYNC_EN 2 R W 0 Enable global sync trigger to synchronize multiple DPLLs When this bit is set to 1 the phase of this DPLL s outputs will be aligned with th...

Page 144: ...on RESERVED N A This field must not be modified from the read value FB_SELECT_REF 4 1 R W 0 Feedback from other DPLL selected as reference for this DPLL Select other DPLL feedback to be used as reference for this DPLL 0 fb clk of DPLL 0 1 fb clk of DPLL 1 2 fb clk of DPLL 2 3 fb clk of DPLL 3 4 fb clk of DPLL 4 5 fb clk of DPLL 5 6 fb clk of DPLL 6 7 fb clk of DPLL 7 8 fb clk of SYS DPLL FB_SELECT...

Page 145: ...al feedback must be the same frequency as ALL input references that this DPLL locks to If INPUT_n IN_MODE MUX_GPIO_IN 1 then the corresponding GPIO to input pin mapping is in effect Ex When INPUT_0 IN_MODE MUX_GPIO_IN 1 then INPUT8 is replaced with the signal from GPIO 0 0x0 Input 0 0x1 Input 1 0x2 Input 2 0x3 Input 3 0x4 Input 4 0x5 Input 5 0x6 Input 6 0x7 Input 7 0x8 Input 8 GPIO 0 0x9 Input 9 G...

Page 146: ...s Offset Address Hex DPLL_0 DPLL_FILTER_STATUS_UPDATE_CFG Bit Field Locations D7 D6 D5 D4 D3 D2 D1 D0 006h RESERVED 7 3 FILTER_STA TUS_UPDAT E_EN 2 FILTER_STATUS_SELECT_ CNFG 1 0 DPLL_0 DPLL_FILTER_STATUS_UPDATE_CFG Bit Field Descriptions Bit Field Name Field Type Default Value Description RESERVED N A This field must not be modified from the read value FILTER_STATUS_UPDAT E_EN 2 R W 0 DPLL loop f...

Page 147: ... DPLL_HO_ADVCD_BW Bit Field Locations and Descriptions Offset Address Hex DPLL_0 DPLL_HO_ADVCD_BW Bit Field Locations D7 D6 D5 D4 D3 D2 D1 D0 008h DPLL_HO_ADVCD_BW 7 0 009h BW_UNIT 15 14 DPLL_HO_ADVCD_BW 13 8 DPLL_0 DPLL_HO_ADVCD_BW Bit Field Descriptions Bit Field Name Field Type Default Value Description BW_UNIT 15 14 R W 0 DPLL advanced holdover bandwidth unit 0 uHz 1 mHz 2 Hz 3 kHz DPLL_HO_ADV...

Page 148: ..._VALUE advanced holds DPLL with value derived from filtered DPLL frequency history 0 simple 1 manual 2 advanced Table 182 DPLL_0 DPLL_LOCK_0 Bit Field Locations and Descriptions Offset Address Hex DPLL_0 DPLL_LOCK_0 Bit Field Locations D7 D6 D5 D4 D3 D2 D1 D0 00Bh PHASE_UNIT 7 6 PHASE_LOCK_MAX_ERROR 5 0 DPLL_0 DPLL_LOCK_0 Bit Field Descriptions Bit Field Name Field Type Default Value Description P...

Page 149: ...D4 D3 D2 D1 D0 00Dh FFO_UNIT 7 6 FFO_LOCK_MAX_ERROR 5 0 DPLL_0 DPLL_LOCK_2 Bit Field Descriptions Bit Field Name Field Type Default Value Description FFO_UNIT 7 6 R W 0 FFO error unit 0 1 ppb 1 10 ppb 2 100 ppb 3 1 ppm FFO_LOCK_MAX_ERROR 5 0 R W 0 Integer maximum FFO error for lock criteria If 0 then Fractional Frequency Offset check is disabled Table 185 DPLL_0 DPLL_LOCK_3 Bit Field Locations and...

Page 150: ... Default Value Description PRIORITY_GROUP_NUM BER 7 6 R W 0 Priority group number Used to group multiple clocks as equal priority References in the same priority group number use non revertive switching PRIORITY_REF 5 1 R W 0 Input reference index for priority 0 0x00 CLK0 0x01 CLK1 0x02 CLK2 0x03 CLK3 0x04 CLK4 0x05 CLK5 0x06 CLK6 0x07 CLK7 0x08 CLK8 0x09 CLK9 0x0A CLK10 0x0B CLK11 0x0C CLK12 0x0D...

Page 151: ...ield Descriptions Bit Field Name Field Type Default Value Description PRIORITY_GROUP_NUM BER 7 6 R W 0 Priority group number For references in the same priority group revertive switching is disabled PRIORITY_REF 5 1 R W 0 Input reference index for priority 1 0x00 CLK0 0x01 CLK1 0x02 CLK2 0x03 CLK3 0x04 CLK4 0x05 CLK5 0x06 CLK6 0x07 CLK7 0x08 CLK8 0x09 CLK9 0x0A CLK10 0x0B CLK11 0x0C CLK12 0x0D CLK...

Page 152: ...ield Descriptions Bit Field Name Field Type Default Value Description PRIORITY_GROUP_NUM BER 7 6 R W 0 Priority group number For references in the same priority group revertive switching is disabled PRIORITY_REF 5 1 R W 0 Input reference index for priority 2 0x00 CLK0 0x01 CLK1 0x02 CLK2 0x03 CLK3 0x04 CLK4 0x05 CLK5 0x06 CLK6 0x07 CLK7 0x08 CLK8 0x09 CLK9 0x0A CLK10 0x0B CLK11 0x0C CLK12 0x0D CLK...

Page 153: ...ield Descriptions Bit Field Name Field Type Default Value Description PRIORITY_GROUP_NUM BER 7 6 R W 0 Priority group number For references in the same priority group revertive switching is disabled PRIORITY_REF 5 1 R W 0 Input reference index for priority 3 0x00 CLK0 0x01 CLK1 0x02 CLK2 0x03 CLK3 0x04 CLK4 0x05 CLK5 0x06 CLK6 0x07 CLK7 0x08 CLK8 0x09 CLK9 0x0A CLK10 0x0B CLK11 0x0C CLK12 0x0D CLK...

Page 154: ...ield Descriptions Bit Field Name Field Type Default Value Description PRIORITY_GROUP_NUM BER 7 6 R W 0 Priority group number For references in the same priority group revertive switching is disabled PRIORITY_REF 5 1 R W 0 Input reference index for priority 4 0x00 CLK0 0x01 CLK1 0x02 CLK2 0x03 CLK3 0x04 CLK4 0x05 CLK5 0x06 CLK6 0x07 CLK7 0x08 CLK8 0x09 CLK9 0x0A CLK10 0x0B CLK11 0x0C CLK12 0x0D CLK...

Page 155: ...ield Descriptions Bit Field Name Field Type Default Value Description PRIORITY_GROUP_NUM BER 7 6 R W 0 Priority group number For references in the same priority group revertive switching is disabled PRIORITY_REF 5 1 R W 0 Input reference index for priority 5 0x00 CLK0 0x01 CLK1 0x02 CLK2 0x03 CLK3 0x04 CLK4 0x05 CLK5 0x06 CLK6 0x07 CLK7 0x08 CLK8 0x09 CLK9 0x0A CLK10 0x0B CLK11 0x0C CLK12 0x0D CLK...

Page 156: ...ield Descriptions Bit Field Name Field Type Default Value Description PRIORITY_GROUP_NUM BER 7 6 R W 0 Priority group number For references in the same priority group revertive switching is disabled PRIORITY_REF 5 1 R W 0 Input reference index for priority 6 0x00 CLK0 0x01 CLK1 0x02 CLK2 0x03 CLK3 0x04 CLK4 0x05 CLK5 0x06 CLK6 0x07 CLK7 0x08 CLK8 0x09 CLK9 0x0A CLK10 0x0B CLK11 0x0C CLK12 0x0D CLK...

Page 157: ...ield Descriptions Bit Field Name Field Type Default Value Description PRIORITY_GROUP_NUM BER 7 6 R W 0 Priority group number For references in the same priority group revertive switching is disabled PRIORITY_REF 5 1 R W 0 Input reference index for priority 7 0x00 CLK0 0x01 CLK1 0x02 CLK2 0x03 CLK3 0x04 CLK4 0x05 CLK5 0x06 CLK6 0x07 CLK7 0x08 CLK8 0x09 CLK9 0x0A CLK10 0x0B CLK11 0x0C CLK12 0x0D CLK...

Page 158: ...ield Descriptions Bit Field Name Field Type Default Value Description PRIORITY_GROUP_NUM BER 7 6 R W 0 Priority group number For references in the same priority group revertive switching is disabled PRIORITY_REF 5 1 R W 0 Input reference index for priority 8 0x00 CLK0 0x01 CLK1 0x02 CLK2 0x03 CLK3 0x04 CLK4 0x05 CLK5 0x06 CLK6 0x07 CLK7 0x08 CLK8 0x09 CLK9 0x0A CLK10 0x0B CLK11 0x0C CLK12 0x0D CLK...

Page 159: ...ield Descriptions Bit Field Name Field Type Default Value Description PRIORITY_GROUP_NUM BER 7 6 R W 0 Priority group number For references in the same priority group revertive switching is disabled PRIORITY_REF 5 1 R W 0 Input reference index for priority 9 0x00 CLK0 0x01 CLK1 0x02 CLK2 0x03 CLK3 0x04 CLK4 0x05 CLK5 0x06 CLK6 0x07 CLK7 0x08 CLK8 0x09 CLK9 0x0A CLK10 0x0B CLK11 0x0C CLK12 0x0D CLK...

Page 160: ...ield Descriptions Bit Field Name Field Type Default Value Description PRIORITY_GROUP_NUM BER 7 6 R W 0 Priority group number For references in the same priority group revertive switching is disabled PRIORITY_REF 5 1 R W 0 Input reference index for priority 10 0x00 CLK0 0x01 CLK1 0x02 CLK2 0x03 CLK3 0x04 CLK4 0x05 CLK5 0x06 CLK6 0x07 CLK7 0x08 CLK8 0x09 CLK9 0x0A CLK10 0x0B CLK11 0x0C CLK12 0x0D CL...

Page 161: ...ield Descriptions Bit Field Name Field Type Default Value Description PRIORITY_GROUP_NUM BER 7 6 R W 0 Priority group number For references in the same priority group revertive switching is disabled PRIORITY_REF 5 1 R W 0 Input reference index for priority 11 0x00 CLK0 0x01 CLK1 0x02 CLK2 0x03 CLK3 0x04 CLK4 0x05 CLK5 0x06 CLK6 0x07 CLK7 0x08 CLK8 0x09 CLK9 0x0A CLK10 0x0B CLK11 0x0C CLK12 0x0D CL...

Page 162: ...ield Descriptions Bit Field Name Field Type Default Value Description PRIORITY_GROUP_NUM BER 7 6 R W 0 Priority group number For references in the same priority group revertive switching is disabled PRIORITY_REF 5 1 R W 0 Input reference index for priority 12 0x00 CLK0 0x01 CLK1 0x02 CLK2 0x03 CLK3 0x04 CLK4 0x05 CLK5 0x06 CLK6 0x07 CLK7 0x08 CLK8 0x09 CLK9 0x0A CLK10 0x0B CLK11 0x0C CLK12 0x0D CL...

Page 163: ...ield Descriptions Bit Field Name Field Type Default Value Description PRIORITY_GROUP_NUM BER 7 6 R W 0 Priority group number For references in the same priority group revertive switching is disabled PRIORITY_REF 5 1 R W 0 Input reference index for priority 13 0x00 CLK0 0x01 CLK1 0x02 CLK2 0x03 CLK3 0x04 CLK4 0x05 CLK5 0x06 CLK6 0x07 CLK7 0x08 CLK8 0x09 CLK9 0x0A CLK10 0x0B CLK11 0x0C CLK12 0x0D CL...

Page 164: ...ield Descriptions Bit Field Name Field Type Default Value Description PRIORITY_GROUP_NUM BER 7 6 R W 0 Priority group number For references in the same priority group revertive switching is disabled PRIORITY_REF 5 1 R W 0 Input reference index for priority 14 0x00 CLK0 0x01 CLK1 0x02 CLK2 0x03 CLK3 0x04 CLK4 0x05 CLK5 0x06 CLK6 0x07 CLK7 0x08 CLK8 0x09 CLK9 0x0A CLK10 0x0B CLK11 0x0C CLK12 0x0D CL...

Page 165: ...ield Descriptions Bit Field Name Field Type Default Value Description PRIORITY_GROUP_NUM BER 7 6 R W 0 Priority group number For references in the same priority group revertive switching is disabled PRIORITY_REF 5 1 R W 0 Input reference index for priority 15 0x00 CLK0 0x01 CLK1 0x02 CLK2 0x03 CLK3 0x04 CLK4 0x05 CLK5 0x06 CLK6 0x07 CLK7 0x08 CLK8 0x09 CLK9 0x0A CLK10 0x0B CLK11 0x0C CLK12 0x0D CL...

Page 166: ...ield Descriptions Bit Field Name Field Type Default Value Description PRIORITY_GROUP_NUM BER 7 6 R W 0 Priority group number For references in the same priority group revertive switching is disabled PRIORITY_REF 5 1 R W 0 Input reference index for priority 16 0x00 CLK0 0x01 CLK1 0x02 CLK2 0x03 CLK3 0x04 CLK4 0x05 CLK5 0x06 CLK6 0x07 CLK7 0x08 CLK8 0x09 CLK9 0x0A CLK10 0x0B CLK11 0x0C CLK12 0x0D CL...

Page 167: ...Field Descriptions Bit Field Name Field Type Default Value Description PRIORITY_GROUP_NUM BER 7 6 R W 0 Priority group number For references in the same priority group revertive switching is disabled PRIORITY_REF 5 1 R W 0 Input reference index for priority 17 0x00 CLK0 0x01 CLK1 0x02 CLK2 0x03 CLK3 0x04 CLK4 0x05 CLK5 0x06 CLK6 0x07 CLK7 0x08 CLK8 0x09 CLK9 0x0A CLK10 0x0B CLK11 0x0C CLK12 0x0D C...

Page 168: ...D3 D2 D1 D0 021h PRIORITY_GROUP_NUMBE R 7 6 PRIORITY_REF 5 1 PRIORITY_E N 0 DPLL_0 DPLL_REF_PRIORITY_18 Bit Field Descriptions Bit Field Name Field Type Default Value Description PRIORITY_GROUP_NUM BER 7 6 R W 0 Priority group number For references in the same priority group revertive switching is disabled PRIORITY_REF 5 1 R W 0 Input reference index for priority 18 0x00 CLK0 0x01 CLK1 0x02 CLK2 0...

Page 169: ...ec_phase_snap_en must also be enabled 0 disabled 1 enabled LOCK_REC_FAST_ACQ_ EN 6 R W 0 Enable fast acquisition stage for LOCKREC state During the fast acquisition stage the bandwidth is temporarily set to DPLL_FASTLOCK_BW to facilitate faster lock acquisition 0 disabled 1 enabled LOCK_REC_PHASE_SNA P_EN 5 R W 0 Enable phase snap for LOCKREC state When lock_rec_ol_pull_in_en is also enabled inste...

Page 170: ...t Field Locations D7 D6 D5 D4 D3 D2 D1 D0 024h PRE_FAST_ACQ_TIMER 7 4 DAMP_FTR 3 0 DPLL_0 DPLL_FASTLOCK_CFG_1 Bit Field Descriptions Bit Field Name Field Type Default Value Description PRE_FAST_ACQ_TIMER 7 4 R W 0 Pre fast acquisition stage timer If the value n 0 the DPLL opens up the bandwidth to the maximum for a duration of 2 n 1 milliseconds If the value n 0 then pre fast acquisition stage is ...

Page 171: ...bit maximum frequency offset limit in ppm Value 0 implies maximum of FFO limit of 244 ppm Table 208 DPLL_0 DPLL_FASTLOCK_PSL Bit Field Locations and Descriptions Offset Address Hex DPLL_0 DPLL_FASTLOCK_PSL Bit Field Locations D7 D6 D5 D4 D3 D2 D1 D0 026h DPLL_FASTLOCK_PSL 7 0 027h DPLL_FASTLOCK_PSL 15 8 DPLL_0 DPLL_FASTLOCK_PSL Bit Field Descriptions Bit Field Name Field Type Default Value Descrip...

Page 172: ... Locations and Descriptions Offset Address Hex DPLL_0 DPLL_FASTLOCK_BW Bit Field Locations D7 D6 D5 D4 D3 D2 D1 D0 02Ah DPLL_FASTLOCK_BW 7 0 02Bh BW_UNIT 15 14 DPLL_FASTLOCK_BW 13 8 DPLL_0 DPLL_FASTLOCK_BW Bit Field Descriptions Bit Field Name Field Type Default Value Description BW_UNIT 15 14 R W 0 Fast lock DPLL bandwidth unit 0 uHz 1 mHz 2 Hz 3 kHz DPLL_FASTLOCK_BW 13 0 R W 0 Unsigned 14 bit DP...

Page 173: ... DPLL_0 DPLL_WRITE_PHASE_TIMER Bit Field Locations and Descriptions Offset Address Hex DPLL_0 DPLL_WRITE_PHASE_TIMER Bit Field Locations D7 D6 D5 D4 D3 D2 D1 D0 02Eh WRITE_PHASE_TIMEOUT_CNFG 7 0 02Fh WRITE_PHASE_TIMEOUT_CNFG 15 8 DPLL_0 DPLL_WRITE_PHASE_TIMER Bit Field Descriptions Bit Field Name Field Type Default Value Description WRITE_PHASE_TIMEOU T_CNFG 15 0 R W 0 Unsigned 16 bit write phase ...

Page 174: ...4 DPLL_0 DPLL_TOD_SYNC_CFG Bit Field Locations and Descriptions Offset Address Hex DPLL_0 DPLL_TOD_SYNC_CFG Bit Field Locations D7 D6 D5 D4 D3 D2 D1 D0 031h RESERVED 7 3 TOD_SYNC_SOURCE 2 1 TOD_SYNC_ EN 0 DPLL_0 DPLL_TOD_SYNC_CFG Bit Field Descriptions Bit Field Name Field Type Default Value Description RESERVED N A This field must not be modified from the read value TOD_SYNC_SOURCE 2 1 R W 0 The ...

Page 175: ... Description RESERVED N A This field must not be modified from the read value PRI_COMBO_SRC_EN 5 R W 0 Enable this source 0 disabled 1 enabled PRI_COMBO_SRC_FILTE RED_CNFG 4 R W 0 Use filtered source 0 use un filtered source 1 use filtered source PRI_COMBO_SRC_ID 3 0 R W 0 Primary combo source DPLL index Table 216 DPLL_0 DPLL_COMBO_SLAVE_CFG_1 Bit Field Locations and Descriptions Offset Address He...

Page 176: ...SLAVE_REF_CFG Bit Field Locations D7 D6 D5 D4 D3 D2 D1 D0 034h RESERVED 7 5 SLAVE_REFERENCE 4 0 DPLL_0 DPLL_SLAVE_REF_CFG Bit Field Descriptions Bit Field Name Field Type Default Value Description RESERVED N A This field must not be modified from the read value SLAVE_REFERENCE 4 0 R W 0 Reference index used by DPLL when reference mode is slave or GPIO_slave 0x0 CLK0 0x1 CLK1 0x2 CLK2 0x3 CLK3 0x4 ...

Page 177: ...cles to calculate the phase offset retrigger DPLL_MODE to restart the phase measurement process Table 218 DPLL_0 DPLL_REF_MODE Bit Field Locations and Descriptions Offset Address Hex DPLL_0 DPLL_REF_MODE Bit Field Locations D7 D6 D5 D4 D3 D2 D1 D0 035h RESERVED 7 4 MODE 3 0 DPLL_0 DPLL_REF_MODE Bit Field Descriptions Bit Field Name Field Type Default Value Description RESERVED N A This field must ...

Page 178: ...elect the feedback clock going into the phase detector The feedback clock selected must have the same frequency as the reference clock selected 0x0 CLK0 0x1 CLK1 0x2 CLK2 0x3 CLK3 0x4 CLK4 0x5 CLK5 0x6 CLK6 0x7 CLK7 0x8 CLK8 0x9 CLK9 0xA CLK10 0xB CLK11 0xC CLK12 0xD CLK13 0xE CLK14 0xF CLK15 PFD_REF_CLK_SEL 3 0 R W 0 Select the reference clock going into the phase detector The reference clock sel...

Page 179: ...ame Field Type Default Value Description RESERVED N A This field must not be modified from the read value WRITE_TIMER_MODE 6 R W 0 Write phase or write frequency timer mode This bit selects simple holdover or advanced holdover for DPLL once the write timer expires 0 simple holdover mode 1 advanced holdover mode PLL_MODE 5 3 R W 0 DPLL operation mode 0 PLL mode 1 write phase mode 2 write frequency ...

Page 180: ...Select input for priority 1 009h SYS_DPLL SYS_DPLL_REF_PRIORITY_2 Select input for priority 2 00Ah SYS_DPLL SYS_DPLL_REF_PRIORITY_3 Select input for priority 3 00Bh SYS_DPLL SYS_DPLL_REF_PRIORITY_4 Select input for priority 4 00Ch SYS_DPLL SYS_DPLL_REF_PRIORITY_5 Select input for priority 5 00Dh SYS_DPLL SYS_DPLL_REF_PRIORITY_6 Select input for priority 6 00Eh SYS_DPLL SYS_DPLL_REF_PRIORITY_7 Sele...

Page 181: ...PLL SYS_DPLL_CTRL_0 Bit Field Descriptions Bit Field Name Field Type Default Value Description FORCE_LOCK_INPUT 7 3 R W 0 System DPLL reference input index when force lock applied 0x00 CLK0 0x01 CLK1 0x02 CLK2 0x03 CLK3 0x04 CLK4 0x05 CLK5 0x06 CLK6 0x07 CLK7 0x08 CLK8 0x09 CLK9 0x0A CLK10 0x0B CLK11 0x0C CLK12 0x0D CLK13 0x0E CLK14 0x0F CLK15 0x12 XO_DPLL REVERTIVE_EN 1 R W 0 Enable revertive mod...

Page 182: ...ress Hex SYS_DPLL SYS_DPLL_FILTER_STATUS_UPDATE_CFG Bit Field Locations D7 D6 D5 D4 D3 D2 D1 D0 002h RESERVED 7 3 FILTER_STA TUS_UPDAT E_EN 2 FILTER_STATUS_SELECT_ CNFG 1 0 SYS_DPLL SYS_DPLL_FILTER_STATUS_UPDATE_CFG Bit Field Descriptions Bit Field Name Field Type Default Value Description RESERVED N A This field must not be modified from the read value FILTER_STATUS_UPDAT E_EN 2 R W 0 System DPLL...

Page 183: ...actional Frequency Offset check is disabled Table 226 SYS_DPLL SYS_DPLL_LOCK_1 Bit Field Locations and Descriptions Offset Address Hex SYS_DPLL SYS_DPLL_LOCK_1 Bit Field Locations D7 D6 D5 D4 D3 D2 D1 D0 004h PHASE_MON_DUR 7 0 SYS_DPLL SYS_DPLL_LOCK_1 Bit Field Descriptions Bit Field Name Field Type Default Value Description PHASE_MON_DUR 7 0 R W 0 Duration of phase error monitoring before lock is...

Page 184: ...nal Frequency Offset check is disabled Table 228 SYS_DPLL SYS_DPLL_LOCK_3 Bit Field Locations and Descriptions Offset Address Hex SYS_DPLL SYS_DPLL_LOCK_3 Bit Field Locations D7 D6 D5 D4 D3 D2 D1 D0 006h FFO_MON_DUR 7 0 SYS_DPLL SYS_DPLL_LOCK_3 Bit Field Descriptions Bit Field Name Field Type Default Value Description FFO_MON_DUR 7 0 R W 0 Duration of FFO error monitoring before lock declared seco...

Page 185: ...evertive switching PRIORITY_REF 5 1 R W 0 Input reference index for priority 0 0x00 CLK0 0x01 CLK1 0x02 CLK2 0x03 CLK3 0x04 CLK4 0x05 CLK5 0x06 CLK6 0x07 CLK7 0x08 CLK8 0x09 CLK9 0x0A CLK10 0x0B CLK11 0x0C CLK12 0x0D CLK13 0x0E CLK14 0x0F CLK15 0x12 XO_DPLL PRIORITY_EN 0 R W 0 Enable reference priority 0 Enable reference priority 0 for the automatic reference selection 0 disabled 1 enabled Table 2...

Page 186: ...RITY_REF 5 1 R W 0 Input reference index for priority 1 0x00 CLK0 0x01 CLK1 0x02 CLK2 0x03 CLK3 0x04 CLK4 0x05 CLK5 0x06 CLK6 0x07 CLK7 0x08 CLK8 0x09 CLK9 0x0A CLK10 0x0B CLK11 0x0C CLK12 0x0D CLK13 0x0E CLK14 0x0F CLK15 0x12 XO_DPLL PRIORITY_EN 0 R W 0 Enable reference priority 1 Enable reference priority 1 for the automatic reference selection 0 disabled 1 enabled Table 231 SYS_DPLL SYS_DPLL_RE...

Page 187: ...RITY_REF 5 1 R W 0 Input reference index for priority 2 0x00 CLK0 0x01 CLK1 0x02 CLK2 0x03 CLK3 0x04 CLK4 0x05 CLK5 0x06 CLK6 0x07 CLK7 0x08 CLK8 0x09 CLK9 0x0A CLK10 0x0B CLK11 0x0C CLK12 0x0D CLK13 0x0E CLK14 0x0F CLK15 0x12 XO_DPLL PRIORITY_EN 0 R W 0 Enable reference priority 2 Enable reference priority 2 for the automatic reference selection 0 disabled 1 enabled Table 232 SYS_DPLL SYS_DPLL_RE...

Page 188: ...RITY_REF 5 1 R W 0 Input reference index for priority 3 0x00 CLK0 0x01 CLK1 0x02 CLK2 0x03 CLK3 0x04 CLK4 0x05 CLK5 0x06 CLK6 0x07 CLK7 0x08 CLK8 0x09 CLK9 0x0A CLK10 0x0B CLK11 0x0C CLK12 0x0D CLK13 0x0E CLK14 0x0F CLK15 0x12 XO_DPLL PRIORITY_EN 0 R W 0 Enable reference priority 3 Enable reference priority 3 for the automatic reference selection 0 disabled 1 enabled Table 233 SYS_DPLL SYS_DPLL_RE...

Page 189: ...RITY_REF 5 1 R W 0 Input reference index for priority 4 0x00 CLK0 0x01 CLK1 0x02 CLK2 0x03 CLK3 0x04 CLK4 0x05 CLK5 0x06 CLK6 0x07 CLK7 0x08 CLK8 0x09 CLK9 0x0A CLK10 0x0B CLK11 0x0C CLK12 0x0D CLK13 0x0E CLK14 0x0F CLK15 0x12 XO_DPLL PRIORITY_EN 0 R W 0 Enable reference priority 4 Enable reference priority 4 for the automatic reference selection 0 disabled 1 enabled Table 234 SYS_DPLL SYS_DPLL_RE...

Page 190: ...RITY_REF 5 1 R W 0 Input reference index for priority 5 0x00 CLK0 0x01 CLK1 0x02 CLK2 0x03 CLK3 0x04 CLK4 0x05 CLK5 0x06 CLK6 0x07 CLK7 0x08 CLK8 0x09 CLK9 0x0A CLK10 0x0B CLK11 0x0C CLK12 0x0D CLK13 0x0E CLK14 0x0F CLK15 0x12 XO_DPLL PRIORITY_EN 0 R W 0 Enable reference priority 5 Enable reference priority 5 for the automatic reference selection 0 disabled 1 enabled Table 235 SYS_DPLL SYS_DPLL_RE...

Page 191: ...RITY_REF 5 1 R W 0 Input reference index for priority 6 0x00 CLK0 0x01 CLK1 0x02 CLK2 0x03 CLK3 0x04 CLK4 0x05 CLK5 0x06 CLK6 0x07 CLK7 0x08 CLK8 0x09 CLK9 0x0A CLK10 0x0B CLK11 0x0C CLK12 0x0D CLK13 0x0E CLK14 0x0F CLK15 0x12 XO_DPLL PRIORITY_EN 0 R W 0 Enable reference priority 6 Enable reference priority 6 for the automatic reference selection 0 disabled 1 enabled Table 236 SYS_DPLL SYS_DPLL_RE...

Page 192: ...RITY_REF 5 1 R W 0 Input reference index for priority 7 0x00 CLK0 0x01 CLK1 0x02 CLK2 0x03 CLK3 0x04 CLK4 0x05 CLK5 0x06 CLK6 0x07 CLK7 0x08 CLK8 0x09 CLK9 0x0A CLK10 0x0B CLK11 0x0C CLK12 0x0D CLK13 0x0E CLK14 0x0F CLK15 0x12 XO_DPLL PRIORITY_EN 0 R W 0 Enable reference priority 7 Enable reference priority 7 for the automatic reference selection 0 disabled 1 enabled Table 237 SYS_DPLL SYS_DPLL_RE...

Page 193: ...RITY_REF 5 1 R W 0 Input reference index for priority 8 0x00 CLK0 0x01 CLK1 0x02 CLK2 0x03 CLK3 0x04 CLK4 0x05 CLK5 0x06 CLK6 0x07 CLK7 0x08 CLK8 0x09 CLK9 0x0A CLK10 0x0B CLK11 0x0C CLK12 0x0D CLK13 0x0E CLK14 0x0F CLK15 0x12 XO_DPLL PRIORITY_EN 0 R W 0 Enable reference priority 8 Enable reference priority 8 for the automatic reference selection 0 disabled 1 enabled Table 238 SYS_DPLL SYS_DPLL_RE...

Page 194: ...ITY_REF 5 1 R W 0 Input reference index for priority 9 0x00 CLK0 0x01 CLK1 0x02 CLK2 0x03 CLK3 0x04 CLK4 0x05 CLK5 0x06 CLK6 0x07 CLK7 0x08 CLK8 0x09 CLK9 0x0A CLK10 0x0B CLK11 0x0C CLK12 0x0D CLK13 0x0E CLK14 0x0F CLK15 0x12 XO_DPLL PRIORITY_EN 0 R W 0 Enable reference priority 9 Enable reference priority 9 for the automatic reference selection 0 disabled 1 enabled Table 239 SYS_DPLL SYS_DPLL_REF...

Page 195: ...TY_REF 5 1 R W 0 Input reference index for priority 10 0x00 CLK0 0x01 CLK1 0x02 CLK2 0x03 CLK3 0x04 CLK4 0x05 CLK5 0x06 CLK6 0x07 CLK7 0x08 CLK8 0x09 CLK9 0x0A CLK10 0x0B CLK11 0x0C CLK12 0x0D CLK13 0x0E CLK14 0x0F CLK15 0x12 XO_DPLL PRIORITY_EN 0 R W 0 Enable reference priority 10 Enable reference priority 10 for the automatic reference selection 0 disabled 1 enabled Table 240 SYS_DPLL SYS_DPLL_R...

Page 196: ...TY_REF 5 1 R W 0 Input reference index for priority 11 0x00 CLK0 0x01 CLK1 0x02 CLK2 0x03 CLK3 0x04 CLK4 0x05 CLK5 0x06 CLK6 0x07 CLK7 0x08 CLK8 0x09 CLK9 0x0A CLK10 0x0B CLK11 0x0C CLK12 0x0D CLK13 0x0E CLK14 0x0F CLK15 0x12 XO_DPLL PRIORITY_EN 0 R W 0 Enable reference priority 11 Enable reference priority 11 for the automatic reference selection 0 disabled 1 enabled Table 241 SYS_DPLL SYS_DPLL_R...

Page 197: ...TY_REF 5 1 R W 0 Input reference index for priority 12 0x00 CLK0 0x01 CLK1 0x02 CLK2 0x03 CLK3 0x04 CLK4 0x05 CLK5 0x06 CLK6 0x07 CLK7 0x08 CLK8 0x09 CLK9 0x0A CLK10 0x0B CLK11 0x0C CLK12 0x0D CLK13 0x0E CLK14 0x0F CLK15 0x12 XO_DPLL PRIORITY_EN 0 R W 0 Enable reference priority 12 Enable reference priority 12 for the automatic reference selection 0 disabled 1 enabled Table 242 SYS_DPLL SYS_DPLL_R...

Page 198: ...TY_REF 5 1 R W 0 Input reference index for priority 13 0x00 CLK0 0x01 CLK1 0x02 CLK2 0x03 CLK3 0x04 CLK4 0x05 CLK5 0x06 CLK6 0x07 CLK7 0x08 CLK8 0x09 CLK9 0x0A CLK10 0x0B CLK11 0x0C CLK12 0x0D CLK13 0x0E CLK14 0x0F CLK15 0x12 XO_DPLL PRIORITY_EN 0 R W 0 Enable reference priority 13 Enable reference priority 13 for the automatic reference selection 0 disabled 1 enabled Table 243 SYS_DPLL SYS_DPLL_R...

Page 199: ...TY_REF 5 1 R W 0 Input reference index for priority 14 0x00 CLK0 0x01 CLK1 0x02 CLK2 0x03 CLK3 0x04 CLK4 0x05 CLK5 0x06 CLK6 0x07 CLK7 0x08 CLK8 0x09 CLK9 0x0A CLK10 0x0B CLK11 0x0C CLK12 0x0D CLK13 0x0E CLK14 0x0F CLK15 0x12 XO_DPLL PRIORITY_EN 0 R W 0 Enable reference priority 14 Enable reference priority 14 for the automatic reference selection 0 disabled 1 enabled Table 244 SYS_DPLL SYS_DPLL_R...

Page 200: ...TY_REF 5 1 R W 0 Input reference index for priority 15 0x00 CLK0 0x01 CLK1 0x02 CLK2 0x03 CLK3 0x04 CLK4 0x05 CLK5 0x06 CLK6 0x07 CLK7 0x08 CLK8 0x09 CLK9 0x0A CLK10 0x0B CLK11 0x0C CLK12 0x0D CLK13 0x0E CLK14 0x0F CLK15 0x12 XO_DPLL PRIORITY_EN 0 R W 0 Enable reference priority 15 Enable reference priority 15 for the automatic reference selection 0 disabled 1 enabled Table 245 SYS_DPLL SYS_DPLL_R...

Page 201: ...TY_REF 5 1 R W 0 Input reference index for priority 16 0x00 CLK0 0x01 CLK1 0x02 CLK2 0x03 CLK3 0x04 CLK4 0x05 CLK5 0x06 CLK6 0x07 CLK7 0x08 CLK8 0x09 CLK9 0x0A CLK10 0x0B CLK11 0x0C CLK12 0x0D CLK13 0x0E CLK14 0x0F CLK15 0x12 XO_DPLL PRIORITY_EN 0 R W 0 Enable reference priority 16 Enable reference priority 16 for the automatic reference selection 0 disabled 1 enabled Table 246 SYS_DPLL SYS_DPLL_R...

Page 202: ...TY_REF 5 1 R W 0 Input reference index for priority 17 0x00 CLK0 0x01 CLK1 0x02 CLK2 0x03 CLK3 0x04 CLK4 0x05 CLK5 0x06 CLK6 0x07 CLK7 0x08 CLK8 0x09 CLK9 0x0A CLK10 0x0B CLK11 0x0C CLK12 0x0D CLK13 0x0E CLK14 0x0F CLK15 0x12 XO_DPLL PRIORITY_EN 0 R W 0 Enable reference priority 17 Enable reference priority 17 for the automatic reference selection 0 disabled 1 enabled Table 247 SYS_DPLL SYS_DPLL_R...

Page 203: ...CLK8 0x09 CLK9 0x0A CLK10 0x0B CLK11 0x0C CLK12 0x0D CLK13 0x0E CLK14 0x0F CLK15 0x12 XO_DPLL PRIORITY_EN 0 R W 0 Enable reference priority 18 Enable reference priority 18 for the automatic reference selection 0 disabled 1 enabled Table 248 SYS_DPLL SYS_DPLL_REF_MODE Bit Field Locations and Descriptions Offset Address Hex SYS_DPLL SYS_DPLL_REF_MODE Bit Field Locations D7 D6 D5 D4 D3 D2 D1 D0 01Bh ...

Page 204: ...0 automatic 1 force lock 2 force freerun 3 force holdover Table 250 DPLL_CTRL_0 Register Index Offset Hex Register Module Base Address C600ha Individual Register Name Register Description 000h DPLL_CTRL_0 DPLL_HS_TIE_RESET Reset hitless switching time interval error 001h DPLL_CTRL_0 DPLL_MANU_REF_CFG Manual reference mode configuration 002h DPLL_CTRL_0 DPLL_DAMPING DPLL loop filter damping factor ...

Page 205: ...PLL_CTRL_0 DPLL_MANUAL_HOLDOVER_ VALUE DCO value to be used in manual holdover mode 036h DPLL_CTRL_0 DPLL_DCD_FILTER_CNFG DPLL DCD filter configuration 038h DPLL_CTRL_0 DPLL_COMBO_MASTER_BW DPLL combo filter bandwidth 03Ah DPLL_CTRL_0 DPLL_COMBO_MASTER_CFG DPLL combo master configuration 03Bh DPLL_CTRL_0 DPLL_FRAME_PULSE_SYNC Frame pulse sync trigger a This register module is instantiated multiple...

Page 206: ..._REF_CFG Bit Field Descriptions Bit Field Name Field Type Default Value Description RESERVED N A This field must not be modified from the read value MANUAL_REFERENCE 4 0 R W 0 Index of manually selected reference input when manual reference mode is enabled 0x00 CLK0 0x01 CLK1 0x02 CLK2 0x03 CLK3 0x04 CLK4 0x05 CLK5 0x06 CLK6 0x07 CLK7 0x08 CLK8 0x09 CLK9 0x0A CLK10 0x0B CLK11 0x0C CLK12 0x0D CLK13...

Page 207: ...9 dB 0 2 dB 6 1 053 0 45 dB 0 5 dB 7 1 172 1 38 dB underdamp Table 254 DPLL_CTRL_0 DPLL_DECIMATOR_BW_MULT Bit Field Locations and Descriptions Offset Address Hex DPLL_CTRL_0 DPLL_DECIMATOR_BW_MULT Bit Field Locations D7 D6 D5 D4 D3 D2 D1 D0 003h MULT 7 0 DPLL_CTRL_0 DPLL_DECIMATOR_BW_MULT Bit Field Descriptions Bit Field Name Field Type Default Value Description MULT 7 0 R W 0 Unsigned 8 bit DPLL ...

Page 208: ... R W 0 Unsigned 14 bit DPLL loop filter bandwidth value Table 256 DPLL_CTRL_0 DPLL_PSL Bit Field Locations and Descriptions Offset Address Hex DPLL_CTRL_0 DPLL_PSL Bit Field Locations D7 D6 D5 D4 D3 D2 D1 D0 006h DPLL_PSL 7 0 007h DPLL_PSL 15 8 DPLL_CTRL_0 DPLL_PSL Bit Field Descriptions Bit Field Name Field Type Default Value Description DPLL_PSL 15 0 R W 0 Unsigned 16 bit loop filter phase slope...

Page 209: ... 015 0 13 dB 2 5 1 022 0 19 dB 0 2 dB 6 1 053 0 45 dB 0 5 dB 7 1 172 1 38 dB underdamp Table 258 DPLL_CTRL_0 DPLL_PRED0_DECIMATOR_BW_MULT Bit Field Locations and Descriptions Offset Address Hex DPLL_CTRL_0 DPLL_PRED0_DECIMATOR_BW_MULT Bit Field Locations D7 D6 D5 D4 D3 D2 D1 D0 009h MULT 7 0 DPLL_CTRL_0 DPLL_PRED0_DECIMATOR_BW_MULT Bit Field Descriptions Bit Field Name Field Type Default Value Des...

Page 210: ...14 bit DPLL loop filter bandwidth value Table 260 DPLL_CTRL_0 DPLL_PRED0_PSL Bit Field Locations and Descriptions Offset Address Hex DPLL_CTRL_0 DPLL_PRED0_PSL Bit Field Locations D7 D6 D5 D4 D3 D2 D1 D0 00Ch DPLL_PRED0_PSL 7 0 00Dh DPLL_PRED0_PSL 15 8 DPLL_CTRL_0 DPLL_PRED0_PSL Bit Field Descriptions Bit Field Name Field Type Default Value Description DPLL_PRED0_PSL 15 0 R W 0 Unsigned 16 bit loo...

Page 211: ... 015 0 13 dB 2 5 1 022 0 19 dB 0 2 dB 6 1 053 0 45 dB 0 5 dB 7 1 172 1 38 dB underdamp Table 262 DPLL_CTRL_0 DPLL_PRED1_DECIMATOR_BW_MULT Bit Field Locations and Descriptions Offset Address Hex DPLL_CTRL_0 DPLL_PRED1_DECIMATOR_BW_MULT Bit Field Locations D7 D6 D5 D4 D3 D2 D1 D0 00Fh MULT 7 0 DPLL_CTRL_0 DPLL_PRED1_DECIMATOR_BW_MULT Bit Field Descriptions Bit Field Name Field Type Default Value Des...

Page 212: ... Locations and Descriptions Offset Address Hex DPLL_CTRL_0 DPLL_PRED1_PSL Bit Field Locations D7 D6 D5 D4 D3 D2 D1 D0 012h DPLL_PRED1_PSL 7 0 013h DPLL_PRED1_PSL 15 8 DPLL_CTRL_0 DPLL_PRED1_PSL Bit Field Descriptions Bit Field Name Field Type Default Value Description DPLL_PRED1_PSL 15 0 R W 0 Unsigned 16 bit loop filter phase slope limit in ns s Value 0 implies no phase slope limit Table 265 DPLL...

Page 213: ... value will cause an output phase advance relative to the input clock phase Note that this phase offset configuration applies to both DPLL mode and write phase mode Table 266 DPLL_CTRL_0 DPLL_HO_HISTORY_RESET Bit Field Locations and Descriptions Offset Address Hex DPLL_CTRL_0 DPLL_HO_HISTORY_RESET Bit Field Locations D7 D6 D5 D4 D3 D2 D1 D0 019h RESERVED 7 1 HO_HISTOR Y_RESET 0 DPLL_CTRL_0 DPLL_HO...

Page 214: ...tes to 782 fs 0 782 ps phase advance applied to the DPLL Conversely 0x0000 means no phase advance is applied to the DPLL Note Phase advance is defined as the phase of the output that is measured relative to another reference and the output clocks rising edge comes after the rising edge of the reference signal by some amount X then a phase advance on the output clock will result in a measurement of...

Page 215: ...de Table 269 DPLL_CTRL_0 DPLL_MASTER_DIV Bit Field Locations and Descriptions Offset Address Hex DPLL_CTRL_0 DPLL_MASTER_DIV Bit Field Locations D7 D6 D5 D4 D3 D2 D1 D0 024h DPLL_MASTER_DIV 7 0 025h DPLL_MASTER_DIV 15 8 026h DPLL_MASTER_DIV 23 16 027h DPLL_MASTER_DIV 31 24 DPLL_CTRL_0 DPLL_MASTER_DIV Bit Field Descriptions Bit Field Name Field Type Default Value Description DPLL_MASTER_DIV 31 0 R ...

Page 216: ...Descriptions Bit Field Name Field Type Default Value Description DPLL_COMBO_SW_VALU E_CNFG 47 0 R W 0 DPLL Combo SW value in units of 2 53 Table 271 DPLL_CTRL_0 DPLL_MANUAL_HOLDOVER_VALUE Bit Field Locations and Descriptions Offset Address Hex DPLL_CTRL_0 DPLL_MANUAL_HOLDOVER_VALUE Bit Field Locations D7 D6 D5 D4 D3 D2 D1 D0 030h DPLL_MANUAL_HOLDOVER_VALUE 7 0 031h DPLL_MANUAL_HOLDOVER_VALUE 15 8 ...

Page 217: ..._CNFG Bit Field Descriptions Bit Field Name Field Type Default Value Description RESERVED N A This field must not be modified from the read value DCD_LPF_COE 14 10 R W 1010b DCD low pass filter coefficient DCD_MANU_UPDATE_RA TE_CNFG 9 6 R W 202h Configure DCD manual calibration mode updating rate Updating rate 10000 2 dcd_manu_update_rate_cnfg in hz DCD_MANU_GAIN_SHIFT 5 1 R W 10h DCD manual calib...

Page 218: ...Descriptions Offset Address Hex DPLL_CTRL_0 DPLL_COMBO_MASTER_CFG Bit Field Locations D7 D6 D5 D4 D3 D2 D1 D0 03Ah RESERVED 7 2 FILTER_IN_ SELECT 1 HOLD_EN 0 DPLL_CTRL_0 DPLL_COMBO_MASTER_CFG Bit Field Descriptions Bit Field Name Field Type Default Value Description RESERVED N A This field must not be modified from the read value FILTER_IN_SELECT 1 R W 0 Select filtered DCO value as combo source 0...

Page 219: ..._DECIMATOR_B W_MULT System DPLL loop filter decimator bandwidth multiplier 004h SYS_DPLL_CTRL SYS_DPLL_BW System DPLL loop filter bandwidth 006h SYS_DPLL_CTRL SYS_DPLL_PSL System DPLL loop filter phase slope limit 008h SYS_DPLL_CTRL SYS_DPLL_PRED0_DAMPI NG Predefined configuration 0 loop filter damping factor 009h SYS_DPLL_CTRL SYS_DPLL_PRED0_DECIM ATOR_BW_MULT Predefined configuration 0 loop filt...

Page 220: ...DPLL_CTRL SYS_DPLL_MANU_REF_CFG Bit Field Descriptions Bit Field Name Field Type Default Value Description RESERVED N A This field must not be modified from the read value MANUAL_REFERENCE 4 0 R W 0 Index of manually selected reference input when manual reference mode is enabled 0x00 CLK0 0x01 CLK1 0x02 CLK2 0x03 CLK3 0x04 CLK4 0x05 CLK5 0x06 CLK6 0x07 CLK7 0x08 CLK8 0x09 CLK9 0x0A CLK10 0x0B CLK1...

Page 221: ... 2 dB 6 1 053 0 45 dB 0 5 dB 7 1 172 1 38 dB underdamp Table 279 SYS_DPLL_CTRL SYS_DPLL_DECIMATOR_BW_MULT Bit Field Locations and Descriptions Offset Address Hex SYS_DPLL_CTRL SYS_DPLL_DECIMATOR_BW_MULT Bit Field Locations D7 D6 D5 D4 D3 D2 D1 D0 002h MULT 7 0 SYS_DPLL_CTRL SYS_DPLL_DECIMATOR_BW_MULT Bit Field Descriptions Bit Field Name Field Type Default Value Description MULT 7 0 R W 0 Unsigned...

Page 222: ... Unsigned 14 bit system DPLL loop filter bandwidth value Table 281 SYS_DPLL_CTRL SYS_DPLL_PSL Bit Field Locations and Descriptions Offset Address Hex SYS_DPLL_CTRL SYS_DPLL_PSL Bit Field Locations D7 D6 D5 D4 D3 D2 D1 D0 006h SYS_DPLL_PSL 7 0 007h SYS_DPLL_PSL 15 8 SYS_DPLL_CTRL SYS_DPLL_PSL Bit Field Descriptions Bit Field Name Field Type Default Value Description SYS_DPLL_PSL 15 0 R W 0 Unsigned...

Page 223: ...dB 2 5 1 022 0 19 dB 0 2 dB 6 1 053 0 45 dB 0 5 dB 7 1 172 1 38 dB underdamp Table 283 SYS_DPLL_CTRL SYS_DPLL_PRED0_DECIMATOR_BW_MULT Bit Field Locations and Descriptions Offset Address Hex SYS_DPLL_CTRL SYS_DPLL_PRED0_DECIMATOR_BW_MULT Bit Field Locations D7 D6 D5 D4 D3 D2 D1 D0 009h MULT 7 0 SYS_DPLL_CTRL SYS_DPLL_PRED0_DECIMATOR_BW_MULT Bit Field Descriptions Bit Field Name Field Type Default V...

Page 224: ...tem DPLL loop filter bandwidth value Table 285 SYS_DPLL_CTRL SYS_DPLL_PRED0_PSL Bit Field Locations and Descriptions Offset Address Hex SYS_DPLL_CTRL SYS_DPLL_PRED0_PSL Bit Field Locations D7 D6 D5 D4 D3 D2 D1 D0 00Ch SYS_DPLL_PRED0_PSL 7 0 00Dh SYS_DPLL_PRED0_PSL 15 8 SYS_DPLL_CTRL SYS_DPLL_PRED0_PSL Bit Field Descriptions Bit Field Name Field Type Default Value Description SYS_DPLL_PRED0_PSL 15 ...

Page 225: ...dB 2 5 1 022 0 19 dB 0 2 dB 6 1 053 0 45 dB 0 5 dB 7 1 172 1 38 dB underdamp Table 287 SYS_DPLL_CTRL SYS_DPLL_PRED1_DECIMATOR_BW_MULT Bit Field Locations and Descriptions Offset Address Hex SYS_DPLL_CTRL SYS_DPLL_PRED1_DECIMATOR_BW_MULT Bit Field Locations D7 D6 D5 D4 D3 D2 D1 D0 00Fh MULT 7 0 SYS_DPLL_CTRL SYS_DPLL_PRED1_DECIMATOR_BW_MULT Bit Field Descriptions Bit Field Name Field Type Default V...

Page 226: ... Table 289 SYS_DPLL_CTRL SYS_DPLL_PRED1_PSL Bit Field Locations and Descriptions Offset Address Hex SYS_DPLL_CTRL SYS_DPLL_PRED1_PSL Bit Field Locations D7 D6 D5 D4 D3 D2 D1 D0 012h SYS_DPLL_PRED1_PSL 7 0 013h SYS_DPLL_PRED1_PSL 15 8 SYS_DPLL_CTRL SYS_DPLL_PRED1_PSL Bit Field Descriptions Bit Field Name Field Type Default Value Description SYS_DPLL_PRED1_PSL 15 0 R W 0 Unsigned 16 bit loop filter ...

Page 227: ...tions D7 D6 D5 D4 D3 D2 D1 D0 016h RESERVED 7 2 FILTER_IN_ SELECT 1 HOLD_EN 0 SYS_DPLL_CTRL SYS_DPLL_COMBO_MASTER_CFG Bit Field Descriptions Bit Field Name Field Type Default Value Description RESERVED N A This field must not be modified from the read value FILTER_IN_SELECT 1 R W 0 Select filtered DCO value as combo source 0 integrator value only 1 sum of proportional and integrator HOLD_EN 0 R W ...

Page 228: ...e Default Value Description DPLL_WRITE_PH 31 0 R W 0 Signed 32 bit phase offset in ITDC_UIs When DPLL_n DPLL_MODE PLL_MODE write phase mode this value inputs to the loop filter and controls the DPLL phase Table 294 DPLL_FREQ_0 Register Index Offset Hex Register Module Base Address C838ha a This register module is instantiated multiple times This is the base address of the first instantiation of th...

Page 229: ... Bit Field Name Field Type Default Value Description RESERVED N A This field must not be modified from the read value DPLL_WR_FREQ 41 0 R W 0 Signed 42 bit FFO in units of 2 53 Used when DPLL_n DPLL_MODE PLL_MODE write frequency mode Table 296 DPLL_PHASE_PULL_IN_0 Register Index Offset Hex Register Module Base Address C880ha a This register module is instantiated multiple times This is the base ad...

Page 230: ... Field Type Default Value Description DPLL_PHASE_PULL_IN_ OFFSET 31 0 R W 0 Signed 32 bit phase pull in offset in nanoseconds The phase offset for the phase pull in operation Table 298 DPLL_PHASE_PULL_IN_0 DPLL_PHASE_PULL_IN_SLOPE_LIMIT Bit Field Locations and Descriptions Offset Address Hex DPLL_PHASE_PULL_IN_0 DPLL_PHASE_PULL_IN_SLOPE_LIMIT Bit Field Locations D7 D6 D5 D4 D3 D2 D1 D0 004h DPLL_P...

Page 231: ...ERVED N A This field must not be modified from the read value PHASE_PULL_IN_REQUE ST 0 R W 0 Phase pull in request Setting this bit to 1 starts a phase pull in if there is no one in progress Otherwise it will be ignored Setting this bit to 0 terminates the on going phase pull in This request is only applicable to pll_mode write phase mode write frequency mode GPIO inc dec mode and synthesizer mode...

Page 232: ...O controlled output squelch for outputs 8 11 003h GPIO_0 GPIO_TOD_TRIG GPIO controlled TOD trigger input 004h GPIO_0 GPIO_DPLL_INDICATOR GPIO indicator for DPLL lock and holdover states 005h GPIO_0 GPIO_LOS_INDICATOR GPIO loss of signal LOS indicator 006h GPIO_0 GPIO_REF_INPUT_DSQ_0 GPIO controlled input disqualification for inputs 0 7 007h GPIO_0 GPIO_REF_INPUT_DSQ_1 GPIO controlled input disqual...

Page 233: ...EC Bit Field Locations and Descriptions Offset Address Hex GPIO_0 GPIO_DCO_INC_DEC Bit Field Locations D7 D6 D5 D4 D3 D2 D1 D0 000h RESERVED 7 3 DPLL_INDEX 2 0 GPIO_0 GPIO_DCO_INC_DEC Bit Field Descriptions Bit Field Name Field Type Default Value Description RESERVED N A This field must not be modified from the read value DPLL_INDEX 2 0 R W 0 DPLL index Select the DPLL to be controlled by this GPI...

Page 234: ...ut 5 0 disabled 1 enabled CTRL_OUT_4 4 R W 0 Select output 4 to be controlled by this GPIO GPIO is used to disable squelch output 4 0 disabled 1 enabled CTRL_OUT_3 3 R W 0 Select output 3 to be controlled by this GPIO GPIO is used to disable squelch output 3 0 disabled 1 enabled CTRL_OUT_2 2 R W 0 Select output 2 to be controlled by this GPIO GPIO is used to disable squelch output 2 0 disabled 1 e...

Page 235: ...O is used to disable squelch output 9 0 disabled 1 enabled CTRL_OUT_8 0 R W 0 Select output 8 to be controlled by this GPIO GPIO is used to disable squelch output 8 0 disabled 1 enabled Table 306 GPIO_0 GPIO_TOD_TRIG Bit Field Locations and Descriptions Offset Address Hex GPIO_0 GPIO_TOD_TRIG Bit Field Locations D7 D6 D5 D4 D3 D2 D1 D0 003h RESERVED 7 4 TOD_TRIG_ 3 3 TOD_TRIG_ 2 2 TOD_TRIG_ 1 1 TO...

Page 236: ...ion is triggered on the rising edge of this GPIO The tod_write_selection or tod_read_trigger for TOD 1 has to be equal to Selected GPIO CAUTION if more than one GPIO is used to trigger the same TOD the behaviour is undefined 0 disabled 1 enabled TOD_TRIG_0 0 R W 0 Select TOD of DPLL 0 to be triggered by this GPIO The TOD read write operation is triggered on the rising edge of this GPIO The tod_wri...

Page 237: ...icator The GPIO level is active when the DPLL is in holdover state when GPIO_n GPIO_FUNCTION holdover indicator 0 DPLL0 1 DPLL1 2 DPLL2 3 DPLL3 4 DPLL4 5 DPLL5 6 DPLL6 7 DPLL7 8 SYS_DPLL Table 308 GPIO_0 GPIO_LOS_INDICATOR Bit Field Locations and Descriptions Offset Address Hex GPIO_0 GPIO_LOS_INDICATOR Bit Field Locations D7 D6 D5 D4 D3 D2 D1 D0 005h RESERVED 7 5 ACTIVE_LEV EL 4 REFMON_INDEX 3 0 ...

Page 238: ... GPIO is used to disqualify input 7 0 disabled 1 enabled DSQ_INP_6 6 R W 0 Select input 6 to be disqualified by this GPIO GPIO is used to disqualify input 6 0 disabled 1 enabled DSQ_INP_5 5 R W 0 Select input 5 to be disqualified by this GPIO GPIO is used to disqualify input 5 0 disabled 1 enabled DSQ_INP_4 4 R W 0 Select input 4 to be disqualified by this GPIO GPIO is used to disqualify input 4 0...

Page 239: ...O is used to disqualify input 15 0 disabled 1 enabled DSQ_INP_14 6 R W 0 Select input 14 to be disqualified by this GPIO GPIO is used to disqualify input 14 0 disabled 1 enabled DSQ_INP_13 5 R W 0 Select input 13 to be disqualified by this GPIO GPIO is used to disqualify input 13 0 disabled 1 enabled DSQ_INP_12 4 R W 0 Select input 12 to be disqualified by this GPIO GPIO is used to disqualify inpu...

Page 240: ...DSQ_DPLL_7 7 R W 0 Select DPLL 7 GPIO is used to disqualify selected inputs for DPLL 7 0 disabled 1 enabled DSQ_DPLL_6 6 R W 0 Select DPLL 6 GPIO is used to disqualify selected inputs for DPLL 6 0 disabled 1 enabled DSQ_DPLL_5 5 R W 0 Select DPLL 5 GPIO is used to disqualify selected inputs for DPLL 5 0 disabled 1 enabled DSQ_DPLL_4 4 R W 0 Select DPLL 4 GPIO is used to disqualify selected inputs ...

Page 241: ...SQ_3 Bit Field Descriptions Bit Field Name Field Type Default Value Description RESERVED N A This field must not be modified from the read value GPIO_DSQ_LEVEL 1 R W 0 Indicates the GPIO level used to disqualify the selected inputs 0 low 1 high DSQ_DPLL_SYS 0 R W 0 Select system DPLL GPIO is used to disqualify selected inputs for system DPLL 0 disabled 1 enabled Table 313 GPIO_0 GPIO_MAN_CLK_SEL_0...

Page 242: ...lect DPLL 7 GPIO is used to select the input for DPLL 7 0 disabled 1 enabled DPLL6 6 R W 0 Select DPLL 6 GPIO is used to select the input for DPLL 6 0 disabled 1 enabled DPLL5 5 R W 0 Select DPLL 5 GPIO is used to select the input for DPLL 5 0 disabled 1 enabled DPLL4 4 R W 0 Select DPLL 4 GPIO is used to select the input for DPLL 4 0 disabled 1 enabled DPLL3 3 R W 0 Select DPLL 3 GPIO is used to ...

Page 243: ...eld Type Default Value Description RESERVED N A This field must not be modified from the read value DPLL_SYS 0 R W 0 Select system DPLL GPIO is used to select the input for system DPLL 0 disabled 1 enabled Table 316 GPIO_0 GPIO_SLAVE Bit Field Locations and Descriptions Offset Address Hex GPIO_0 GPIO_SLAVE Bit Field Locations D7 D6 D5 D4 D3 D2 D1 D0 00Dh RESERVED 7 1 GPIO_SLAV E_LEVEL 0 GPIO_0 GPI...

Page 244: ...ue Description RESERVED N A This field must not be modified from the read value GPIO_ALERT_OUT_LEVE L 0 R W 0 GPIO alert out active level 0 active low 1 active high Table 318 GPIO_0 GPIO_TOD_NOTIFICATION_CFG Bit Field Locations and Descriptions Offset Address Hex GPIO_0 GPIO_TOD_NOTIFICATION_CFG Bit Field Locations D7 D6 D5 D4 D3 D2 D1 D0 00Fh RESERVED 7 4 GPIO_ASSE RT_LEVEL 3 TOD_READ_ SECONDAR Y...

Page 245: ...el becomes active after the TOD register is updated 0 ToD read primary 1 ToD read secondary DPLL_TOD 1 0 R W 0 DPLL TOD index Select the DPLL whose TOD register has been read 0 DPLL0 1 DPLL1 2 DPLL2 3 DPLL3 Table 319 GPIO_0 GPIO_CTRL Bit Field Locations and Descriptions Offset Address Hex GPIO_0 GPIO_CTRL Bit Field Locations D7 D6 D5 D4 D3 D2 D1 D0 010h GPIO_FUNCTION 7 4 GPIO_PU_P D_MODE 3 GPIO_CO...

Page 246: ...ock disqualify in 0x7 manual clock select in 0x8 OTP configuration select in 0x9 clock output control in 0xA ToD trigger in 0xB ToD read notification out 0xC master slave signal in GPIO_PU_PD_MODE 3 R W 0 Select pull up or pull down Applies when GPIO direction is Input 0 pu 1 pd GPIO_CONTROL_DIR 2 R W 0 Select GPIO direction Applies when GPIO function mode is disabled 0 input 1 output GPIO_CMOS_OD...

Page 247: ... the driver for the clock and sync for output divider 8 In normal mode FOD 4 drives output divider 8 and FOD 5 drives output divider 9 In coupled mode FOD 5 drives both output divider 8 and 9 0 normal 1 coupled Table 322 OUT_DIV_MUX OUT_DIV11_MUX Bit Field Locations and Descriptions Offset Address Hex OUT_DIV_MUX OUT_DIV11_MUX Bit Field Locations D7 D6 D5 D4 D3 D2 D1 D0 001h RESERVED 7 1 FOD6_TO_O...

Page 248: ...this module For later instantiations use the appropriate module base address Individual Register Name Register Description 000h OUTPUT_0 OUT_DIV Output divider value 004h OUTPUT_0 OUT_DUTY_CYCLE_HIGH Output duty cycle 008h OUTPUT_0 OUT_CTRL_0 Output electrical characteristics 009h OUTPUT_0 OUT_CTRL_1 Output electrical characteristics 00Ch OUTPUT_0 OUT_PHASE_ADJ Output phase adjustment Table 324 OU...

Page 249: ...UT_DUTY_CYCLE_HIGH Bit Field Locations and Descriptions Offset Address Hex OUTPUT_0 OUT_DUTY_CYCLE_HIGH Bit Field Locations D7 D6 D5 D4 D3 D2 D1 D0 004h OUT_DUTY_CYCLE_HIGH 7 0 005h OUT_DUTY_CYCLE_HIGH 15 8 006h OUT_DUTY_CYCLE_HIGH 23 16 007h OUT_DUTY_CYCLE_HIGH 31 24 OUTPUT_0 OUT_DUTY_CYCLE_HIGH Bit Field Descriptions Bit Field Name Field Type Default Value Description OUT_DUTY_CYCLE_HIG H 31 0 R...

Page 250: ...750mV 3 900mV PAD_MODE 2 0 R W 0 Output mode 0 high Z 1 differential 2 LVCMOS inverted 3 LVCMOS in phase 4 reserved 5 reserved 6 LVCMOS Q enabled nQ High Z 7 reserved Table 327 OUTPUT_0 OUT_CTRL_1 Bit Field Locations and Descriptions Offset Address Hex OUTPUT_0 OUT_CTRL_1 Bit Field Locations D7 D6 D5 D4 D3 D2 D1 D0 009h OUT_SYNC_ DISABLE 7 SQUELCH_V ALUE 6 SQUELCH_ DISABLE 5 PAD_VDDO 4 2 PAD_CMOSD...

Page 251: ...8 1 5V 100 1 2V 2 18 3 3V 20 2 5V 29 1 8V 40 1 5V 65 1 2V 3 15 3 3V 16 2 5V 23 1 8V 29 1 5V 50 1 2V Table 328 OUTPUT_0 OUT_PHASE_ADJ Bit Field Locations and Descriptions Offset Address Hex OUTPUT_0 OUT_PHASE_ADJ Bit Field Locations D7 D6 D5 D4 D3 D2 D1 D0 00Ch OUT_PHASE_ADJ 7 0 00Dh OUT_PHASE_ADJ 15 8 00Eh OUT_PHASE_ADJ 23 16 00Fh OUT_PHASE_ADJ 31 24 OUTPUT_0 OUT_PHASE_ADJ Bit Field Descriptions B...

Page 252: ...erface 0 main serial port 005h SERIAL SER1 Slave serial interface 1 auxiliary serial port configuration 006h SERIAL SER1_SPI SPI configuration for serial interface 1 auxiliary serial port 007h SERIAL SER1_I2C I2C configuration for serial interface 1 auxiliary serial port 008h SERIAL SER_APPLY_CONFIG Trigger serial configuration changes Table 330 SERIAL I2CM Bit Field Locations and Descriptions Off...

Page 253: ...R W 0 Serial interface 0 address size 0 1 byte 1 2 byte MODE 1 0 R W 0 Serial interface 0 mode Set MODE 0 to maintain current configuration e g mode indicated by SER0_STATUS_MODE field will remain the same 0 no change 1 I2C 2 SPI 3 disabled Table 332 SERIAL SER0_SPI Bit Field Locations and Descriptions Offset Address Hex SERIAL SER0_SPI Bit Field Locations D7 D6 D5 D4 D3 D2 D1 D0 003h RESERVED 7 5...

Page 254: ...ns D7 D6 D5 D4 D3 D2 D1 D0 004h APPLY 7 DEVICE_ADDRESS 6 0 SERIAL SER0_I2C Bit Field Descriptions Bit Field Name Field Type Default Value Description APPLY 7 R W 0 Apply the new I2C address when the confirmation code triggers configuration to serial interface 0 0 do not change 1 apply new address DEVICE_ADDRESS 6 0 R W 0 7 bit I2C address Table 334 SERIAL SER1 Bit Field Locations and Descriptions ...

Page 255: ...t Field Locations D7 D6 D5 D4 D3 D2 D1 D0 006h RESERVED 7 5 SPI_SDO_D ELAY 4 SPI_CLOCK _SELECTIO N 3 SPI_DUPLE X_MODE 2 RESERVED 1 0 SERIAL SER1_SPI Bit Field Descriptions Bit Field Name Field Type Default Value Description SPI_SDO_DELAY 4 R W 0 SPI delay SDO driving edge 0 driving edge used for SDO 1 SDO driving edge delayed half cycle of SCLK SPI_CLOCK_SELECTION 3 R W 0 SPI Clock Selection for S...

Page 256: ... change 1 apply new address DEVICE_ADDRESS 6 0 R W 0 7 bit I2C address Table 337 SERIAL SER_APPLY_CONFIG Bit Field Locations and Descriptions Offset Address Hex SERIAL SER_APPLY_CONFIG Bit Field Locations D7 D6 D5 D4 D3 D2 D1 D0 008h SER0_CONFIRM_CODE 7 4 SER1_CONFIRM_CODE 3 0 SERIAL SER_APPLY_CONFIG Bit Field Descriptions Bit Field Name Field Type Default Value Description SER0_CONFIRM_CODE 7 4 R...

Page 257: ...01h PWM_ENCODER_0 PWM_ENCODER_CNFG PWM encoder configuration 002h PWM_ENCODER_0 PWM_ENCODER_SIGNA TURE_0 PWM encoder signature configuration 003h PWM_ENCODER_0 PWM_ENCODER_SIGNA TURE_1 PWM encoder signature configuration 004h PWM_ENCODER_0 PWM_ENCODER_CMD PWM encoder command Table 339 PWM_ENCODER_0 PWM_ENCODER_ID Bit Field Locations and Descriptions Offset Address Hex PWM_ENCODER_0 PWM_ENCODER_ID ...

Page 258: ...t the Q5 output divider is used as the PPS trigger source Please note that in this case you also need to set secondary_output 1 0 ToD PPS 1 alternate PPS SECONDARY_OUTPUT 2 R W 0 Select output to be used for PWM carrier For dual channel PWM encoders 0 3 a value of 1 indicates that the secondary output is used for PWM carrier For single channel PWM encoders 4 7 a value of 1 indicates that the Q5 ou...

Page 259: ...zero 25 on 75 off duty cycle clock period one 75 on 25 off duty cycle clock period space 50 on 50 off duty cycle clock period 0 zero 1 one 2 space SEVENTH_SYMBOL 3 2 R W 0 The seventh symbol of the signature zero 25 on 75 off duty cycle clock period one 75 on 25 off duty cycle clock period space 50 on 50 off duty cycle clock period 0 zero 1 one 2 space EIGHTH_SYMBOL 1 0 R W 0 The eighth symbol of ...

Page 260: ...5 4 R W 0 The second symbol of the signature zero 25 on 75 off duty cycle clock period one 75 on 25 off duty cycle clock period space 50 on 50 off duty cycle clock period 0 zero 1 one 2 space THIRD_SYMBOL 3 2 R W 0 The third symbol of the signature zero 25 on 75 off duty cycle clock period one 75 on 25 off duty cycle clock period space 50 on 50 off duty cycle clock period 0 zero 1 one 2 space FOUR...

Page 261: ...e 344 PWM_DECODER_0 Register Index Offset Hex Register Module Base Address CB40ha a This register module is instantiated multiple times This is the base address of the first instantiation of this module For later instantiations use the appropriate module base address Individual Register Name Register Description 000h PWM_DECODER_0 PWM_DECODER_CNFG PWM_PPS configuration 002h PWM_DECODER_0 PWM_DECOD...

Page 262: ...ATE 14 0 R W 0 PWM PPS rate in units of 0 5 Hz Table 346 PWM_DECODER_0 PWM_DECODER_ID Bit Field Locations and Descriptions Offset Address Hex PWM_DECODER_0 PWM_DECODER_ID Bit Field Locations D7 D6 D5 D4 D3 D2 D1 D0 002h DECODER_ID 7 0 PWM_DECODER_0 PWM_DECODER_ID Bit Field Descriptions Bit Field Name Field Type Default Value Description DECODER_ID 7 0 R W 0 Unique PWM decoder ID in the PWM network...

Page 263: ...ro 25 on 75 off duty cycle clock period one 75 on 25 off duty cycle clock period space 50 on 50 off duty cycle clock period 0 zero 1 one 2 space SEVENTH_SYMBOL 3 2 R W 0 The seventh symbol of the signature zero 25 on 75 off duty cycle clock period one 75 on 25 off duty cycle clock period space 50 on 50 off duty cycle clock period 0 zero 1 one 2 space EIGHTH_SYMBOL 1 0 R W 0 The eighth symbol of th...

Page 264: ...cond symbol of the signature zero 25 on 75 off duty cycle clock period one 75 on 25 off duty cycle clock period space 50 on 50 off duty cycle clock period 0 zero 1 one 2 space THIRD_SYMBOL 3 2 R W 0 The third symbol of the signature zero 25 on 75 off duty cycle clock period one 75 on 25 off duty cycle clock period space 50 on 50 off duty cycle clock period 0 zero 1 one 2 space FOURTH_SYMBOL 1 0 R ...

Page 265: ...lded in FIFO for 1 second SIGNATURE_MODE 1 R W 0 Enable signature mode 0 disabled 1 enabled ENABLE 0 R W 0 Enable PWM decoder 0 disabled 1 enabled Table 350 PWM_USER_DATA Register Index Offset Hex Register Module Base Address CBC8h Individual Register Name Register Description 000h PWM_USER_DATA PWM_SRC_ENCODER_ID Source PWM encoder 001h PWM_USER_DATA PWM_DST_DECODER_ID Destination PWM decoder 002...

Page 266: ...t Field Descriptions Bit Field Name Field Type Default Value Description DECODER_ID 7 0 R W 0 PWM decoder identification Use 0xFF for broadcast transmission Table 353 PWM_USER_DATA PWM_USER_DATA_SIZE Bit Field Locations and Descriptions Offset Address Hex PWM_USER_DATA PWM_USER_DATA_SIZE Bit Field Locations D7 D6 D5 D4 D3 D2 D1 D0 002h BYTES 7 0 PWM_USER_DATA PWM_USER_DATA_SIZE Bit Field Descripti...

Page 267: ...te a Start transmission command 0 1 and 2 are set by the user All the other status codes are set by the device 0x00 idle 0x01 tx request 0x02 start transmission 0x03 tx ack 0x04 tx in progress 0x05 tx success 0x06 tx invalid encoder ID 0x07 tx wrong data size 0x08 tx encoder error 0x09 tx cancelled 0x0A rx in progress 0x0B rx success 0x0C rx wrong data size 0x0D rx lost frames 0x0E rx timeout 0x0F...

Page 268: ...ed every 2 seconds 0 disabled 1 enabled TOD_OUT_SYNC_ENABL E 1 R W 0 Enable the TOD output channel synchronization 0 disabled 1 enabled TOD_ENABLE 0 R W 0 Enable TOD 0 disabled 1 enabled Table 357 TOD_WRITE_0 Register Index Offset Hex Register Module Base Address CC00ha a This register module is instantiated multiple times This is the base address of the first instantiation of this module For late...

Page 269: ... 31 24 004h NS 39 32 005h SECONDS 47 40 006h SECONDS 55 48 007h SECONDS 63 56 008h SECONDS 71 64 009h SECONDS 79 72 00Ah SECONDS 87 80 TOD_WRITE_0 TOD_WRITE Bit Field Descriptions Bit Field Name Field Type Default Value Description SECONDS 87 40 R W 0 Seconds part of TOD Unsigned 48 bit value in seconds NS 39 8 R W 0 Nanoseconds part of TOD Unsigned 32 bit value in nanoseconds The maximum value is...

Page 270: ...is written to Table 360 TOD_WRITE_0 TOD_WRITE_SELECT_CFG_0 Bit Field Locations and Descriptions Offset Address Hex TOD_WRITE_0 TOD_WRITE_SELECT_CFG_0 Bit Field Locations D7 D6 D5 D4 D3 D2 D1 D0 00Dh PWM_DECODER_INDEX 7 4 REF_INDEX 3 0 TOD_WRITE_0 TOD_WRITE_SELECT_CFG_0 Bit Field Descriptions Bit Field Name Field Type Default Value Description PWM_DECODER_INDEX 7 4 R W 0 PWM decoder index used as t...

Page 271: ...Y_0 Register Index Offset Hex Register Module Base Address CC40ha a This register module is instantiated multiple times This is the base address of the first instantiation of this module For later instantiations use the appropriate module base address Individual Register Name Register Description 000h TOD_READ_PRIMARY_0 TOD_READ_PRIMA RY TOD read primary registers 00Bh TOD_READ_PRIMARY_0 TOD_READ_...

Page 272: ...noseconds The maximum value is 0x3b9ac9ff 999 999 999 ns SUBNS 7 0 R O 0 Sub nanoseconds part of TOD Unsigned 8 bit value in units of 1 256 nanoseconds Table 364 TOD_READ_PRIMARY_0 TOD_READ_PRIMARY_COUNTER Bit Field Locations and Descriptions Offset Address Hex TOD_READ_PRIMARY_0 TOD_READ_PRIMARY_COUNTER Bit Field Locations D7 D6 D5 D4 D3 D2 D1 D0 00Bh READ_COUNTER 7 0 TOD_READ_PRIMARY_0 TOD_READ_...

Page 273: ...Bit Field Locations D7 D6 D5 D4 D3 D2 D1 D0 00Ch PWM_DECODER_INDEX 7 4 REF_INDEX 3 0 TOD_READ_PRIMARY_0 TOD_READ_PRIMARY_SEL_CFG_0 Bit Field Descriptions Bit Field Name Field Type Default Value Description PWM_DECODER_INDEX 7 4 R W 0 PWM decoder index used as trigger REF_INDEX 3 0 R W 0 Input reference index used as trigger Table 366 TOD_READ_PRIMARY_0 TOD_READ_PRIMARY_CMD Bit Field Locations and ...

Page 274: ...te to DPLL_WR_FREQ 7 selected GPIO Table 367 TOD_READ_SECONDARY_0 Register Index Offset Hex Register Module Base Address CC90ha a This register module is instantiated multiple times This is the base address of the first instantiation of this module For later instantiations use the appropriate module base address Individual Register Name Register Description 000h TOD_READ_SECONDARY_0 TOD_READ_SE CO...

Page 275: ...16 003h NS 31 24 004h NS 39 32 005h SECONDS 47 40 006h SECONDS 55 48 007h SECONDS 63 56 008h SECONDS 71 64 009h SECONDS 79 72 00Ah SECONDS 87 80 TOD_READ_SECONDARY_0 TOD_READ_SECONDARY Bit Field Descriptions Bit Field Name Field Type Default Value Description SECONDS 87 40 R O 0 Seconds part of TOD Unsigned 48 bit value in seconds NS 39 8 R O 0 Nanoseconds part of TOD Unsigned 32 bit value in nano...

Page 276: ..._0 Bit Field Locations and Descriptions Offset Address Hex TOD_READ_SECONDARY_0 TOD_READ_SECONDARY_SEL_CFG_0 Bit Field Locations D7 D6 D5 D4 D3 D2 D1 D0 00Ch PWM_DECODER_INDEX 7 4 REF_INDEX 3 0 TOD_READ_SECONDARY_0 TOD_READ_SECONDARY_SEL_CFG_0 Bit Field Descriptions Bit Field Name Field Type Default Value Description PWM_DECODER_INDEX 7 4 R W 0 PWM decoder index used as trigger REF_INDEX 3 0 R W 0...

Page 277: ...ernal ToD PPS signal 3 selected reference clock input 4 selected PWM decoder s 1 PPS output 5 reserved 6 a write to DPLL_WR_FREQ 7 selected GPIO Table 372 OUTPUT_TDC_CFG Register Index Offset Hex Register Module Base Address CCD0h Individual Register Name Register Description 000h OUTPUT_TDC_CFG OUTPUT_TDC_CFG_GB L_0 Fastlock enable delay 002h OUTPUT_TDC_CFG OUTPUT_TDC_CFG_GB L_1 Fastlock disable ...

Page 278: ... shorten the settling time to within microseconds compared to milliseconds Table 374 OUTPUT_TDC_CFG OUTPUT_TDC_CFG_GBL_1 Bit Field Locations and Descriptions Offset Address Hex OUTPUT_TDC_CFG OUTPUT_TDC_CFG_GBL_1 Bit Field Locations D7 D6 D5 D4 D3 D2 D1 D0 002h FAST_LOCK_DISABLE_DELAY 7 0 003h FAST_LOCK_DISABLE_DELAY 15 8 OUTPUT_TDC_CFG OUTPUT_TDC_CFG_GBL_1 Bit Field Descriptions Bit Field Name Fi...

Page 279: ... OUTPUT_TDC_CFG_STATUS state 0 disabled 1 enabled Table 376 OUTPUT_TDC_0 Register Index Offset Hex Register Module Base Address CD00ha a This register module is instantiated multiple times This is the base address of the first instantiation of this module For later instantiations use the appropriate module base address Individual Register Name Register Description 000h OUTPUT_TDC_0 OUTPUT_TDC_CTRL...

Page 280: ...PUT_TDC_0 OUTPUT_TDC_CTRL_1 Bit Field Locations and Descriptions Offset Address Hex OUTPUT_TDC_0 OUTPUT_TDC_CTRL_1 Bit Field Locations D7 D6 D5 D4 D3 D2 D1 D0 002h TARGET_PHASE_OFFSET 7 0 003h TARGET_PHASE_OFFSET 15 8 OUTPUT_TDC_0 OUTPUT_TDC_CTRL_1 Bit Field Descriptions Bit Field Name Field Type Default Value Description TARGET_PHASE_OFFSE T 15 0 R W 0 Target phase offset for alignment operation ...

Page 281: ...mode to indicate the target DPLL s to align with source_index DPLL alignment target mask index Alignment mode Each set bit represents the DPLLs to be aligned with the source_index DPLL Bit 0 corresponds to DPLL0 bit 1 DPLL1 etc 0b00000001 DPLL0 0b10000000 DPLL7 0b00000011 DPLL0 and DPLL1 Table 380 OUTPUT_TDC_0 OUTPUT_TDC_CTRL_3 Bit Field Locations and Descriptions Offset Address Hex OUTPUT_TDC_0 O...

Page 282: ...ainst source_index 0x0 DPLL0 0x1 DPLL1 0x2 DPLL2 0x3 DPLL3 0x4 DPLL4 0x5 DPLL5 0x6 DPLL6 0x7 DPLL7 0x8 GPIO6 0x9 GPIO1 0xA GPIO2 0xB GPIO7 SOURCE_INDEX 3 0 R W 0 Used in measurement and alignment mode to indicate the source clock Indicates the source to be used as the measurement reference 0x0 DPLL0 0x1 DPLL1 0x2 DPLL2 0x3 DPLL3 0x4 DPLL4 0x5 DPLL5 0x6 DPLL6 0x7 DPLL7 0x8 GPIO6 0x9 GPIO1 0xA GPIO2...

Page 283: ...dings that match target_phase_offset before declaring alignment is done Value of 0 means count of 1 ALIGN_RESET 3 R W 0 Reset output TDC accumulated adjustments to zero prior to starting output TDC operation i e clear accumulated coarse phase delay and fine phase advance adjustments Measurement mode Set to 1 to reset the output TDC alignment of the target specified by the target_index field Alignm...

Page 284: ...hot when the operation is complete go will be cleared to 0 and OUTPUT_TDC0_STATUS status will be set to Idle on success and an error status on failure For type continuous on success go will stay set and the operation continues until user clears go to cancel the alignment operations On failure the operation stops and go will be cleared 0 stop output TDC operation 1 start output TDC operation Table ...

Page 285: ...ble When set to 1 the value assigned to input_tdc_fbd_integer field is used to program the input TDC feedback divider Otherwise when set to 0 the input TDC feedback divider will be programmed internally and the input TDC frequency will be configured as 625 MHz 0 disabled 1 enabled FBD_INTEGER 6 0 R W 0 Input TDC feedback divider integer value ITDC_UI 1 32 input TDC frequency Table 384 INPUT_TDC IN...

Page 286: ...TCH SCRATCH0 Multipurpose register 004h SCRATCH SCRATCH1 Multipurpose register 008h SCRATCH SCRATCH2 Multipurpose register 00Ch SCRATCH SCRATCH3 Multipurpose register Table 386 SCRATCH SCRATCH0 Bit Field Locations and Descriptions Offset Address Hex SCRATCH SCRATCH0 Bit Field Locations D7 D6 D5 D4 D3 D2 D1 D0 000h SCRATCH0 7 0 001h SCRATCH0 15 8 002h SCRATCH0 23 16 003h SCRATCH0 31 24 SCRATCH SCRA...

Page 287: ...ons and Descriptions Offset Address Hex SCRATCH SCRATCH2 Bit Field Locations D7 D6 D5 D4 D3 D2 D1 D0 008h SCRATCH2 7 0 009h SCRATCH2 15 8 00Ah SCRATCH2 23 16 00Bh SCRATCH2 31 24 SCRATCH SCRATCH2 Bit Field Descriptions Bit Field Name Field Type Default Value Description SCRATCH2 31 0 R W 0 User data Table 389 SCRATCH SCRATCH3 Bit Field Locations and Descriptions Offset Address Hex SCRATCH SCRATCH3 ...

Page 288: ...M_I2C_ADDR Bit Field Locations and Descriptions Offset Address Hex EEPROM EEPROM_I2C_ADDR Bit Field Locations D7 D6 D5 D4 D3 D2 D1 D0 000h RESERVED 7 I2C_ADDR 6 0 EEPROM EEPROM_I2C_ADDR Bit Field Descriptions Bit Field Name Field Type Default Value Description RESERVED N A This field must not be modified from the read value I2C_ADDR 6 0 R W 0 I2C address of the EEPROM Table 392 EEPROM EEPROM_SIZE ...

Page 289: ...criptions Bit Field Name Field Type Default Value Description EEPROM_OFFSET 15 0 R W 0 Unsigned 16 bit value in bytes indicating the offset inside the EEPROM Table 394 EEPROM EEPROM_CMD Bit Field Locations and Descriptions Offset Address Hex EEPROM EEPROM_CMD Bit Field Locations D7 D6 D5 D4 D3 D2 D1 D0 004h EEPROM_CMD 7 0 005h EEPROM_CMD 15 8 EEPROM EEPROM_CMD Bit Field Descriptions Bit Field Name...

Page 290: ... Bit Field Name Field Type Default Value Description OTP_CMD 31 0 R W 0 Table 397 OTP OTP_CM_CTR Bit Field Locations and Descriptions Offset Address Hex OTP OTP_CM_CTR Bit Field Locations D7 D6 D5 D4 D3 D2 D1 D0 004h OTP_CM_CTR 7 0 005h OTP_CM_CTR 15 8 OTP OTP_CM_CTR Bit Field Descriptions Bit Field Name Field Type Default Value Description OTP_CM_CTR 15 0 R O 0 Total number of 32 bit words transf...

Page 291: ...t counter is updated by the external host processor and represents the total number of 32 bit words transferred through the OTP buffer during the current command Table 399 BYTE Register Index Offset Hex Register Module Base Address CF80h Individual Register Name Register Description 000h BYTE OTP_EEPROM_PWM_BUFF_0 OTP EEPROM PWM buffer 001h BYTE OTP_EEPROM_PWM_BUFF_1 002h BYTE OTP_EEPROM_PWM_BUFF_...

Page 292: ...P_EEPROM_PWM_BUFF_28 01Dh BYTE OTP_EEPROM_PWM_BUFF_29 01Eh BYTE OTP_EEPROM_PWM_BUFF_30 01Fh BYTE OTP_EEPROM_PWM_BUFF_31 020h BYTE OTP_EEPROM_PWM_BUFF_32 021h BYTE OTP_EEPROM_PWM_BUFF_33 022h BYTE OTP_EEPROM_PWM_BUFF_34 023h BYTE OTP_EEPROM_PWM_BUFF_35 024h BYTE OTP_EEPROM_PWM_BUFF_36 025h BYTE OTP_EEPROM_PWM_BUFF_37 026h BYTE OTP_EEPROM_PWM_BUFF_38 027h BYTE OTP_EEPROM_PWM_BUFF_39 028h BYTE OTP_EE...

Page 293: ...P_EEPROM_PWM_BUFF_60 03Dh BYTE OTP_EEPROM_PWM_BUFF_61 03Eh BYTE OTP_EEPROM_PWM_BUFF_62 03Fh BYTE OTP_EEPROM_PWM_BUFF_63 040h BYTE OTP_EEPROM_PWM_BUFF_64 041h BYTE OTP_EEPROM_PWM_BUFF_65 042h BYTE OTP_EEPROM_PWM_BUFF_66 043h BYTE OTP_EEPROM_PWM_BUFF_67 044h BYTE OTP_EEPROM_PWM_BUFF_68 045h BYTE OTP_EEPROM_PWM_BUFF_69 046h BYTE OTP_EEPROM_PWM_BUFF_70 047h BYTE OTP_EEPROM_PWM_BUFF_71 048h BYTE OTP_EE...

Page 294: ...OM_PWM_BUFF_92 05Dh BYTE OTP_EEPROM_PWM_BUFF_93 05Eh BYTE OTP_EEPROM_PWM_BUFF_94 05Fh BYTE OTP_EEPROM_PWM_BUFF_95 060h BYTE OTP_EEPROM_PWM_BUFF_96 061h BYTE OTP_EEPROM_PWM_BUFF_97 062h BYTE OTP_EEPROM_PWM_BUFF_98 063h BYTE OTP_EEPROM_PWM_BUFF_99 064h BYTE OTP_EEPROM_PWM_BUFF_100 065h BYTE OTP_EEPROM_PWM_BUFF_101 066h BYTE OTP_EEPROM_PWM_BUFF_102 067h BYTE OTP_EEPROM_PWM_BUFF_103 068h BYTE OTP_EEPR...

Page 295: ...WM_BUFF_120 079h BYTE OTP_EEPROM_PWM_BUFF_121 07Ah BYTE OTP_EEPROM_PWM_BUFF_122 07Bh BYTE OTP_EEPROM_PWM_BUFF_123 07Ch BYTE OTP_EEPROM_PWM_BUFF_124 07Dh BYTE OTP_EEPROM_PWM_BUFF_125 07Eh BYTE OTP_EEPROM_PWM_BUFF_126 07Fh BYTE OTP_EEPROM_PWM_BUFF_127 Table 400 BYTE OTP_EEPROM_PWM_BUFF_0 Bit Field Locations and Descriptions Offset Address Hex BYTE OTP_EEPROM_PWM_BUFF_0 Bit Field Locations D7 D6 D5 D...

Page 296: ...OTP EEPROM or PWM Table 402 BYTE OTP_EEPROM_PWM_BUFF_2 Bit Field Locations and Descriptions Offset Address Hex BYTE OTP_EEPROM_PWM_BUFF_2 Bit Field Locations D7 D6 D5 D4 D3 D2 D1 D0 002h DATA 7 0 BYTE OTP_EEPROM_PWM_BUFF_2 Bit Field Descriptions Bit Field Name Field Type Default Value Description DATA 7 0 R W 0 Data to be transferred into OTP EEPROM or PWM Table 403 BYTE OTP_EEPROM_PWM_BUFF_3 Bit ...

Page 297: ...OTP EEPROM or PWM Table 405 BYTE OTP_EEPROM_PWM_BUFF_5 Bit Field Locations and Descriptions Offset Address Hex BYTE OTP_EEPROM_PWM_BUFF_5 Bit Field Locations D7 D6 D5 D4 D3 D2 D1 D0 005h DATA 7 0 BYTE OTP_EEPROM_PWM_BUFF_5 Bit Field Descriptions Bit Field Name Field Type Default Value Description DATA 7 0 R W 0 Data to be transferred into OTP EEPROM or PWM Table 406 BYTE OTP_EEPROM_PWM_BUFF_6 Bit ...

Page 298: ...OTP EEPROM or PWM Table 408 BYTE OTP_EEPROM_PWM_BUFF_8 Bit Field Locations and Descriptions Offset Address Hex BYTE OTP_EEPROM_PWM_BUFF_8 Bit Field Locations D7 D6 D5 D4 D3 D2 D1 D0 008h DATA 7 0 BYTE OTP_EEPROM_PWM_BUFF_8 Bit Field Descriptions Bit Field Name Field Type Default Value Description DATA 7 0 R W 0 Data to be transferred into OTP EEPROM or PWM Table 409 BYTE OTP_EEPROM_PWM_BUFF_9 Bit ...

Page 299: ...OTP EEPROM or PWM Table 411 BYTE OTP_EEPROM_PWM_BUFF_11 Bit Field Locations and Descriptions Offset Address Hex BYTE OTP_EEPROM_PWM_BUFF_11 Bit Field Locations D7 D6 D5 D4 D3 D2 D1 D0 00Bh DATA 7 0 BYTE OTP_EEPROM_PWM_BUFF_11 Bit Field Descriptions Bit Field Name Field Type Default Value Description DATA 7 0 R W 0 Data to be transferred into OTP EEPROM or PWM Table 412 BYTE OTP_EEPROM_PWM_BUFF_12 ...

Page 300: ...OTP EEPROM or PWM Table 414 BYTE OTP_EEPROM_PWM_BUFF_14 Bit Field Locations and Descriptions Offset Address Hex BYTE OTP_EEPROM_PWM_BUFF_14 Bit Field Locations D7 D6 D5 D4 D3 D2 D1 D0 00Eh DATA 7 0 BYTE OTP_EEPROM_PWM_BUFF_14 Bit Field Descriptions Bit Field Name Field Type Default Value Description DATA 7 0 R W 0 Data to be transferred into OTP EEPROM or PWM Table 415 BYTE OTP_EEPROM_PWM_BUFF_15 ...

Page 301: ...OTP EEPROM or PWM Table 417 BYTE OTP_EEPROM_PWM_BUFF_17 Bit Field Locations and Descriptions Offset Address Hex BYTE OTP_EEPROM_PWM_BUFF_17 Bit Field Locations D7 D6 D5 D4 D3 D2 D1 D0 011h DATA 7 0 BYTE OTP_EEPROM_PWM_BUFF_17 Bit Field Descriptions Bit Field Name Field Type Default Value Description DATA 7 0 R W 0 Data to be transferred into OTP EEPROM or PWM Table 418 BYTE OTP_EEPROM_PWM_BUFF_18 ...

Page 302: ...OTP EEPROM or PWM Table 420 BYTE OTP_EEPROM_PWM_BUFF_20 Bit Field Locations and Descriptions Offset Address Hex BYTE OTP_EEPROM_PWM_BUFF_20 Bit Field Locations D7 D6 D5 D4 D3 D2 D1 D0 014h DATA 7 0 BYTE OTP_EEPROM_PWM_BUFF_20 Bit Field Descriptions Bit Field Name Field Type Default Value Description DATA 7 0 R W 0 Data to be transferred into OTP EEPROM or PWM Table 421 BYTE OTP_EEPROM_PWM_BUFF_21 ...

Page 303: ...OTP EEPROM or PWM Table 423 BYTE OTP_EEPROM_PWM_BUFF_23 Bit Field Locations and Descriptions Offset Address Hex BYTE OTP_EEPROM_PWM_BUFF_23 Bit Field Locations D7 D6 D5 D4 D3 D2 D1 D0 017h DATA 7 0 BYTE OTP_EEPROM_PWM_BUFF_23 Bit Field Descriptions Bit Field Name Field Type Default Value Description DATA 7 0 R W 0 Data to be transferred into OTP EEPROM or PWM Table 424 BYTE OTP_EEPROM_PWM_BUFF_24 ...

Page 304: ...OTP EEPROM or PWM Table 426 BYTE OTP_EEPROM_PWM_BUFF_26 Bit Field Locations and Descriptions Offset Address Hex BYTE OTP_EEPROM_PWM_BUFF_26 Bit Field Locations D7 D6 D5 D4 D3 D2 D1 D0 01Ah DATA 7 0 BYTE OTP_EEPROM_PWM_BUFF_26 Bit Field Descriptions Bit Field Name Field Type Default Value Description DATA 7 0 R W 0 Data to be transferred into OTP EEPROM or PWM Table 427 BYTE OTP_EEPROM_PWM_BUFF_27 ...

Page 305: ...OTP EEPROM or PWM Table 429 BYTE OTP_EEPROM_PWM_BUFF_29 Bit Field Locations and Descriptions Offset Address Hex BYTE OTP_EEPROM_PWM_BUFF_29 Bit Field Locations D7 D6 D5 D4 D3 D2 D1 D0 01Dh DATA 7 0 BYTE OTP_EEPROM_PWM_BUFF_29 Bit Field Descriptions Bit Field Name Field Type Default Value Description DATA 7 0 R W 0 Data to be transferred into OTP EEPROM or PWM Table 430 BYTE OTP_EEPROM_PWM_BUFF_30 ...

Page 306: ...OTP EEPROM or PWM Table 432 BYTE OTP_EEPROM_PWM_BUFF_32 Bit Field Locations and Descriptions Offset Address Hex BYTE OTP_EEPROM_PWM_BUFF_32 Bit Field Locations D7 D6 D5 D4 D3 D2 D1 D0 020h DATA 7 0 BYTE OTP_EEPROM_PWM_BUFF_32 Bit Field Descriptions Bit Field Name Field Type Default Value Description DATA 7 0 R W 0 Data to be transferred into OTP EEPROM or PWM Table 433 BYTE OTP_EEPROM_PWM_BUFF_33 ...

Page 307: ...OTP EEPROM or PWM Table 435 BYTE OTP_EEPROM_PWM_BUFF_35 Bit Field Locations and Descriptions Offset Address Hex BYTE OTP_EEPROM_PWM_BUFF_35 Bit Field Locations D7 D6 D5 D4 D3 D2 D1 D0 023h DATA 7 0 BYTE OTP_EEPROM_PWM_BUFF_35 Bit Field Descriptions Bit Field Name Field Type Default Value Description DATA 7 0 R W 0 Data to be transferred into OTP EEPROM or PWM Table 436 BYTE OTP_EEPROM_PWM_BUFF_36 ...

Page 308: ...OTP EEPROM or PWM Table 438 BYTE OTP_EEPROM_PWM_BUFF_38 Bit Field Locations and Descriptions Offset Address Hex BYTE OTP_EEPROM_PWM_BUFF_38 Bit Field Locations D7 D6 D5 D4 D3 D2 D1 D0 026h DATA 7 0 BYTE OTP_EEPROM_PWM_BUFF_38 Bit Field Descriptions Bit Field Name Field Type Default Value Description DATA 7 0 R W 0 Data to be transferred into OTP EEPROM or PWM Table 439 BYTE OTP_EEPROM_PWM_BUFF_39 ...

Page 309: ...OTP EEPROM or PWM Table 441 BYTE OTP_EEPROM_PWM_BUFF_41 Bit Field Locations and Descriptions Offset Address Hex BYTE OTP_EEPROM_PWM_BUFF_41 Bit Field Locations D7 D6 D5 D4 D3 D2 D1 D0 029h DATA 7 0 BYTE OTP_EEPROM_PWM_BUFF_41 Bit Field Descriptions Bit Field Name Field Type Default Value Description DATA 7 0 R W 0 Data to be transferred into OTP EEPROM or PWM Table 442 BYTE OTP_EEPROM_PWM_BUFF_42 ...

Page 310: ...OTP EEPROM or PWM Table 444 BYTE OTP_EEPROM_PWM_BUFF_44 Bit Field Locations and Descriptions Offset Address Hex BYTE OTP_EEPROM_PWM_BUFF_44 Bit Field Locations D7 D6 D5 D4 D3 D2 D1 D0 02Ch DATA 7 0 BYTE OTP_EEPROM_PWM_BUFF_44 Bit Field Descriptions Bit Field Name Field Type Default Value Description DATA 7 0 R W 0 Data to be transferred into OTP EEPROM or PWM Table 445 BYTE OTP_EEPROM_PWM_BUFF_45 ...

Page 311: ...OTP EEPROM or PWM Table 447 BYTE OTP_EEPROM_PWM_BUFF_47 Bit Field Locations and Descriptions Offset Address Hex BYTE OTP_EEPROM_PWM_BUFF_47 Bit Field Locations D7 D6 D5 D4 D3 D2 D1 D0 02Fh DATA 7 0 BYTE OTP_EEPROM_PWM_BUFF_47 Bit Field Descriptions Bit Field Name Field Type Default Value Description DATA 7 0 R W 0 Data to be transferred into OTP EEPROM or PWM Table 448 BYTE OTP_EEPROM_PWM_BUFF_48 ...

Page 312: ...OTP EEPROM or PWM Table 450 BYTE OTP_EEPROM_PWM_BUFF_50 Bit Field Locations and Descriptions Offset Address Hex BYTE OTP_EEPROM_PWM_BUFF_50 Bit Field Locations D7 D6 D5 D4 D3 D2 D1 D0 032h DATA 7 0 BYTE OTP_EEPROM_PWM_BUFF_50 Bit Field Descriptions Bit Field Name Field Type Default Value Description DATA 7 0 R W 0 Data to be transferred into OTP EEPROM or PWM Table 451 BYTE OTP_EEPROM_PWM_BUFF_51 ...

Page 313: ...OTP EEPROM or PWM Table 453 BYTE OTP_EEPROM_PWM_BUFF_53 Bit Field Locations and Descriptions Offset Address Hex BYTE OTP_EEPROM_PWM_BUFF_53 Bit Field Locations D7 D6 D5 D4 D3 D2 D1 D0 035h DATA 7 0 BYTE OTP_EEPROM_PWM_BUFF_53 Bit Field Descriptions Bit Field Name Field Type Default Value Description DATA 7 0 R W 0 Data to be transferred into OTP EEPROM or PWM Table 454 BYTE OTP_EEPROM_PWM_BUFF_54 ...

Page 314: ...OTP EEPROM or PWM Table 456 BYTE OTP_EEPROM_PWM_BUFF_56 Bit Field Locations and Descriptions Offset Address Hex BYTE OTP_EEPROM_PWM_BUFF_56 Bit Field Locations D7 D6 D5 D4 D3 D2 D1 D0 038h DATA 7 0 BYTE OTP_EEPROM_PWM_BUFF_56 Bit Field Descriptions Bit Field Name Field Type Default Value Description DATA 7 0 R W 0 Data to be transferred into OTP EEPROM or PWM Table 457 BYTE OTP_EEPROM_PWM_BUFF_57 ...

Page 315: ...OTP EEPROM or PWM Table 459 BYTE OTP_EEPROM_PWM_BUFF_59 Bit Field Locations and Descriptions Offset Address Hex BYTE OTP_EEPROM_PWM_BUFF_59 Bit Field Locations D7 D6 D5 D4 D3 D2 D1 D0 03Bh DATA 7 0 BYTE OTP_EEPROM_PWM_BUFF_59 Bit Field Descriptions Bit Field Name Field Type Default Value Description DATA 7 0 R W 0 Data to be transferred into OTP EEPROM or PWM Table 460 BYTE OTP_EEPROM_PWM_BUFF_60 ...

Page 316: ...OTP EEPROM or PWM Table 462 BYTE OTP_EEPROM_PWM_BUFF_62 Bit Field Locations and Descriptions Offset Address Hex BYTE OTP_EEPROM_PWM_BUFF_62 Bit Field Locations D7 D6 D5 D4 D3 D2 D1 D0 03Eh DATA 7 0 BYTE OTP_EEPROM_PWM_BUFF_62 Bit Field Descriptions Bit Field Name Field Type Default Value Description DATA 7 0 R W 0 Data to be transferred into OTP EEPROM or PWM Table 463 BYTE OTP_EEPROM_PWM_BUFF_63 ...

Page 317: ...OTP EEPROM or PWM Table 465 BYTE OTP_EEPROM_PWM_BUFF_65 Bit Field Locations and Descriptions Offset Address Hex BYTE OTP_EEPROM_PWM_BUFF_65 Bit Field Locations D7 D6 D5 D4 D3 D2 D1 D0 041h DATA 7 0 BYTE OTP_EEPROM_PWM_BUFF_65 Bit Field Descriptions Bit Field Name Field Type Default Value Description DATA 7 0 R W 0 Data to be transferred into OTP EEPROM or PWM Table 466 BYTE OTP_EEPROM_PWM_BUFF_66 ...

Page 318: ...OTP EEPROM or PWM Table 468 BYTE OTP_EEPROM_PWM_BUFF_68 Bit Field Locations and Descriptions Offset Address Hex BYTE OTP_EEPROM_PWM_BUFF_68 Bit Field Locations D7 D6 D5 D4 D3 D2 D1 D0 044h DATA 7 0 BYTE OTP_EEPROM_PWM_BUFF_68 Bit Field Descriptions Bit Field Name Field Type Default Value Description DATA 7 0 R W 0 Data to be transferred into OTP EEPROM or PWM Table 469 BYTE OTP_EEPROM_PWM_BUFF_69 ...

Page 319: ...OTP EEPROM or PWM Table 471 BYTE OTP_EEPROM_PWM_BUFF_71 Bit Field Locations and Descriptions Offset Address Hex BYTE OTP_EEPROM_PWM_BUFF_71 Bit Field Locations D7 D6 D5 D4 D3 D2 D1 D0 047h DATA 7 0 BYTE OTP_EEPROM_PWM_BUFF_71 Bit Field Descriptions Bit Field Name Field Type Default Value Description DATA 7 0 R W 0 Data to be transferred into OTP EEPROM or PWM Table 472 BYTE OTP_EEPROM_PWM_BUFF_72 ...

Page 320: ...OTP EEPROM or PWM Table 474 BYTE OTP_EEPROM_PWM_BUFF_74 Bit Field Locations and Descriptions Offset Address Hex BYTE OTP_EEPROM_PWM_BUFF_74 Bit Field Locations D7 D6 D5 D4 D3 D2 D1 D0 04Ah DATA 7 0 BYTE OTP_EEPROM_PWM_BUFF_74 Bit Field Descriptions Bit Field Name Field Type Default Value Description DATA 7 0 R W 0 Data to be transferred into OTP EEPROM or PWM Table 475 BYTE OTP_EEPROM_PWM_BUFF_75 ...

Page 321: ...OTP EEPROM or PWM Table 477 BYTE OTP_EEPROM_PWM_BUFF_77 Bit Field Locations and Descriptions Offset Address Hex BYTE OTP_EEPROM_PWM_BUFF_77 Bit Field Locations D7 D6 D5 D4 D3 D2 D1 D0 04Dh DATA 7 0 BYTE OTP_EEPROM_PWM_BUFF_77 Bit Field Descriptions Bit Field Name Field Type Default Value Description DATA 7 0 R W 0 Data to be transferred into OTP EEPROM or PWM Table 478 BYTE OTP_EEPROM_PWM_BUFF_78 ...

Page 322: ...OTP EEPROM or PWM Table 480 BYTE OTP_EEPROM_PWM_BUFF_80 Bit Field Locations and Descriptions Offset Address Hex BYTE OTP_EEPROM_PWM_BUFF_80 Bit Field Locations D7 D6 D5 D4 D3 D2 D1 D0 050h DATA 7 0 BYTE OTP_EEPROM_PWM_BUFF_80 Bit Field Descriptions Bit Field Name Field Type Default Value Description DATA 7 0 R W 0 Data to be transferred into OTP EEPROM or PWM Table 481 BYTE OTP_EEPROM_PWM_BUFF_81 ...

Page 323: ...OTP EEPROM or PWM Table 483 BYTE OTP_EEPROM_PWM_BUFF_83 Bit Field Locations and Descriptions Offset Address Hex BYTE OTP_EEPROM_PWM_BUFF_83 Bit Field Locations D7 D6 D5 D4 D3 D2 D1 D0 053h DATA 7 0 BYTE OTP_EEPROM_PWM_BUFF_83 Bit Field Descriptions Bit Field Name Field Type Default Value Description DATA 7 0 R W 0 Data to be transferred into OTP EEPROM or PWM Table 484 BYTE OTP_EEPROM_PWM_BUFF_84 ...

Page 324: ...OTP EEPROM or PWM Table 486 BYTE OTP_EEPROM_PWM_BUFF_86 Bit Field Locations and Descriptions Offset Address Hex BYTE OTP_EEPROM_PWM_BUFF_86 Bit Field Locations D7 D6 D5 D4 D3 D2 D1 D0 056h DATA 7 0 BYTE OTP_EEPROM_PWM_BUFF_86 Bit Field Descriptions Bit Field Name Field Type Default Value Description DATA 7 0 R W 0 Data to be transferred into OTP EEPROM or PWM Table 487 BYTE OTP_EEPROM_PWM_BUFF_87 ...

Page 325: ...OTP EEPROM or PWM Table 489 BYTE OTP_EEPROM_PWM_BUFF_89 Bit Field Locations and Descriptions Offset Address Hex BYTE OTP_EEPROM_PWM_BUFF_89 Bit Field Locations D7 D6 D5 D4 D3 D2 D1 D0 059h DATA 7 0 BYTE OTP_EEPROM_PWM_BUFF_89 Bit Field Descriptions Bit Field Name Field Type Default Value Description DATA 7 0 R W 0 Data to be transferred into OTP EEPROM or PWM Table 490 BYTE OTP_EEPROM_PWM_BUFF_90 ...

Page 326: ...OTP EEPROM or PWM Table 492 BYTE OTP_EEPROM_PWM_BUFF_92 Bit Field Locations and Descriptions Offset Address Hex BYTE OTP_EEPROM_PWM_BUFF_92 Bit Field Locations D7 D6 D5 D4 D3 D2 D1 D0 05Ch DATA 7 0 BYTE OTP_EEPROM_PWM_BUFF_92 Bit Field Descriptions Bit Field Name Field Type Default Value Description DATA 7 0 R W 0 Data to be transferred into OTP EEPROM or PWM Table 493 BYTE OTP_EEPROM_PWM_BUFF_93 ...

Page 327: ...OTP EEPROM or PWM Table 495 BYTE OTP_EEPROM_PWM_BUFF_95 Bit Field Locations and Descriptions Offset Address Hex BYTE OTP_EEPROM_PWM_BUFF_95 Bit Field Locations D7 D6 D5 D4 D3 D2 D1 D0 05Fh DATA 7 0 BYTE OTP_EEPROM_PWM_BUFF_95 Bit Field Descriptions Bit Field Name Field Type Default Value Description DATA 7 0 R W 0 Data to be transferred into OTP EEPROM or PWM Table 496 BYTE OTP_EEPROM_PWM_BUFF_96 ...

Page 328: ...OTP EEPROM or PWM Table 498 BYTE OTP_EEPROM_PWM_BUFF_98 Bit Field Locations and Descriptions Offset Address Hex BYTE OTP_EEPROM_PWM_BUFF_98 Bit Field Locations D7 D6 D5 D4 D3 D2 D1 D0 062h DATA 7 0 BYTE OTP_EEPROM_PWM_BUFF_98 Bit Field Descriptions Bit Field Name Field Type Default Value Description DATA 7 0 R W 0 Data to be transferred into OTP EEPROM or PWM Table 499 BYTE OTP_EEPROM_PWM_BUFF_99 ...

Page 329: ...OTP EEPROM or PWM Table 501 BYTE OTP_EEPROM_PWM_BUFF_101 Bit Field Locations and Descriptions Offset Address Hex BYTE OTP_EEPROM_PWM_BUFF_101 Bit Field Locations D7 D6 D5 D4 D3 D2 D1 D0 065h DATA 7 0 BYTE OTP_EEPROM_PWM_BUFF_101 Bit Field Descriptions Bit Field Name Field Type Default Value Description DATA 7 0 R W 0 Data to be transferred into OTP EEPROM or PWM Table 502 BYTE OTP_EEPROM_PWM_BUFF_...

Page 330: ...OTP EEPROM or PWM Table 504 BYTE OTP_EEPROM_PWM_BUFF_104 Bit Field Locations and Descriptions Offset Address Hex BYTE OTP_EEPROM_PWM_BUFF_104 Bit Field Locations D7 D6 D5 D4 D3 D2 D1 D0 068h DATA 7 0 BYTE OTP_EEPROM_PWM_BUFF_104 Bit Field Descriptions Bit Field Name Field Type Default Value Description DATA 7 0 R W 0 Data to be transferred into OTP EEPROM or PWM Table 505 BYTE OTP_EEPROM_PWM_BUFF_...

Page 331: ...OTP EEPROM or PWM Table 507 BYTE OTP_EEPROM_PWM_BUFF_107 Bit Field Locations and Descriptions Offset Address Hex BYTE OTP_EEPROM_PWM_BUFF_107 Bit Field Locations D7 D6 D5 D4 D3 D2 D1 D0 06Bh DATA 7 0 BYTE OTP_EEPROM_PWM_BUFF_107 Bit Field Descriptions Bit Field Name Field Type Default Value Description DATA 7 0 R W 0 Data to be transferred into OTP EEPROM or PWM Table 508 BYTE OTP_EEPROM_PWM_BUFF_...

Page 332: ...OTP EEPROM or PWM Table 510 BYTE OTP_EEPROM_PWM_BUFF_110 Bit Field Locations and Descriptions Offset Address Hex BYTE OTP_EEPROM_PWM_BUFF_110 Bit Field Locations D7 D6 D5 D4 D3 D2 D1 D0 06Eh DATA 7 0 BYTE OTP_EEPROM_PWM_BUFF_110 Bit Field Descriptions Bit Field Name Field Type Default Value Description DATA 7 0 R W 0 Data to be transferred into OTP EEPROM or PWM Table 511 BYTE OTP_EEPROM_PWM_BUFF_...

Page 333: ...OTP EEPROM or PWM Table 513 BYTE OTP_EEPROM_PWM_BUFF_113 Bit Field Locations and Descriptions Offset Address Hex BYTE OTP_EEPROM_PWM_BUFF_113 Bit Field Locations D7 D6 D5 D4 D3 D2 D1 D0 071h DATA 7 0 BYTE OTP_EEPROM_PWM_BUFF_113 Bit Field Descriptions Bit Field Name Field Type Default Value Description DATA 7 0 R W 0 Data to be transferred into OTP EEPROM or PWM Table 514 BYTE OTP_EEPROM_PWM_BUFF_...

Page 334: ...OTP EEPROM or PWM Table 516 BYTE OTP_EEPROM_PWM_BUFF_116 Bit Field Locations and Descriptions Offset Address Hex BYTE OTP_EEPROM_PWM_BUFF_116 Bit Field Locations D7 D6 D5 D4 D3 D2 D1 D0 074h DATA 7 0 BYTE OTP_EEPROM_PWM_BUFF_116 Bit Field Descriptions Bit Field Name Field Type Default Value Description DATA 7 0 R W 0 Data to be transferred into OTP EEPROM or PWM Table 517 BYTE OTP_EEPROM_PWM_BUFF_...

Page 335: ...OTP EEPROM or PWM Table 519 BYTE OTP_EEPROM_PWM_BUFF_119 Bit Field Locations and Descriptions Offset Address Hex BYTE OTP_EEPROM_PWM_BUFF_119 Bit Field Locations D7 D6 D5 D4 D3 D2 D1 D0 077h DATA 7 0 BYTE OTP_EEPROM_PWM_BUFF_119 Bit Field Descriptions Bit Field Name Field Type Default Value Description DATA 7 0 R W 0 Data to be transferred into OTP EEPROM or PWM Table 520 BYTE OTP_EEPROM_PWM_BUFF_...

Page 336: ...OTP EEPROM or PWM Table 522 BYTE OTP_EEPROM_PWM_BUFF_122 Bit Field Locations and Descriptions Offset Address Hex BYTE OTP_EEPROM_PWM_BUFF_122 Bit Field Locations D7 D6 D5 D4 D3 D2 D1 D0 07Ah DATA 7 0 BYTE OTP_EEPROM_PWM_BUFF_122 Bit Field Descriptions Bit Field Name Field Type Default Value Description DATA 7 0 R W 0 Data to be transferred into OTP EEPROM or PWM Table 523 BYTE OTP_EEPROM_PWM_BUFF_...

Page 337: ...OTP EEPROM or PWM Table 525 BYTE OTP_EEPROM_PWM_BUFF_125 Bit Field Locations and Descriptions Offset Address Hex BYTE OTP_EEPROM_PWM_BUFF_125 Bit Field Locations D7 D6 D5 D4 D3 D2 D1 D0 07Dh DATA 7 0 BYTE OTP_EEPROM_PWM_BUFF_125 Bit Field Descriptions Bit Field Name Field Type Default Value Description DATA 7 0 R W 0 Data to be transferred into OTP EEPROM or PWM Table 526 BYTE OTP_EEPROM_PWM_BUFF_...

Page 338: ...YTE OTP_EEPROM_PWM_BUFF_127 Bit Field Locations and Descriptions Offset Address Hex BYTE OTP_EEPROM_PWM_BUFF_127 Bit Field Locations D7 D6 D5 D4 D3 D2 D1 D0 07Fh DATA 7 0 BYTE OTP_EEPROM_PWM_BUFF_127 Bit Field Descriptions Bit Field Name Field Type Default Value Description DATA 7 0 R W 0 Data to be transferred into OTP EEPROM or PWM ...

Page 339: ...ommander Personality v5 x Added hardware revision ID register to the documentation June 11 2018 Updated Additional Documents table to match current datasheets February 23 2018 Updated to match v4 5 register map Pipeline 10035 and Timing Commander Personality v4 x February 21 2018 Updated introductory text to highlight trigger register functionality Removed older history associated with Rev A silic...

Page 340: ...de and does not convey any license under intellectual property rights of IDT or any third parties IDT s products are not intended for use in applications involving extreme environmental conditions or in life support systems or similar devices where the failure or malfunction of an IDT product can be rea sonably expected to significantly affect the health or safety of users Anyone using an IDT prod...

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