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IDT   Link Operation

PES48T12G2 User Manual

6 - 9

April 5, 2013

Notes

–

When software sets the Link Retrain (LRET) bit in the PCIELCTL register and the PES48T12G2

port has recorded support for the higher speed by its link partner.

1

When operating at 5.0 GT/s, a PES48T12G2 port initiates a link speed downgrade in the following

cases:

–

When the PHY layer cannot achieve reliable operation at the higher speed. In this case, the

switch’s port continues to support the higher speed in the training-sets it transmits during link

training.

–

When software sets the target link speed to 2.5 GT/s and sets the LRET bit in the PCIELCTL

register. In this case, the switch’s port removes support for the higher speed in the training-sets it

transmits during link training.

Additionally, the PES48T12G2 ports always respond to link partner requests to change speed. In this

case, the speed change is only successful when both components in the link advertise support the target
speed. When a link speed upgrade operation fails, the PHY LTSSM reverts back to the speed before the
upgrade (i.e., 2.5 GT/s) and does not autonomously initiate a subsequent link speed upgrade. In this case,
the PHY continues to support Gen1 and Gen2 data rates and therefore responds to link partner requests for
link speed upgrade, or to link speed upgrades triggered by software setting the LRET bit in the port’s
PCIELCTL register.

The PES48T12G2 ports do not have a mechanism to autonomously regulate link speed. As a result, the

Hardware Autonomous Speed Disable (HASD) bit in the PCIELCTL2 register has no effect and is hardwired
to 0x0. Additionally, PES48T12G2 ports never set the ‘Autonomous Change’ bit in the training sets
exchanged with the link partner during link training

2

. Still, a link partner connected to a PES48T12G2 down-

stream port may autonomously change link speed. When this occurs, the PES48T12G2 downstream port
sets the Link Autonomous Bandwidth Status (LABWSTS) bit in the PCIELSTS register.

A system designer may limit the maximum speed at which each port operates by changing the target

link speed via software or EEPROM and forcing link retraining. Refer to section Link Retraining on page 6-
10 for further details.

Software Management of Link Speed

Software can interact with the link control and status registers of downstream ports to set the link speed,

as well as receive notification of link speed changes. This gives software the capability to choose the
desired link speed based on system specific criteria. For example, depending on the traffic load expected
on a link, software can choose to downgrade link speed to 2.5 GT/s in order to reduce power on a low-traffic
link, and later upgrade the link to 5.0 GT/s when the bandwidth is required. Software may also choose to
change the link speed due to link reliability reasons (i.e., a link that has reliability problems at 5.0 GT/s may
be downgraded to 2.5 GT/s).

As mentioned above, the Target Link Speed (TLS) field of the port’s Link Control 2 Register

(PCIELCTL2) sets the preferred link speed. By default, the Target Link Speed of each PES48T12G2 port is
set to 5.0 GT/s. During normal operation, the link speed of a downstream port may be modified by setting
the TLS field of the port’s PCIELCTL2 register to the desired speed and initiating link retraining by writing a
one to the Link Retrain (LRET) bit in the Link Control (PCIELCTL) register.

–

The port will only initiate a change to a higher speed if the link partner advertised support for the

higher speed in its latest entry to the Configuration.Complete or Recovery.RcvrCfg states.

–

If a speed change is initiated to a speed not supported by the link partner, then the port will remain

at the current speed by transitioning through the Recovery state without the “Speed_Change” bit

set.

1. 

The speed advertisement of the link partner is noted by PES48T12G2 in the latest LTSSM entry to the Configu-

ration.Complete or Recovery.RcvrCfg sub-states.

2. 

Note that the ‘Autonomous Change’ bit is located in bit 6 of the fourth symbol in the training sets. This bit has 

multiple meanings depending on the LTSSM state in which it is issued. PES48T12G2 never sets this bit in LTSSM 
states in which this bit carries the ‘autonomous change’ meaning.

Summary of Contents for 89HPES48T12G2

Page 1: ...Creek Valley Road San Jose California 95138 Telephone 800 345 7015 408 284 8200 FAX 408 284 2775 Printed in U S A 2013 Integrated Device Technology Inc IDT 89HPES48T12G2 PCI Express Switch User Manua...

Page 2: ...PLES CONTAINED IN ANY IDT PUBLICATION OR PUBLIC DISCLOSURE OR THAT IS CONTAINED ON ANY IDT INTERNET SITE IN NO EVENT WILL IDT BE LIABLE FOR ANY DIRECT CONSEQUENTIAL INCIDENTAL INDIRECT PUNITIVE OR SPE...

Page 3: ...version link width negotiation and lane reversal Chapter 7 SerDes describes basic functionality and controllability associated with the Serialiazer Deserializer SerDes block in PES48T12G2 ports Chapte...

Page 4: ...level To define buses the most significant bit MSB will be on the left and least significant bit LSB will be on the right No leading zeros will be included Throughout this manual when describing sign...

Page 5: ...re or hardware mechanisms such as pin strapping or serial EEPROM System firmware hard ware initialization is only allowed for system integrated devices Bits are read only after initialization and can...

Page 6: ...Read Only RO Software can only read registers bits with this attribute Contents are hardwired to a constant value or are status bits that may be set and cleared by hardware Writing to a RO location h...

Page 7: ...5 and Figure 12 8 In Chapter 14 added section Partial Byte Access to Word and DWord Registers In Chapter 16 added bit BDISCARD to the Switch Control register and changed bit 26 in the SMBus Status reg...

Page 8: ...to each description in the PCIESCTLIV register In Chapter 16 added FEN and FCAPSEL fields to SWPART x CTL register and SWPORT x CTL registers added PFAILOVER and SFAILOVER fields to SWPART X STS regi...

Page 9: ...sion ID 1 6 JTAG ID 1 6 SSID SSVID 1 6 Device Serial Number Enhanced Capability 1 6 Pin Description 1 7 Pin Characteristics 1 13 Architectural Overview Introduction 2 1 Logical View 2 2 Switch Core In...

Page 10: ...ion in the PES48T12G2 6 7 Software Management of Link Speed 6 9 Link Retraining 6 10 Link Down 6 10 Slot Power Limit Support 6 11 Upstream Port 6 11 Downstream Port 6 11 Link States 6 11 Active State...

Page 11: ...8 16 Bus Locking 8 17 Hot Plug and Hot Swap Introduction 9 1 Hot Plug Signals 9 3 Port Reset Outputs 9 4 Power Enable Controlled Reset Output 9 5 Power Good Controlled Reset Output 9 5 Hot Plug Events...

Page 12: ...ture 15 27 Message Signaled Interrupt Capability Structure 15 29 Subsystem ID and Subsystem Vendor ID 15 31 Extended Configuration Space Access Registers 15 31 Advanced Error Reporting AER Enhanced Ca...

Page 13: ...cess Point 17 1 Signal Definitions 17 1 Boundary Scan Chain 17 2 Test Data Register DR 17 5 Boundary Scan Registers 17 5 Instruction Register IR 17 7 EXTEST 17 8 SAMPLE PRELOAD 17 8 BYPASS 17 8 CLAMP...

Page 14: ...IDT Table of Contents PES48T12G2 User Manual vi April 5 2013 Notes...

Page 15: ...ansmit Driver Settings in Gen2 Mode with 6 0dB de emphasis 7 8 Table 7 5 Transmitter Slew Rate Settings 7 11 Table 7 6 PCI Express Transmit Margining Levels supported by the PES48T12G2 7 12 Table 7 7...

Page 16: ...able 12 12 Slave SMBus Command Code Fields 12 14 Table 12 13 CSR Register Read or Write Operation Byte Sequence 12 15 Table 12 14 CSR Register Read or Write CMD Field Description 12 16 Table 12 15 Ser...

Page 17: ...the PHY Operates in Gen1 Data Rate with 3 5 dB Nominal de emphasis 7 10 Figure 7 2 De emphasis Applied on Link as a Function of the Fine de emphasis and Transmit Drive Level Controls when the PHY Oper...

Page 18: ...ter Read Using SMBus Read and Write Transactions with PEC Disabled 12 19 Figure 13 1 Multicast Group Address Ranges 13 2 Figure 13 2 Multicast Group Address Region Determination 13 3 Figure 14 1 PCI t...

Page 19: ...0x002 15 1 ECFGADDR Extended Configuration Space Access Address 0x0F8 15 31 ECFGDATA Extended Configuration Space Access Data 0x0FC 15 32 EEPROMINTF Serial EEPROM Interface 0x0AD0 16 19 EROMBASE Expan...

Page 20: ...R Message Signaled Interrupt Address 0x0D4 15 30 MSICAP Message Signaled Interrupt Capability and Control 0x0D0 15 29 MSIMDATA Message Signaled Interrupt Message Data 0x0DC 15 30 MSIUADDR Message Sign...

Page 21: ...Lane Control 16 12 S 13 12 9 0 TXLCTL0 SerDes x Transmitter Lane Control 0 16 6 S 13 12 9 0 TXLCTL1 SerDes x Transmitter Lane Control 1 16 9 SBUSN Secondary Bus Number Register 0x019 15 5 SECSTS Secon...

Page 22: ...IDT Register List PES48T12G2 User Manual xiv April 5 2013 Notes...

Page 23: ...th PCI Express Base Specification Revision 2 0 Features High Performance Non Blocking Switch Architecture 48 lane 12 port PCIe switch Six x8 ports switch ports each of which can bifurcate to two x4 po...

Page 24: ...g Supports 100 MHz and 125 MHz reference clock frequencies Flexible clocking modes Common clock Non common clock Hot Plug and Hot Swap Hot plug controller on all ports Hot plug supported on all downst...

Page 25: ...t modes Supports IEEE 1149 6 AC JTAG and IEEE 1149 1 JTAG Power Supplies Requires only two power supply voltages 1 0 V and 2 5 V No power sequencing requirements Packaged in a 27mm x 27mm 676 ball Fli...

Page 26: ...User Manual 1 4 April 5 2013 Notes Note There are no ports 10 and 11 in the PES48T12G2 device 5 0x4 6 0x4 7 0x4 8 0x4 9 0x4 12 0x4 13 0x4 Port PCIELCAP MAXLNKWDTH Table 1 1 Initial Configuration Regi...

Page 27: ...witch SerDes Output Port 0 Port 0 PE09RP 3 0 PE09RN 3 0 PCI Express Switch SerDes Input PE09TP 3 0 PE09TN 3 0 PCI Express Switch SerDes Output Port 9 Port 9 PE13RP 3 0 PE13RN 3 0 PCI Express Switch Se...

Page 28: ...D fields in the Subsystem ID and Subsystem Vendor ID SSIDSSVID register must be initialized with the appropriate ID values the Next Pointer NXTPTR field in one of the other enhanced capabilities shoul...

Page 29: ...ress receive pairs for port 2 PE02TP 3 0 PE02TN 3 0 O PCI Express Port 2 Serial Data Transmit Differential PCI Express trans mit pairs for port 2 PE03RP 3 0 PE03RN 3 0 I PCI Express Port 3 Serial Data...

Page 30: ...press Port 13 Serial Data Receive Differential PCI Express receive pairs for port 13 When port 12 is merged with port 13 these sig nals become port 12 receive pairs for lanes 4 through 7 PE13TP 3 0 PE...

Page 31: ...ernate function pin type Output 2nd Alternate function Port 0 Link Active Status Output GPIO 6 I General Purpose I O This pin can be configured as a general purpose I O pin GPIO 7 I O General Purpose...

Page 32: ...When this pin is low port 6 is merged with port 7 to form a single x8 port The Serdes lanes associated with port 7 become lanes 4 through 7 of port 6 Refer to section Port Merging on page 5 6 for deta...

Page 33: ...sabled 0xB Single partition with Serial EEPROM initialization and port 2 selected as the upstream port port 0 disabled 0xE Reserved 0xF Reserved Signal Type Name Description JTAG_TCK I JTAG Clock This...

Page 34: ...vides a reference for the PLL bias currents and PLL calibration circuitry A 3K Ohm 1 resistor should be connected from this pin to ground VDDCORE I Core VDD Power supply for core logic 1 0V VDDI O I I...

Page 35: ...ft floating Finally No Connection pins should not be connected Function Pin Name Type Buffer I O Type Internal Resistor1 Notes PCI Express Interface PE00RN 3 0 I PCIe Differential2 Serial Link PE00RP...

Page 36: ...up on board SSMBADDR 2 1 I Input pull up SSMBCLK I O STI pull up on board SSMBDAT I O STI pull up on board General Pur pose I O GPIO 8 0 I O LVTTL STI High Drive pull up System Pins CLKMODE 1 0 I LVTT...

Page 37: ...REFRES08 I O REFRES09 I O REFRES12 I O REFRES13 I O REFRESPLL I O 1 Internal resistor values under typical operating conditions are 92K for pull up and 91K for pull down 2 All receiver pins set the D...

Page 38: ...IDT PES48T12G2 Device Overview PES48T12G2 User Manual 1 16 April 5 2013 Notes...

Page 39: ...rt performs switch application layer functions such as TLP routing using route map tables processing configuration read and write requests etc The switch core is responsible for transferring TLPs betw...

Page 40: ...CIe switch are interconnected by a virtual PCI bus The primary side of the upstream port s PCI to PCI bridge is associated with the external link while the secondary side connects to the virtual PCI b...

Page 41: ...nder going ordering and arbitration they are transferred to the corresponding egress buffer via the crossbar interconnect The presence of egress buffers provides head of line blocking HOLB relief when...

Page 42: ...lay buffer This allows for efficient use of the egress buffer space when transmitted packets are not being acknowledged by the link partner the replay buffer grows to allow further transmission when t...

Page 43: ...the port merged or bifurcated and the width and speed of the port s link Packets received from the port are stored in the appropriate IFB queue After being queued in an IFB1 and undergoing ordering an...

Page 44: ...relaxed ordering attribute in packets as shown in the table Arbitration Packets stored in the ingress buffers are subject to arbitration as they are moved towards the egress port The switch core perf...

Page 45: ...be simultaneously routed across the switch and transferred on the egress link The entire TLP need not be received and buffered prior to starting the routing process i e store and forward This reduces...

Page 46: ...fully store it in the EFB as it is transferred towards the egress link 1 During cut through transfers the crossbar maintains the connection between the appropriate IFB and EFB through out the duratio...

Page 47: ...up to 4 KB of completion data being returned to the requester Depending on system architecture and configured maximum payload size this completion data may be returned as a single completion TLP or m...

Page 48: ...operation is illustrated Figure 3 4 Figure 3 4 a shows requests injection without request metering Figure 3 4 b shows requests injection with request metering Request metering is imple mented by logi...

Page 49: ...ounter The count represents a signed magnitude fixed point 0 13 11 number i e a positive number with 13 integer bits and 11 fractional bits but is treated by the logic as a 24 bit unsigned integer The...

Page 50: ...es it to become negative The computation that occurs on each clock tick by the request metering counter is shown Figure 3 7 Link Width Link Speed Decrement Value Notes x1 Gen 1 0x02 Corresponds to 1 B...

Page 51: ...ion and all values are implicitly converted to this value Figure 3 8 Non Posted Read Request Completion Size Estimate Computation The number of data DWords in a non posted request TLP is estimated by...

Page 52: ...IG Internal Error Reporting ECN The reporting of internal errors may be disabled by clearing the Internal Error Reporting Enable IERROREN bit in the port s Internal Error Reporting Control IERRORCTL r...

Page 53: ...ity in which the error was detected i e single bit error correction is not disabled when a double bit error is detected and a double bit error may result in one or more single bit corrections Associat...

Page 54: ...ected during a DL layer replay then all TLPs in the replay buffer are flushed In addition to TLPs that flow through the switch cases exist in which TLPs are produced and consumed by the switch e g con...

Page 55: ...ocking SSC The global reference clock input is provided to each SerDes quad and to an on chip PLL The on chip PLL uses this clock to generate a 250 MHz core clock that is used by internal switch logic...

Page 56: ...ent of whether or not the port uses the same reference clock source as the link partner A one in the SCLK field indicates that the port and its link partner use the same reference clock source This is...

Page 57: ...nated as Read Write when Unlocked RWL are implicitly SWSticky Their value is preserved across all resets except a switch fundamental reset Boot Configuration Vector A boot configuration vector consist...

Page 58: ...ts See Table 4 1 for a definition of the encoding of these signals The value of these signals may be overridden by modifying the Port Clocking Mode PCLKMODE register P01MERGEN N Ports 0 and 1 Merge Th...

Page 59: ...he slave SMBus is taken out of reset and initialized The slave SMBus address is specified by the SSMBADDR 2 1 signals in the boot configuration vector 11 If the sampled Switch Mode SWMODE 3 0 state co...

Page 60: ...iguration prior to initiation of these side effects The operation of a switch fundamental reset with serial EEPROM initialization is illustrated in Figure 5 1 Figure 5 1 Switch Fundamental Reset with...

Page 61: ...port is in the Disabled LTSSM state then a hot reset will not be propagated out on that port The port will instead transition to the Detect LTSSM state Although not a hot reset this has the same funct...

Page 62: ...arded Wait for software to clear the Secondary Bus Reset SRESET bit in the downstream port s Bridge Control Register BCTL Normal downstream port operation begins The operation of the upstream port is...

Page 63: ...t part of the PCI Express hierarchy The port is not associated with any switch partition The port is unaffected by the state of any switch partition and vice versa Unused logic is placed in a low powe...

Page 64: ...IDT Reset and Initialization PES48T12G2 User Manual 5 8 April 5 2013 Notes...

Page 65: ...eiver examines symbols 6 through 15 of the TS1 and TS2 ordered sets for inversion of the PExRP n and PExRN n signals If an inversion is detected then logic for the receiving lane automatically inverts...

Page 66: ...S48T12G2 lane 0 lane 1 a x2 Port without lane reversal PExRP 0 PExRP 1 PExRP 2 PExRP 3 PES48T12G2 lane 1 lane 0 b x2 Port with lane reversal PExRP 0 PExRP 1 PExRP 2 PExRP 3 PES48T12G2 lane 0 a x1 Port...

Page 67: ...S48T12G2 lane 0 lane 1 a x2 Port without lane reversal PExRP 0 PExRP 1 PExRP 2 PExRP 3 PExRP 4 PExRP 5 PExRP 6 PExRP 7 PES48T12G2 lane 1 lane 0 b x2 Port with lane reversal PExRP 0 PExRP 1 PExRP 2 PEx...

Page 68: ...ES48T12G2 lane 3 lane 2 lane 1 lane 0 b x4 Port with lane reversal PExRP 0 PExRP 1 PExRP 2 PExRP 3 PExRP 4 PExRP 5 PExRP 6 PExRP 7 PES48T12G2 lane 0 lane 1 c x2 Port without lane reversal PExRP 0 PExR...

Page 69: ...0 lane 1 lane 2 lane 3 lane 4 lane 5 lane 6 lane 7 a x8 Port without lane reversal PExRP 0 PExRP 1 PExRP 2 PExRP 3 PExRP 4 PExRP 5 PExRP 6 PExRP 7 PES48T12G2 lane 7 lane 6 lane 5 lane 4 lane 3 lane 2...

Page 70: ...ate During this re training the PES48T12G2 port does not re attempt a lane reversed configuration but rather tries to form the link without reversing the lanes As a result a x1 link is formed using la...

Page 71: ...k at the target link speed or at the highest common speed supported by both components of the link whichever is lower In addition the upstream component must initiate a link speed upgrade if it has re...

Page 72: ...SM transi tions through the Detect state Assuming the target link speed is set to 5 0 GT s a PES48T12G2 port initi ates a link speed upgrade in the following cases Link speed upgrade after initial lin...

Page 73: ...d at which each port operates by changing the target link speed via software or EEPROM and forcing link retraining Refer to section Link Retraining on page 6 10 for further details Software Management...

Page 74: ...through the Detect state in its retraining attempt The speed of the link is not necessarily changed as a result of link retraining A link that operates at 5 0 GT s will continue to operate at that spe...

Page 75: ...eam port then the fields in the message are written to the PCI Express Device Capabilities PCIEDCAP register of that port Byte 0 bits 7 0 of the message payload are written to the Captured Slot Power...

Page 76: ...n the port s operational state A port configured in Upstream Switch Port mode initiates L0s entry when all of the conditions listed below are met L0s ASPM is enabled via the port s PCIELCTL register T...

Page 77: ...0s states then the hardware will request a transition to the L1 state from its link partner If the link partner acknowledges the transition then the L1 state is entered Otherwise L0s entry is attempte...

Page 78: ...iolation of the 10 s gap between L1 ASPM entry requests The switch does not respond with an acceptance or rejection Therefore the endpoint keeps waiting for an acceptance or rejection A live lock cond...

Page 79: ...link partner s desired de emphasis and always choose the de emphasis setting in the SDE field of the port s PCIELCTL2 register Crosslink The PES48T12G2 ports support the optional crosslink capability...

Page 80: ...a downstream port with downstream lanes For a port operating in upstream switch port mode There is no higher layer mechanism to place the port in hot reset state Regardless of the physical layer s mo...

Page 81: ...t exits Gen1 Compatibility Mode by clearing the G1CME field in the PHYLCFG0 register and fully retraining the link i e via the FLRET bit the PHYLSTATE0 register When this occurs the training set bits...

Page 82: ...IDT Link Operation PES48T12G2 User Manual 6 18 April 5 2013 Notes...

Page 83: ...is device A SerDes quad is normally associated with its corresponding numbered port i e SerDes quad 0 is associated with port 0 SerDes quad 1 is associated with Port 1 and so on A x4 port is always as...

Page 84: ...emphasis bit in each port s PCI Express Link Control 2 register2 This field is set by hardware or firmware e g EEPROM during boot time and remains unchanged during normal system operation To allow the...

Page 85: ...ested Programming of SerDes Controls The SerDes controls described above may be programmed by accessing IDT proprietary registers within the PES48T12G2 switch The registers may be programmed via any o...

Page 86: ...ted with two transmitter control registers S x TXLCTL0 and S x TXLCTL1 Together these registers allow full programmability of the SerDes trans mitter voltage levels and de emphasis These registers are...

Page 87: ...highlighted Note that in Gen1 mode de emphasis is ideally 3 5dB with 0 5dB error refer to Section 4 3 3 5 of the PCI Express 2 0 Specification All settings listed in the table ensure that the de emph...

Page 88: ...x2 942 3 5 628 0x16 0x2 0x3 0x4 0x2 935 3 5 624 0x15 0x2 0x3 0x4 0x2 928 3 5 620 0x14 0x2 0x3 0x4 0x2 902 3 5 602 0x13 0x2 0x3 0x4 0x2 877 3 5 584 0x12 0x2 0x3 0x4 0x2 851 3 6 566 0x11 0x2 0x3 0x4 0x2...

Page 89: ...0x4 0x0 871 3 6 574 0x18 0x1 0x1 0x4 0x0 854 3 6 562 0x17 0x1 0x1 0x4 0x0 837 3 7 549 0x16 0x1 0x1 0x4 0x0 819 3 7 537 0x15 0x1 0x1 0x4 0x0 802 3 7 525 0x14 0x1 0x1 0x4 0x0 777 3 7 509 0x13 0x1 0x1 0x...

Page 90: ...rs Drive Level De empha sis De empha sized Level TDVL_ FS6DBG2 TX_EQ_ 6DBG2 CDC_ FS6DBG2 FDC_ FS6DBG2 TX_SLEW _G2 903 5 8 461 0x1C 0x1 0x3 0x1 0x0 901 5 8 460 0x1B 0x1 0x3 0x2 0x0 899 5 8 459 0x1A 0x1...

Page 91: ...ontrol the transmit drive swing controls and the data rate of the SerDes The coarse de emphasis controls should generally be set as shown in Tables 7 2 7 3 and 7 4 Note that there are separate coarse...

Page 92: ...ine de emphasis control must be adjusted appropriately to ensure that the de emphasis on the line falls within the range mandated by the PCI Express specification Note It is possible to turn off the d...

Page 93: ...0x7 Programmable Slew Adjustment The transmitter s slew rate is controlled by fields in the S x TXLCTL0 register It is possible to select different settings for Gen1 operation and Gen2 operation The...

Page 94: ...iance state the SerDes transmit level is controlled by the TM field in the associated port s PCIELCTL2 register and the de emphasis setting is controlled by the LTSSM based on the rules described in S...

Page 95: ...omati cally turned off Therefore the Selectable De emphasis SDE and Compliance De emphasis CDE fields in the PCIELCTL2 register have no effect Additionally the Current De emphasis CDE field in the PCI...

Page 96: ...tion circuit has two controls which may be programmed via the SerDes Receiver Equalization Lane Control S x RXEQLCTL register These are Receiver Equalization Zero RXEQZ Increases the high frequency g...

Page 97: ...sociated with the port are turned on Unused lanes are powered down Lanes that form the initial link width i e lanes on which the PHY LTSSM detected the presence of a link partner in the Detect state a...

Page 98: ...IDT SerDes PES48T12G2 User Manual 7 16 April 5 2013 Notes...

Page 99: ...scribed in Table 8 2 The removal of the interrupt condition occurs when unmasked status bit s causing the interrupt are masked or cleared The PES48T12G2 assumes that all generated MSIs target the root...

Page 100: ...our interrupt signals i e A through D at each port An Assert_INTx message is sent to the root by the upstream port when the aggre gated state of the corresponding interrupt in the upstream port transi...

Page 101: ...ACS causes a TLP to be re directed the re direction is implemented such that TLPs received by a port that are ACS re directed follow the ordering rules for more information contact ssdhelp idt com Sp...

Page 102: ...ownstream Port Figure 8 3 shows an example of ACS upstream forwarding at a downstream port As with ACS Peer to Peer forwarding the offending TLP received by the downstream port is re directed towards...

Page 103: ...lock ing 3 Applicable to memory request TLPs received by a downstream port on its ingress link ACS Upstream For warding 2 Applicable to request or completion TLPs received by the downstream port on it...

Page 104: ...port to a downstream port each port performs error checking and handling independently The errors described below are associated with specific actions to log and report the error The terms uncorrecta...

Page 105: ...errors are ignored in cases where the error is associated with a received packet for which the physical layer reports an error This prevents error pollution Error Condition PCIe Base 2 0 Specificatio...

Page 106: ...PCI Express 2 0 specification transaction layer errors are ignored in cases where the error is associated with a received packet for which the physical or data link layers report an error This preven...

Page 107: ...om the link 2 Non advisory cases uncorrectable error processing Advisory cases correctable error pro cessing TLP header logged in AER Affected packet is forwarded across the bridge unless the bridge f...

Page 108: ...P is nullified Flow control pro tocol error 2 6 1 No N A always non advisory Not applicable The PES48T12G2 does not check for any flow control errors Malformed TLP See Tables 8 11 and 8 12 below No N...

Page 109: ...ting the bridge function Reception of a poisoned IO request memory write request or message with data except Vendor Defined messages that targets a switch port s PCI to PCI bridge function 2 7 2 2 Fun...

Page 110: ...ports do not support ACS Source Validation on message requests received by a port with Local Terminate at Receiver and Gath ered and Routed to Root Complex routing type e g INTx PME_TO_Ack Vendor Defi...

Page 111: ...sidered a completer abort error in AER The Signaled Target Abort STAS bit is set in the SECSTS register Non advisory case uncorrectable error pro cessing Advisory case correctable error processing TLP...

Page 112: ...ne ously The prioritization of errors shown in Table 8 14 determines the error that is logged and reported when multiple errors are detected simultaneously for the received TLP Higher priority errors...

Page 113: ...handle per Table 12 9 but do not log UR error and do not generate a completion with UR status Else handle per Table 12 9 Yes Poisoned TLP If ECRC error detected handle per Table 12 9 but do not log P...

Page 114: ...r is blocked by the multicast blocking check the blocking action takes place but a multicast blocking error is not logged Unsupported request errors are only logged and reported when the request TLP h...

Page 115: ...s at the upstream port but which do not target an enabled downstream port device number i e target a PCI to PCI bridge device number that doesn t exist Type 1 requests that route through the PES48T12G...

Page 116: ...wn stream port and the upstream port becomes locked the switch becomes bus locked While a switch is bus locked the following applies It is illegal to read or write any of the PCIe configuration space...

Page 117: ...013 Notes Note that when a TLP received by port is blocked from being forwarded due to a bus locked switch the TLP is delayed until the switch is unlocked If the switch is locked for an extended perio...

Page 118: ...IDT Theory of Operation PES48T12G2 User Manual 8 20 April 5 2013 Notes...

Page 119: ...upstream port serves as the add in card s PCIe inter face In this application the upstream port may be hot plugged into a slot on the main system Finally Figure 9 3 illustrates the use of PES48T12G2...

Page 120: ...t is implemented or on the add in board When located on the add in board state changes are communicated between the hot plug controller asso ciated with the slot and the add in card via hot plug messa...

Page 121: ...re made available to external logic using an external I O expander located on the master SMBus interface The negated value for an unused hot plug I O expander output is the value shown in Table 9 2 Th...

Page 122: ...rted maintains an asserted state for 100 to 150 ms and then transitions back to negated When the Toggle Electromechan ical Interlock Control TEMICTL bit in the HPCFGCTL register is set writing a one t...

Page 123: ...ower Enable Output PxPEP is asserted and then power to the slot is enabled and the corresponding downstream port reset output is negated The time between the assertion of the PxPEP signal and the nega...

Page 124: ...n taken is determined by the MSI Enable EN bit in the MSI Capability MSICAP register and the Interrupt Disable INTXD bit in the PCI Command PCICMD register When the downstream port is in a D3hot state...

Page 125: ...ty associated with the port remains unchanged INTx MSI and PME events from other sources are also unaffected The enhanced hot plug signalling mechanism supported by the PES48T12G2 is graphically illus...

Page 126: ...e a precharge voltage Since no clock is present during physical connection the device will maintain all outputs in a high impedance state even when no clock is present The I O cells meet VI requiremen...

Page 127: ...ated with each Function affects the power state of that Function only When the upstream PCI to PCI bridge Function enters the D3Hot state and the PME Turn Off protocol is completed i e PME_TO_Ack mess...

Page 128: ...rom any event other than the receipt of a TLP are discarded i e no error message is generated All completions that target the bridge are treated as unexpected completions UC Completions flowing in eit...

Page 129: ...witch Port or Downstream Switch Port Mode When a port configured in Upstream Switch Port mode receives a PME_Turn_Off message it broadcasts the PME_Turn_Off message on all active downstream ports The...

Page 130: ...n the PCI Express 2 0 base specification and eight general purpose read write registers The Power Budgeting Capabilities PWRBCAP register contains the PCI Express enhanced capability header for the po...

Page 131: ...marizes the configuration of GPIO pins Configured as an Input When configured as an input in the GPIOCFGx register and as a GPIO function in the GPIOFUNCx register the GPIO pin is sampled and register...

Page 132: ...be determined at any time by reading the corresponding GPIODx register When an alternate function input signal is not enabled on any GPIO or I O expander for hot plug signals the alternate function si...

Page 133: ...nnect to the serial EEPROM and I O expander slaves In the split configuration the master and slave SMBuses operate as two independent buses thus multi master arbitration is not required Master SMBus I...

Page 134: ...ter A blank serial EEPROM contains 0xFF in all data bytes When the PES48T12G2 is configured to initialize from serial EEPROM and the first 256 bytes read from the EEPROM all contain the value 0xFF the...

Page 135: ...or sequential double word initialization sequences this value is always 0x1 The SYSADDR field contains the starting double word system address to be initialized The NUMDW field specifies the number of...

Page 136: ...quence with the checksum field initialized to zero 1 The 1 s complement of this sum is placed in the checksum field The checksum is verified in the following manner An 8 bit counter is cleared and the...

Page 137: ...ccur when accessing the serial EEPROM If an error occurs then it is reported in the SMBus Status SMBUSSTS register Software should check for errors before and after each serial EEPROM access I O Expan...

Page 138: ...iated until serial EEPROM initialization completes it is not possible to toggle a hot plug output through serial EEPROM initialization i e it is not possible to cause a 0 1 0 transition or a 1 0 1 tra...

Page 139: ...to I O expander register 6 Write the configuration value to select inputs outputs in the upper eight I O expander bits i e I O 1 0 through I O 1 7 to I O expander register 7 Read value of I O expander...

Page 140: ...interrupt output that is asserted when an I O expander input pin changes state The open drain I O expander interrupt output of all I O expanders should be tied together on the board and connected to...

Page 141: ...s This includes modifications due to upstream secondary bus resets and hot resets I O expander outputs are not modified when the device transitions from normal operation to a fundamental reset In syst...

Page 142: ...0 6 I P6MRLN Port 6 manually operated retention latch MRL input 7 I O 0 7 I P7MRLN Port 7 manually operated retention latch MRL input 8 I O 1 0 I P8MRLN Port 8 manually operated retention latch MRL i...

Page 143: ...tromechanical interlock output 15 I O 1 7 O P7ILOCKP Port 7 electromechanical interlock output 1 I O x y corresponds to the notation used for PCA9555 port x I O pin y SMBus I O Expander Bit Type Signa...

Page 144: ...utput 9 I O 1 1 O P9LINKUPN Port 9 link up status output 10 I O 1 2 O Unused 11 I O 1 3 O Unused 12 I O 1 4 O P12LINKUPN Port 12 link up status output 13 I O 1 5 O P13LINKUPN Port 13 link up status ou...

Page 145: ...ification for a detailed description of these transactions Byte and Word Write Read Block Write Read Initiation of any SMBus transaction other than those listed above to the slave SMBus interface prod...

Page 146: ...etting both START and END signi fies a single transaction sequence 0 Current transaction is not the last read or write sequence 1 Current transaction is the last read or write sequence 1 START Start o...

Page 147: ...te Count The byte count field is only transmitted for block type SMBus transactions SMBus word and byte accesses do not contain this field The byte count field indicates the number of bytes following...

Page 148: ...set that is not listed or is regarded as a reserve register the RERR and WERR bits will be set after a read or write operation is performed Read Only and Clear Read Error This bit is set if the last C...

Page 149: ...hat specified in the MSMBADDR field in the SMBUSSTS register 2 Reserved Reserved field 3 NAERR RW1C No Acknowledge Error This bit is set if an unexpected NACK is observed during a master SMBus transac...

Page 150: ...r A A CCODE START END S PES48T12G2 Slave SMBus Address Rd DATALM DATALL A A A A A P ADDRU A S PES48T12G2 Slave SMBus Address Wr A N CCODE START END P PES48T12G2 not ready with data S PES48T12G2 Slave...

Page 151: ...ADDRL A CCODE START END ADDRU A DATA A P PEC A ADDRU N A ADDRL CMD status S PES48T12G2 Slave SMBus Address Wr A A CMD read A ADDRL A CCODE START Word S PES48T12G2 Slave SMBus Address Wr A CCODE START...

Page 152: ...IDT SMBus Interfaces PES48T12G2 User Manual 12 20 April 5 2013 Notes...

Page 153: ...gress ports and multi cast egress processing performed at each function These tasks are described in the following sections Multicast TLP Determination The determination of whether or not a TLP is a m...

Page 154: ...register As illustrated in Figure 13 1 multicast TLP group membership is determined by address Associated with each multicast group is an address region Posted memory write and address routed message...

Page 155: ...Determination Once a TLP has been determined to be a multicast TLP and the multicast group ID has been deter mined the following error checks are performed If the multicast TLP fails the source valida...

Page 156: ...g the TLP on the link associated with the switch port corresponding to the PCI to PCI bridge If no function accepts a multicast TLP then the TLP is silently discarded This is not an error Note This se...

Page 157: ...sing If a multicast TLP contains an ECRC and multicast overlay processing is enabled then the following actions are performed The ECRC of the original multicast TLP is checked while simultaneously the...

Page 158: ...IDT Multicast PES48T12G2 User Manual 13 6 April 5 2013 Notes...

Page 159: ...nstream switch port The PCI configuration or extended configuration space address of a PCI to PCI bridge register is equal to the offset address of the register within the global address region The of...

Page 160: ...Word register should be read or written with all the byte enables set Register Side Effects There are software visible configuration registers that have a side effect action when written and this side...

Page 161: ...a and have no other effect The port operating mode e g upstream switch port or downstream switch port determines the pres ence of configuration registers within the PCI to PCI bridge function s config...

Page 162: ...SSVIDCAP 0x0F0 0x0 0x0 PCI Capability Structure Default Value of Next Pointer field NXTPTR Name Offset in Configuration Space US DS Advanced Error Reporting Capability AERCAP 0x100 0x200 0x200 Device...

Page 163: ...Enhanced PCI Express Type 1 Reserved 0x000 0x040 0x0D0 PCI Power Management 64 Dwords Enhanced Capability Device Serial Number Enhanced Capability PCIe Virtual Channel Enhanced Capability Power Budgin...

Page 164: ...Secondary Latency Timer Register 0x01B on page 15 5 0x01C Byte IOBASE IOBASE I O Base Register 0x01C on page 15 5 0x01D Byte IOLIMIT IOLIMIT I O Limit Register 0x01D on page 15 6 0x01E Word SECSTS SEC...

Page 165: ...AP2 PCI Express Slot Capabilities 2 0x074 on page 15 27 N 0x078 Word PCIESCTL2 PCIESCTL2 PCI Express Slot Control 2 0x078 on page 15 27 N 0x07A Word PCIESSTS2 PCIESSTS2 PCI Express Slot Status 2 0x07A...

Page 166: ...0x20C on page 15 43 0x20E Word PVCSTS PVCSTS Port VC Status 0x20E on page 15 43 0x210 DWord VCR0CAP VCR0CAP VC Resource 0 Capability 0x210 on page 15 43 0x214 DWord VCR0CTL VCR0CTL VC Resource 0 Cont...

Page 167: ...H Multicast Enhanced Capability Header 0x330 on page 15 52 0x334 Word MCCAP MCCAP Multicast Capability 0x334 on page 15 52 0x336 Word MCCTL MCCTL Multicast Control 0x336 on page 15 52 0x338 Dword MCBA...

Page 168: ...addresses for proprietary port specific registers are listed in Table 14 5 Offset addresses are with respect to the corresponding PCI to PCI bridge function 0 base address Registers in this address ra...

Page 169: ...SCFG SerDes Configuration 0x510 on page 15 65 0x51C Dword LANESTS0 LANESTS0 Lane Status 0 0x51C on page 15 66 0x520 Dword LANESTS1 LANESTS1 Lane Status 1 0x520 on page 15 66 0x530 Dword PHYLCFG0 PHYLC...

Page 170: ...ress range are referenced as REGNAME where REGNAME represents the register name in Table 14 6 Offset addresses for these regis ters can be found in Table 14 6 and register definitions are provided in...

Page 171: ...9 0 STS Switch Port x Status on page 16 4 0x03C0 DWord SWPORT6CTL SWPORT 13 12 9 0 CTL Switch Port x Control on page 16 3 0x03C4 DWord SWPORT6STS SWPORT 13 12 9 0 STS Switch Port x Status on page 16 4...

Page 172: ...rol on page 16 12 0x0880 DWord S4CTL S 13 12 9 0 CTL SerDes x Control on page 16 5 0x0884 DWord S4TXLCTL0 S 13 12 9 0 TXLCTL0 SerDes x Transmitter Lane Control 0 on page 16 6 0x0888 DWord S4TXLCTL1 S...

Page 173: ...Equalization Lane Control on page 16 12 0x0980 DWord S12CTL S 13 12 9 0 CTL SerDes x Control on page 16 5 0x0984 DWord S12TXLCTL0 S 13 12 9 0 TXLCTL0 SerDes x Transmitter Lane Control 0 on page 16 6...

Page 174: ...CTL SMBUSCTL SMBus Control 0x0ACC on page 16 19 0x0AD0 DWord EEPROMINTF EEPROMINTF Serial EEPROM Interface 0x0AD0 on page 16 19 0x0AD8 DWord IOEXPADDR0 IOEXPADDR0 SMBus I O Expander Address 0 0x0AD8 o...

Page 175: ...OBASE and IOLIMIT 0x0 disable Disable I O space 0x1 enable Enable I O space 1 MAE RW 0x0 Memory Access Enable When this bit is cleared the bridge does not respond to memory and prefetchable memory spa...

Page 176: ...atal and fatal error reporting 9 FB2B RO 0x0 Fast Back to Back Enable Not applicable 10 INTXD RW 0x0 INTx Disable Controls the ability of the PCI to PCI bridge to gen erate an INTx interrupt message W...

Page 177: ...Master Abort Not applicable the bridge function never generates requests on its own behalf 14 SSE RW1C 0x0 Signaled System Error This bit is set when the bridge function sends a ERR_FATAL or ERR_NONFA...

Page 178: ...y software This field is implemented for compatibility with legacy software Bit Field Field Name Type Default Value Description 7 0 PLTIMER RO 0x00 Primary Latency Timer Not applicable Bit Field Field...

Page 179: ...segment to which the secondary interface of the bridge is connected Bit Field Field Name Type Default Value Description 7 0 SUBUSN RW 0x0 Subordinate Bus Number The Subordinate Bus Number register is...

Page 180: ...curs the function receives a Poisoned Completion going Upstream or the function transmits a Poisoned Request Downstream 10 9 DVSEL RO 0x0 Not applicable 11 STAS RW1C 0x0 Signaled Target Abort Status T...

Page 181: ...y interfaces of the bridge This field contains A 31 20 of the highest address with A 19 0 assumed to be 0xF_FFFF that is below the primary interface of the bridge Bit Field Field Name Type Default Val...

Page 182: ...e Memory Address Base Upper This field specifies the upper 32 bits of PMBASE when 64 bit addressing is used When the PMCAP field in the PMBASE register is cleared this field becomes read only with a v...

Page 183: ...Line This register communicates interrupt line routing information Values in this register are programmed by system software and are system architecture specific The bridge does not use the value in...

Page 184: ...Forward upstream ISA I O addresses in the address range defined by the I O base and I O limit registers that are in the first 64 KB of PCI I O address space top 768 bytes of each 1 KB block 3 VGAEN RW...

Page 185: ...ort is connected to a slot This field does not apply to an upstream port and should be set to zero 29 25 IMN RO 0x0 Interrupt Message Number The function is allocated only one MSI Therefore this field...

Page 186: ...field is undefined in PCI Express 2 0 specification 15 RBERR RO 0x1 Role Based Error Reporting This bit is set to indicate that the switch supports error reporting as defined in PCI Express 2 0 spec i...

Page 187: ...size 0x1 s256 256 bytes max payload size 0x2 s512 512 bytes max payload size 0x3 s1024 1024 bytes max payload size 0x4 s2048 2048 bytes max payload size 0x5 s4096 4096 bytes max payload size 0x6 reser...

Page 188: ...f Fatal errors Errors are logged in this registers regardless of whether error reporting is enabled or not 3 URD RW1C 0x0 Unsupported Request Detected This bit indicates the device received an Unsuppo...

Page 189: ...0x3 to indicate that L0s and L1 are supported This field may be overridden to allow user control over the ASPM capabilities of this port L0s and or L1 14 12 L0SEL RWL 0x6 L0s Exit Latency This field...

Page 190: ...is default value 0x0 disabled disabled 0x1 l0s L0s enable entry 0x2 l1 L1 enable entry 0x3 l0sl1 L0s and L1 enable entry Note that L0s enable entry corresponds to the transmitter enter ing L0s the rec...

Page 191: ...reducing the link width The switch ports do not have a hardware autonomous mechanism to change link width except due to link reliability issues Therefore this bit is not applicable and is hardwired to...

Page 192: ...WINIT Slot Clock Configuration When set this bit indicates that the port uses the same physical reference clock used by its link partner i e common clock configuration The initial value of this field...

Page 193: ...is bit is read only and has a value of zero when the SLOT bit in the PCIECAP register is cleared 2 MRLP RWL 0x0 MRL Sensor Present This bit is set when an MRL Sensor is implemented for the port This b...

Page 194: ...ck Present This bit is set if an electro mechanical interlock is implemented on the chassis for this slot This bit is read only and has a value of zero when the SLOT bit in the PCIECAP register is cle...

Page 195: ...ue of the corresponding field in the PCI ESCTLIV register 4 CCIE RW HWINIT Command Complete Interrupt Enable This bit when set enables the generation of a Hot Plug interrupt when a command is com plet...

Page 196: ...CIESCAP register When the corresponding capability is enabled the initial value of this field is equal to the value of the corresponding field in the PCI ESCTLIV register 0x0 on Power on 0x1 off Power...

Page 197: ...the presence of a card in the slot corresponding to the port and reflects the state of the Presence Detect status When the SLOT bit is cleared in the PCIECAP register this bit is hardwired to one in d...

Page 198: ...is read only zero in an upstream port 31 6 Reserved RO 0x0 Reserved field Bit Field Field Name Type Default Value Description 4 0 Reserved RO 0x0 Reserved field 5 ARIFEN RW 0x0 ARI Forwarding Enable...

Page 199: ...link speed for device specific reasons other than to correct unreliable link operation by reducing the link speed Initial transition to the highest supported common link speed is not blocked by this b...

Page 200: ...PHY LTSSM transitions through the states in which it is allowed to modify the transmit margin setting on the line i e Recovery RcvrLock Therefore after modifying this field it is rec ommended that the...

Page 201: ...x0 De emphasis level 6 0 dB 0x1 De emphasis level 3 5 dB The value of this bit in undefined when the link operates at 2 5 GT s 15 1 Reserved RO 0x0 Reserved field Bit Field Field Name Type Default Val...

Page 202: ...ich the port may generate a PME Bits 27 30 and 31 are set to indicate that the P2P bridge within the switch will forward PME messages The switch does not forward PME messages in D3cold This func tiona...

Page 203: ...t never generates a PME this bit will never be set in that port 21 16 Reserved RO 0x0 Reserved field 22 B2B3 RO 0x0 B2 B3 Support Does not apply to PCI Express 23 BPCCE RO 0x0 Bus Power Clock Control...

Page 204: ...ing an MSI produces unde fined results Bit Field Field Name Type Default Value Description 31 0 UADDR RW 0x0 Upper Message Address This field specifies the upper portion of the DWORD address of the MS...

Page 205: ...Value Description 15 0 SSVID RWL 0x0 SubSystem Vendor ID This field identifies the manufacturer of the add in card or subsystem SSVID values are assigned by the PCI SIG to insure uniqueness 31 16 SSI...

Page 206: ...pe Default Value Description 31 0 DATA RW 0x0 Configuration Data A read from this field will return the configura tion space register value pointed to by the ECFGADDR register A write to this field wi...

Page 207: ...tions For this exception case the error is an ACS vio lation and is not logged as a completer abort error 16 UECOMP RW1C 0x0 Sticky Unexpected Completion Status This bit is set when an unex pected com...

Page 208: ...to the root complex This bit does not affect the state of the corresponding bit in the AERUES register 11 6 Reserved RO 0x0 Reserved field 12 POISONED RW 0x0 Sticky Poisoned TLP Mask When this bit is...

Page 209: ...is not updated and an error is not reported to the root complex This bit does not affect the state of the corresponding bit in the AERUES register 19 ECRC RW 0x0 Sticky ECRC Mask When this bit is set...

Page 210: ...AERUES register When the Disable Multicast Error Reporting DMCER bit is set in the Switch Control SWCTL register this field becomes read only with a value of zero 31 24 Reserved RO 0x0 Reserved field...

Page 211: ...a non fatal error 20 UR RW 0x0 Sticky UR Severity This bit controls the severity of the reported error If this bit is set the event is reported as a fatal error When this bit is cleared the event is...

Page 212: ...bit is set when an error that requires packet header logging occurs but the packet header can not be logged by the port s AER Header Log registers AERHL 1 4 DW A packet s header cannot be logged in t...

Page 213: ...When this bit is set the corre sponding bit in the AERCES register is masked When a bit is masked in the AERCES register the corresponding event is not reported to the root complex This bit does not...

Page 214: ...apable of checking ECRC 8 ECRCCE RW 0x0 Sticky ECRC Check Enable When this bit is set ECRC checking is enabled for the Function 9 MHRC RO 0x0 Multiple Header Recording Capable The PES48T12G2 ports do...

Page 215: ...ty ID The value of 0x3 indicates a device serial number capability structure 19 16 CAPVER RO 0x1 Capability Version The value of 0x1 indicates compatibility with version 1 of the specification 31 20 N...

Page 216: ...T RWL 0x0 Extended VC Count A value 0x0 indicates that only the default VC VC0 is implemented 3 Reserved RO 0x0 Reserved field 6 4 LPEVCCNT RWL 0x0 Low Priority Extended VC Count Not applicable only t...

Page 217: ...1 Reserved RO 0x0 Reserved field Bit Field Field Name Type Default Value Description 7 0 PARBC RWL 0x1 Port Arbitration Capability This field indicates the type of port arbitration supported by the V...

Page 218: ...ogic This bit always returns 0 when read 19 17 PARBSEL RW 0x0 Port Arbitration Select This field configures the VC resource to provide a particular port arbitration service The permissible values of t...

Page 219: ...4 port_4 Port 4 0x5 port_5 Port 5 0x6 port_6 Port 6 0x7 port_7 Port 7 0x8 port_8 Port 8 0x9 port_9 Port 9 0xC port_12 Port 12 0xD port_13 Port 13 7 4 PHASE1 RW 0x0 Phase 1 This field contains the port...

Page 220: ...PHASE14 RW 0x0 Phase 14 This field contains the port ID for the corresponding port arbitration period 31 28 PHASE15 RW 0x0 Phase 15 This field contains the port ID for the corresponding port arbitrati...

Page 221: ...esponding port arbitration period 23 20 PHASE29 RW 0x0 Phase 29 This field contains the port ID for the corresponding port arbitration period 27 24 PHASE30 RW 0x0 Phase 30 This field contains the port...

Page 222: ...turns the contents of the corresponding Power Budget ing Data Value PWRBDVx register Otherwise this field contains a value of zero Bit Field Field Name Type Default Value Description 0 SA RWL 0x0 Syst...

Page 223: ...inter The value of 0x0 terminates the list Bit Field Field Name Type Default Value Description 0 V Upstream Port RO Down stream Port RWL Upstream Port 0x0 Downstream Port 0x1 ACS Source Validation If...

Page 224: ...trol Vector register The value of 0x10 indicates that egress control may be done with up to 8 ports The value of this field is undefined if the ACS P2P Egress Control bit in this register is set to 0x...

Page 225: ...RO Downstream Port RW 0x0 ACS Direct Translated P2P Enable When set the port performs ACS Direct Translated Peer to Peer control 15 7 Reserved RO 0x0 Reserved field Bit Field Field Name Type Default...

Page 226: ...upported by the switch partition which is 32 The maximum number of supported groups is 64 and this field may be re programmed during initial switch configuration e g via EEPROM to 0x3F to enable suppo...

Page 227: ...tion i e INDEXPOS are non zero Bit Field Field Name Type Default Value Description 31 0 MCBARH RW 0x0 Multicast BAR High This field specifies the upper 32 bits i e bits 32 through 63 of the multicast...

Page 228: ...t Block All Each bit in this field corresponds to one of the lower 32 multicast groups e g bit 0 corresponds to multicast group 0 bit 1 corresponds to multicast group 1 and so on When a bit is set in...

Page 229: ...t Value Description 31 0 MCBLKUT RW 0x0 Multicast Block Untranslated Each bit in this field corresponds to one of the upper 32 multicast groups e g bit 0 corresponds to multicast group 32 bit 1 corres...

Page 230: ...is to allow the initial value of the corresponding field in the PCIESCTL register to be controlled following a partition fundamental reset A write to this field causes an immediate effect in the corre...

Page 231: ...gister when the corre sponding slot or hot plug capability is enabled A partition reset does not reset slot and hot plug capability bits since they are RWL The intent of this field is to allow the ini...

Page 232: ...rting Enable When this bit is set internal error reporting is enabled and reported through AER Refer to sec tion Internal Errors on page 3 12 for details 31 1 Reserved RO 0x0 Reserved field Bit Field...

Page 233: ...le Link Detected This bit is set when the ULD bit is set in the port s Autonomous Link Reliability Status ALRSTS register 17 RBCTLSBE RW1C 0x0 SWSticky Replay Buffer Control Single Bit Error This bit...

Page 234: ...r to the AER Capability Structure This bit does not affect the state of the corresponding bit in the IERRORSTS regis ter 9 IFBCTLSBE RW 0x0 SWSticky IFB Control Single Bit Error When this bit is set t...

Page 235: ...s set the corresponding error bit in the IERRORSTS register is masked from reporting an internal error to the AER Capability Structure This bit does not affect the state of the corresponding bit in th...

Page 236: ...is cleared and the corresponding status bit is set and unmasked then the error is reported as an correctable internal error 8 IFBDATDBE RW 0x1 SWSticky IFB Data Double Bit Error This bit controls how...

Page 237: ...he corresponding type is reported When this bit is set and the corresponding status bit is set and unmasked then the error is reported as an uncorrectable internal error When this bit is cleared and t...

Page 238: ...a one to this bit sets the corre sponding bit in the IERRORSTS register This bit always returns a value of zero when read 8 IFBDATDBE RW 0x0 IFB Data Double Bit Error Writing a one to this bit sets t...

Page 239: ...31 19 Reserved RO 0x0 Reserved field Bit Field Field Name Type Default Value Description 7 0 RCVD_OVRD RW 0x0 SWSticky Receiver Detect Override Each bit in this register corresponds to a SerDes lane...

Page 240: ...nly be set when the LTSSM is in the L0 Configuration Disabled or Hot Reset states 31 24 Reserved RO 0x0 Reserved field Bit Field Field Name Type Default Value Description 7 0 UND RW1C 0x0 Sticky Recei...

Page 241: ...er a port automatically initiates a speed change to Gen2 speed if Gen2 speed is permissible after initial entry to L0 from Detect 0x0 automatic Automatically initiate speed change to Gen2 speed if per...

Page 242: ...he request The actual time may be calculated by multiplying the value in this field by 4ns For example a setting of 0x947 i e 2375 d corre sponds to a time of 2375 cycles 4ns 9 5us Refer to section 5...

Page 243: ...d When the number of DWords required in completions to service a non posted read request is greater than the value in this field then the completion size estimate considers the number of individual co...

Page 244: ...port Similarly the value of this register must not be programmed to point to the address of the Extended Configuration Address ECF GADDR or Extended Configuration Data registers ECFGDATA in this or a...

Page 245: ...witch Fundamental Reset on page 5 2 The initial value of this bit is that of the RSTHALT signal in the boot configuration vector 3 REGUNLOCK RW 0x0 SWSticky Register Unlock When this bit is set the co...

Page 246: ...nk associated with a downstream switch port regardless of the specified device number 0x3 reserved 18 11 Reserved RO 0x0 Reserved field 19 BDISCARD RW 0x0 SWSticky Discard Vendor Defined Broadcast Mes...

Page 247: ...eserved field Bit Field Field Name Type Default Value Description 15 0 USSBR RW 0x0 SWSticky Side Effect Delay This field specifies the delay in microseconds from when a configuration request that ini...

Page 248: ...place holder for the future 21 20 Reserved RW HWINIT SWSticky This field is unused in the switch and serves as a place holder for the future 31 22 Reserved RO 0x0 Reserved field Bit Field Field Name T...

Page 249: ...t affected by this field i e reading from a SerDes lane control register returns the last value written to that register regardless of the setting of this field Operating on a reserved lane results in...

Page 250: ...the lane s selected by the Lane Select LANESEL 3 0 field in the SerDes Control S x CTL register This value is SWSticky for all lanes i e even those not selected by the LANESEL field in the S x CTL re...

Page 251: ...it in the port s SERDESCFG register is set to 0x1 for both Gen 1 and Gen 2 data rates This field controls the transmit equalization for the lane s selected by the Lane Select LANESEL 3 0 field in the...

Page 252: ...ansmitter uses its maximum slew rate setting 28 27 TX_AMPBOOST RW 0x1 SWSticky Transmit Driver Amplitude Boost This field increases the trans mitter driver s differential swing for the lane s selected...

Page 253: ...in Gen 1 data rate the de emphasis should nominally be set to 3 5dB of the transmit driver voltage level This field has no effect when the port operates in low swing mode i e de emphasis is turned off...

Page 254: ...mmable Voltage Margining and De Empha sis on page 7 3 for further details on programming this field 20 16 TDVL_FS6DBG2 RW 0x13 SWSticky Transmit Driver Voltage Level for Full Swing Mode with 6 0dB De...

Page 255: ...er is set to 0x1 and Gen 1 data rate The value of this field corresponds to the peak to peak differential voltage at the transmitter pins This field controls the voltage level for the lane s selected...

Page 256: ...the S x CTL register 5 3 RXEQB RW 0x7 SWSticky Receive Equalization Boost Reduces the low frequency gain of the equalizer A value of 0x0 results in the largest low frequency gain and smallest amount...

Page 257: ...ured to operate as an alternate function See Chapter 11 for details 0x0 afunc0 Alternate function 0 0x1 afunc1 Alternate function 1 0x2 afunc2 Alternate function 2 0x3 afunc3 Alternate function 3 Bit...

Page 258: ...t Value Description 21 0 GPIOCFG RW 0x0 SWSticky GPIO Configuration Each bit in this field controls the correspond ing GPIO pin When a bit is configured as a general purpose I O pin and the correspond...

Page 259: ...input signals is ignored and the state of the hot plug output signals is negated 9 5 HP1GPIOPRT RW 0x1F SWSticky Hot Plug GPIO 1 Port Map This field selects the PES48T12G2 port whose hot plug signals...

Page 260: ...vert Polarity of PxAIN When this bit is set the polarity of the PxAIN output is inverted in all ports 5 IPXPIN RW 0x0 SWSticky Invert Polarity of PxPIN When this bit is set the polarity of the PxPIN o...

Page 261: ...te of the PxILOCKP output i e the state of the PxILOCKP signal is imply inverted and not pulsed 15 14 RSTMODE RW 0x0 SWSticky Reset Mode This field controls the manner in which port reset out puts are...

Page 262: ...ed to operate in a mode in which serial EEPROM initialization occurs during a Switch Fundamental Reset this bit is set when serial EEPROM initialization completes or when an error is detected 25 NAERR...

Page 263: ...on 17 ICHECKSUM RW 0x0 SWSticky Ignore Checksum Errors When this bit is set serial EEPROM initialization checksum errors are ignored i e the checksum always passes 21 18 Reserved RO 0x0 Reserved field...

Page 264: ...This field contains the SMBus address assigned to I O expander 2 on the master SMBus interface 24 Reserved RO 0x0 Reserved field 31 25 IOE3ADDR RWL 0x0 SWSticky I O Expander 3 Address This field conta...

Page 265: ...25 IOE11ADDR RWL 0x0 SWSticky I O Expander 11 Address This field contains the SMBus address assigned to I O expander 3 on the master SMBus interface Bit Field Field Name Type Default Value Description...

Page 266: ...als are active low 0x1 invert GPEN signals are active high Bit Field Field Name Type Default Value Description 15 0 GPES RO 0x0 General Purpose Event Status Each bit in this field corresponds to a swi...

Page 267: ...system logic utilizes a 16 state TAP controller a six bit instruction register and five dedicated pins to perform a variety of functions The primary use of the JTAG TAP Controller state machine is to...

Page 268: ...G RESET active low Asynchronous reset for JTAG TAP controller internal pull up JTAG_TCK Input JTAG Clock Test logic clock JTAG_TMS and JTAG_TDI are sampled on the rising edge JTAG_TDO is output on the...

Page 269: ...0 I PE02TN 3 0 O C PE02TP 3 0 O PE03RN 3 0 I O PE03RP 3 0 I PE03TN 3 0 O C PE03TP 3 0 O PE04RN 3 0 I O PE04RP 3 0 I PE04TN 3 0 O C PE04TP 3 0 O PE05RN 3 0 I O PE05RP 3 0 I PE05TN 3 0 O C PE05TP 3 0 O...

Page 270: ...CLK I O O C MSMBDAT I O O C SSMBADDR 2 1 I O SSMBCLK I O O C SSMBDAT I O O C General Purpose I O GPIO 8 0 I O O C System Pins CLKMODE 1 0 I O GCLKFSEL I O P01MERGEN I P23MERGEN I P45MERGEN I P67MERGEN...

Page 271: ...currently held in the boundary scan register s output latches is immediately transferred to the corresponding outputs or output enables Therefore the SAMPLE PRELOAD instruction must first be used to l...

Page 272: ...utput cells is shown in Figure 17 4 Figure 17 4 Diagram of Output Cell The output enable cells are also output cells The simplified logic is shown in Figure 17 5 Input Pin shift_dr From previous cell...

Page 273: ...ster allows an instruction to be shifted serially into the device at the rising edge of JTAG_TCK The instruction is then used to select the test to be performed or the test register to be accessed or...

Page 274: ...ut into BYPASS mode Instruction Definition Opcode EXTEST Mandatory instruction allowing the testing of board level interconnec tions Data is typically loaded onto the latched parallel outputs of the b...

Page 275: ...a Device ID register it must also contain a BYPASS register The only difference is that the BYPASS register will not be the default register selected during the TAP controller reset When the IDCODE i...

Page 276: ...not entered the output of the AC pins is not distinguishable from the output of the DC EXTEST instruction RESERVED Reserved instructions implement various test modes used in the device manufacturing...

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