IDT 89HPES48T12G2, User Manual, Page: 65 / 276

Notes
PES48T12G2 User Manual 6 - 1 April 5, 2013
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Chapter 6
Link Operation
Introduction
Link operation in the PES48T12G2 adheres to the PCI Express 2.0 Base Specification, supporting
speeds of 2.5 GT/s and 5.0 GT/s. The PES48T12G2 contains sixteen x4 ports which may be merged in
pairs to form x8 ports. The default link width of each port is x4 and the SerDes lanes are statically assigned
to a port.
Each port supports upstream and downstream link behavior. The behavior is determined dynamically by
the port’s operating state (i.e., upstream switch port, downstream switch port). A full link retrain is defined as
retraining of a link that transitions through the Detect LTSSM
1
state.
Polarity Inversion
Each port of the PES48T12G2 supports automatic polarity inversion as required by the PCIe specifica-
tion. Polarity inversion is a function of the receiver and not the transmitter. The transmitter never inverts its
data. During link training, the receiver examines symbols 6 through 15 of the TS1 and TS2 ordered sets for
inversion of the PExRP[n] and PExRN[n] signals. If an inversion is detected, then logic for the receiving
lane automatically inverts received data. Polarity inversion is a lane and not a link function. Therefore, it is
possible for some lanes of link to be inverted and for others not to be inverted.
Lane Reversal
The PCIe specification describes an optional lane reversal feature. The PES48T12G2 supports the
automatic lane reversal feature outlined in the PCIe specification. The operation of lane reversal is depen-
dent on the maximum link width determined dynamically by the PHY. The maximum link width is the
minimum of:
– The value of the MAXLNKWDTH field in the port’s PCI Express Link Capabilities (PCIELCAP)
register.
– The number of consecutive lanes detected during the Detect state on which valid training sets are
received.
Lane reversal mapping for the various non-trivial maximum link width configurations supported by the
PES48T12G2 is illustrated in Figures 6.1 and 6.5.
1.
The term ‘LTSSM’ refers to a port’s Link Training and Status State Machine in the Physical Layer.