IDT 89HPES48T12G2, User Manual

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IDT PCI to PCI Bridge and Proprietary Port Specific Registers
PES48T12G2 User Manual 15 - 37 April 5, 2013
AERCES - AER Correctable Error Status (0x110)
14 COMPTO RO 0x0 Completion Timeout Severity. A switch port does not initiate non-
posted requests on its own behalf. Therefore, this field is hardwired
to zero.
15 CABORT RO 0x0 Completer Abort Severity. Tthe switch never responds to a non-
posted request with a completer abort, except for ACS violations.
16 UECOMP RW 0x0
Sticky
Unexpected Completion Severity . This bit controls the severity
of the reported error. If this bit is set, the event is reported as a fatal
error. When this bit is cleared, the event is reported as a non-fatal
error.
17 RCVOVR RW 0x1
Sticky
Receiver Overflow Severity. This bit controls the severity of the
reported error. If this bit is set, the event is reported as a fatal error.
When this bit is cleared, the event is reported as a non-fatal error.
18 MALFORMED RW 0x1
Sticky
Malformed TLP Severity. This bit controls the severity of the
reported error. If this bit is set, the event is reported as a fatal error.
When this bit is cleared, the event is reported as a non-fatal error.
19 ECRC RW 0x0
Sticky
ECRC Severity. This bit controls the severity of the reported error.
If this bit is set, the event is reported as a fatal error. When this bit
is cleared, the event is reported as a non-fatal error.
20 UR RW 0x0
Sticky
UR Severity. This bit controls the severity of the reported error. If
this bit is set, the event is reported as a fatal error. When this bit is
cleared, the event is reported as a non-fatal error.
21 ACSV RW 0x0
Sticky
ACS Violation Severity. This bit controls the severity of the
reported error. If this bit is set, the event is reported as a fatal error.
When this bit is cleared, the event is reported as a non-fatal error.
22 UIE RW 0x1
Sticky
Uncorrectable Internal Error Severity. This bit controls the
severity of the reported error. If this bit is set, the event is reported
as a fatal error. When this bit is cleared, the event is reported as a
non-fatal error.
When the Internal Error Reporting Enable (IERROREN) bit is
cleared in the Internal Error Reporting Control (IERRORCTL) reg-
ister, this field becomes read-only with a value of one.
23 MCBLKTLP RW 0x0
Sticky
MC Blocked TLP Severity. This bit controls the severity of the
reported error. If this bit is set, the event is reported as a fatal error.
When this bit is cleared, the event is reported as a non-fatal error.
When the Disable Multicast Error Reporting (DMCER) bit is
cleared in the Switch Control (SWCTL) register, this field becomes
read-only with a value of zero.
31:24 Reserved RO 0x0 Reserved field.
Bit
Field
Field
Name
Type
Default
Value
Description
0 RCVERR RW1C 0x0
Sticky
Receiver Error Status. This bit is set when the physical layer
detects a receiver error.
5:1 Reserved RO 0x0 Reserved field.
Bit
Field
Field
Name
Type
Default
Value
Description