IDT 89HPES48T12G2, User Manual

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IDT SMBus Interfaces
PES48T12G2 User Manual 12 - 5 April 5, 2013
Notes
Programming the Serial EEPROM
The serial EEPROM may be programmed prior to board assembly or in-system via the slave SMBus
interface or a PCIe root. Programming the serial EEPROM via the slave SMBus is described in section
Serial EEPROM Read or Write Operation on page 12-16. A PCIe root may read and write the serial
EEPROM by performing configuration read and write transactions to the Serial EEPROM Interface
(EEPROMINTF) register.
To read a byte from the serial EEPROM, the root should configure the Address (ADDR) field in the
EEPROMINTF register with the byte address of the serial EEPROM location to be read and the Operation
(OP) field to “read.” The Busy (BUSY) bit should then be checked. If the EEPROM is not busy, then the read
operation may be initiated by performing a write to the Data (DATA) field. When the serial EEPROM read
operation completes, the Done (DONE) bit in the EEPROMINTF register is set and the busy bit is cleared.
When this occurs, the DATA field contains the byte data of the value read from the serial EEPROM.
To write a byte to the serial EEPROM, the root should configure the ADDR field with the byte address of
the serial EEPROM location to be written and set the OP field to “write.” If the serial EEPROM is not busy
(i.e., the BUSY bit is cleared), then the write operation may be initiated by writing the value to be written to
the DATA field. When the write operation completes, the DONE bit is set and the busy bit is cleared.
Initiating a serial EEPROM read or write operation when the BUSY bit is set produces undefined results.
SMBus errors may occur when accessing the serial EEPROM. If an error occurs, then it is reported in the
SMBus Status (SMBUSSTS) register. Software should check for errors before and after each serial
EEPROM access.
I/O Expanders
PES48T12G2 utilizes external SMBus/I2C-bus I/O expanders connected to the master SMBus interface
for hot-plug and port status signals. PES48T12G2 is designed to work with Phillips PCA9555 compatible I/
O expanders (i.e., PCA9555, PCA9535, and PCA9539). See the Phillips PCA9555 data sheet for details on
the operation of this device. An external SMBus I/O expander provides 16 bit I/O pins that may be config-
ured as inputs or outputs.
Error Action Taken
Configuration Done Sequence checksum mis-
match with that computed - Set RSTHALT bit in SWCTL register
- ICSERR bit is set in the SMBUSSTS register
- Abort initialization, set DONE bit in the SMBUSSTS register
Invalid configuration block type
(only invalid type is 0x2) - Set RSTHALT bit in SWCTL register
- ICSERR bit is set in the SMBUSSTS register
- Abort initialization, set DONE bit in the SMBUSSTS register
An unexpected NACK is observed during a
master SMBus transaction - Set RSTHALT bit in SWCTL register
- NAERR bit is set in the SMBUSSTS register
- Abort initialization, set DONE bit in the SMBUSSTS register
A misplaced START or STOP condition is
detected by the master SMBus interface - Set RSTHALT bit in SWCTL register
- OTHERERR bit is set in the SMBUSSTS register
- Abort initialization, set DONE bit in the SMBUSSTS register
Serial EEPROM address rollover error
detected - Set RSTHALT bit in SWCTL register
- ROLLOVER bit is set in the SMBUSSTS register
- Abort initialization, set DONE bit in the SMBUSSTS register
Blank serial EEPROM detected - BLANK bit is set in the SMBUSSTS register
- Abort initialization, set DONE bit in the SMBUSSTS register
Table 12.2 Serial EEPROM Initialization Errors