IDT 89HPES34H16, User Manual, Page: 44 / 182

IDT Clocking, Reset, and Initialization Clock Operation
PES34H16 User Manual 3 - 4 October 30, 2008
Notes
Reset
The PES34H16 defines four reset categories: fundamental reset, hot reset, upstream secondary bus
reset, and downstream secondary bus reset.
– A fundamental reset causes all logic in the PES34H16 to be returned to an initial state.
– A hot reset causes all logic in the PES34H16 to be returned to an initial state, but does not cause
the state of register fields denoted as “sticky” to be modified.
– An upstream secondary bus reset causes all devices on the virtual PCI bus to be hot reset except
the upstream port (i.e., upstream PCI to PCI bridge).
– A downstream secondary bus reset causes a hot reset to be propagated on the corresponding
external secondary bus link.
There are two sub-categories of fundamental reset: cold reset and warm reset. A cold reset occurs
following a device being powered on and assertion of PERSTN. A warm reset is a fundamental reset that
occurs without removal of power.
P23MERGEN N Port 2 and 3 Merge. When this pin is asserted, port 3 is merged with
port 2 to form a single x8 port. The SerDes lanes associated with
port 3 become lanes 4 through 7 of port 2.
P45MERGEN N Port 4 and 5 Merge. When this pin is asserted, port 5 is merged with
port 4 to form a single x8 port. The SerDes lanes associated with
port 5 become lanes 4 through 7 of port 4.
PERSTN I Fundamental Reset. Assertion of this signal resets all logic inside
the PES34H16 and initiates a PCI Express fundamental reset.
RSTHALT Y Reset Halt. When this signal is asserted during a PCI Express fun-
damental reset, the PES34H16 executes the reset procedure and
remains in a reset state with the Master and Slave SMBuses active.
This allows software to read and write registers internal to the device
before normal device operation begins. The device exits the reset
state when the RSTHALT bit is cleared in the SWCTL register
through the SMBus.
The value may be overridden by modifying the RSTHALT bit in the
SWCTL register.
SWMODE[3:0] N Switch Mode. These configuration pins determine the PES34H16
switch operating mode. These pins should be static and not change
following the negation of PERSTN.
0x0 - Normal switch mode
0x1 - Normal switch mode with Serial EEPROM initialization
0x2 through 0x7 - Reserved
0x8 - Normal switch mode with upstream port failover (port 0
selected as the upstream port)
0x9 - Normal switch mode with upstream port failover (port 2
selected as the upstream port)
0xA - Normal switch mode with Serial EEPROM initialization and
upstream port failover (port 0 selected as the upstream port)
0xB - Normal switch mode with Serial EEPROM initialization and
upstream port failover (port 2 selected as the upstream port)
0xC through 0xF - Reserved
Signal
May Be
Overridden
Description
Table 3.2 Boot Configuration Vector Signals