IDT 89HPES34H16, User Manual, Page: 30 / 182

IDT PES34H16 Device Overview
PES34H16 User Manual 1 - 12 October 30, 2008
Notes
Pin Characteristics
Note: Some input pads of the PES34H16 do not contain internal pull-ups or pull-downs. Unused
inputs should be tied off to appropriate levels. This is especially critical for unused control signal
inputs which, if left floating, could adversely affect operation. Also, any input pin left floating can
cause a slight increase in power consumption.
Signal Type Name/Description
V
DD
CORE I Core VDD. Power supply for core logic.
V
DD
I/O I I/O VDD. LVTTL I/O buffer power supply.
V
DD
PE I PCI Express Digital Power. PCI Express digital power used by the digital
power of the SerDes.
V
DD
APE I PCI Express Analog Power. PCI Express analog power used by the PLL
and bias generator.
V
SS
I Ground.
V
TT
PE PCI Express Serial Data Transmit Termination Voltage. This pin allows
the driver termination voltage to be set, enabling the system designer to con-
trol the Common Mode Voltage and output voltage swing of the correspond-
ing PCI Serial Data Transmit differential pair.
Table 1.8 Power and Ground Pins
Function Pin Name Type Buffer
I/O
Type
Internal
Resistor
Notes
PCI Express Interface PE0RN[3:0] I CML Serial Link
PE0RP[3:0] I
PE0TN[3:0] O
PE0TP[3:0] O
PE1RN[3:0] I
PE1RP[3:0] I
PE1TN[3:0] O
PE1TP[3:0] O
PE2RN[3:0] I
PE2RP[3:0] I
PE2TN[3:0] O
PE2TP[3:0] O
PE3RN[3:0] I
PE3RP[3:0] I
PE3TN[3:0] O
PE3TP[3:0] O
PE4RN[3:0] I
PE4RP[3:0] I
Table 1.9 Pin Characteristics (Part 1 of 3)