IDT 89HPES24N3A, User Manual

Page: 22 / 168

IDT PES24N3A Device Overview
PES24N3A User Manual 1 - 4 April 10, 2008
Logic Diagram
Figure 1.3 PES24N3A Logic Diagram
Note: In the PES24N3A, the two downstream ports are labeled port 2 and port 4.
Reference
Clocks
PEREFCLKP
PEREFCLKN
JTAG_TCK
GPIO[7:0]
8
General Purpose
I/O
V
DD
CORE
V
DD
IO
V
DD
PE
V
DD
APE
Power/Ground
MSMBADDR[4:1]
MSMBCLK
MSMBDAT
4
SSMBADDR[5,3:1]
SSMBCLK
SSMBDAT
4
Master
SMBus Interface
Slave
SMBus Interface
CCLKUS
RSTHALT
System
Functions
JTAG_TDI
JTAG_TDO
JTAG_TMS
JTAG_TRST_N
JTAG
V
SS
SWMODE[3:0]
4
2
2
CCLKDS
PERSTN
REFCLKM
MSMBSMODE
V
TT
PE
PE0RP[0]
PE0RN[0]
PE0RP[7]
PE0RN[7]
PCI Express
Switch
SerDes Input
PE0TP[0]
PE0TN[0]
PE0TP[7]
PE0TN[7]
PCI Express
Switch
SerDes Output
...
Port 0
Port 0
...
PE2RP[0]
PE2RN[0]
PE2RP[7]
PE2RN[7]
PCI Express
Switch
SerDes Input
PE2TP[0]
PE2TN[0]
PE2TP[7]
PE2TN[7]
PCI Express
Switch
SerDes Output
...
Port 2
Port 2
...
PE4RP[0]
PE4RN[0]
PE4RP[7]
PE4RN[7]
PCI Express
Switch
SerDes Input
PE4TP[0]
PE4TN[0]
PE4TP[7]
PE4TN[7]
PCI Express
Switch
SerDes Output
...
Port 4
Port 4
...
PES24N3A
SSMBADDR[5,3:1]
SSMBCLK
SSMBDAT
4
Slave
SMBus Interface