IDT 89HPES24N3A, User Manual

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Notes
PES24N3A User Manual 1 - 1 April 10, 2008
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Chapter 1
PES24N3A Device Overview
Introduction
The 89HPES24N3A is a member of the IDT PRECISE™ family of PCI Express® switching solutions.
The PES24N3A is a 24-lane, 3-port peripheral chip that performs PCI Express packet switching with a
feature set optimized for high performance applications such as servers, storage, and communications/
networking. It provides connectivity and switching functions between a PCI Express upstream port and two
downstream ports and supports switching between downstream ports
Utilizing standard PCI Express interconnect, the PES24N3A provides the most efficient I/O connectivity
solution for applications requiring high throughput, low latency, and simple board layout with a minimum
number of board layers. It provides connectivity for up to 3 ports across 24 integrated serial lanes. Each
lane provides 2.5 Gbps of bandwidth in both directions and is fully compliant with PCI Express Base speci-
fication revision 1.1.
The PES24N3A is based on a flexible and efficient layered architecture. The PCI Express layers consist
of SerDes, Physical, Data Link and Transaction layers. The PES24N3A can operate either as a store and
forward switch or a cut-through switch and is designed to switch memory and I/O transactions. It supports
eight Traffic Classes (TCs) and one Virtual Channel (VC) with sophisticated resource management to
enable efficient switching and I/O connectivity.
List of Features
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High Performance PCI Express Switch
– Twenty-four 2.5 Gbps PCI Express lanes
– Three switch ports
– Upstream port configurable up to x8
– Downstream ports configurable up to x8
– Low-latency cut-through switch architecture
– Support for Max Payload Size up to 2048 bytes
– One virtual channel
– Eight traffic classes
– PCI Express Base Specification Revision 1.1 compliant
‹
Flexible Architecture with Numerous Configuration Options
– Automatic per port link width negotiation to x8, x4, x2 or x1
– Automatic lane reversal on all ports
– Automatic polarity inversion on all lanes
– Ability to load device configuration from serial EEPROM
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Legacy Support
– PCI compatible INTx emulation
– Bus locking
‹
Highly Integrated Solution
– Requires no external components
– Incorporates on-chip internal memory for packet buffering and queueing
– Integrates twenty-four 2.5 Gbps embedded SerDes with 8B/10B encoder/decoder (no separate
transceivers needed)