IDT 89HPES24N3A, User Manual

Page: 155 / 168

IDT Configuration Registers
PES24N3A User Manual 9 - 61 April 10, 2008
Notes
SWTSCNTCTL - Switch Time-Stamp Counter Control (0x4A8)
Internal Switch Error Control and Status Registers
SWPECTL - Switch Parity Error Control (0x740)
SWPESTS - Switch Parity Error Status (0x744)
Bit
Field
Field
Name
Type
Default
Value
Description
31:0 PRESETVAL RW 0x0 Time-Stamp Preset Value. A write to this register will cause
bits 34 through three of the time-stamp counter associated
with all ports to take on the value written and bits two
through zero to be set to zero.
Bit
Field
Field
Name
Type
Default
Value
Description
0 DEEPC RW 0x0
Sticky
Disable End-to-End Parity Checking. When this bit is set,
end-to-end parity is not checked by the port and errors are
never generated. End-to-end parity is always computed for
data sent by the port to the switch core and cannot be dis-
abled.
1 GBEEP RW 0x0
Sticky
Generate Bad End-to-End Parity. When this bit is set, bad
parity is generated for all double words in TLPs emitted to
the switch core from this port (i.e., those received on the
ingress port or generated by the port) whose TLP header
length field (i.e., bits seven through zero of byte zero of the
TLP header) match the value in the Error Match Length
(Length) field in this register
7:2 Reserved RO 0x0 Reserved field.
15:8 LENGTH RW 0x0
Sticky
Error Match Length. When the GBEEP bit is set, bad parity
is generated for all double words in TLPs emitted to the
switch core from this port (i.e., those received on the ingress
port or generated by the stack) whose TLP header length
field (i.e., bits seven through zero of byte zero of the TLP
header) matches the value in this field.
31:16 Reserved RO 0x0 Reserved field.
Bit
Field
Field
Name
Type
Default
Value
Description
0 EEPE RW1C 0x0 End-to-End Parity Error. This bit is set when an end-to-end
parity error is detected at the port.
31:1 Reserved RO 0x0 Reserved field.