IDT 89HPES16T4G2, Preliminary User'S Manual

Page: 132 / 149

IDT Configuration Registers
PES16T4G2 User Manual 8 - 54 January 28, 2013
Notes
SWCTL - Switch Control (0x404)
31:10 Reserved RO 0x0 Reserved field.
Bit
Field
Field
Name
Type Default
Value
Description
0 FRST RW 0x0 Fundamental Reset. Writing a one to this bit initiates a Funda-
mental Reset. Writing a zero has no effect. This field always
returns a value of zero when read.
Writing of a one to this bit always results in the action specified by
this bit to take effect after 1ms. Whitney always returns a comple-
tion to the requester before the effect of this bit is applied.
See section Fundamental Reset on page 2-3 for the behavior of
this bit.
1 HRST RW 0x0 Hot Reset. Writing a one to this bit initiates a hot reset. Addition-
ally, the upstream port’s PHY initiates a full link retrain.
Writing a zero has no effect. This field always returns a value of
zero when read.
Writing of a one to this bit always results in the action specified by
this bit to take effect after 1ms. Whitney always returns a comple-
tion to the requester before the effect of this bit is applied.
See section Hot Reset on page 2-5 for the behavior of this bit.
2 RSTHALT RW HWINIT
Sticky
Reset Halt. When this bit is set, all of the switch logic except the
SMBus interface remains in a reset state. In this state, registers in
the device may be initialized by the slave SMBus interface. When
this bit is cleared, normal operation ensues.
Setting or clearing this bit has no effect following a reset operation.
This bit may be set by asserting the RSTHALT signal during a
reset operation or through initialization by the serial EEPROM.
3 REGUN-
LOCK
RW 0x0
Sticky
Register Unlock. When this bit is set, the contents of registers and
fields of type Read and Write when Unlocked (RWL) are modified
when written to. When this bit is cleared, all registers and fields
denoted as RWL become read-only.
While the initial value of this field is cleared, it is set during a reset
operation, thus allowing serial EEPROM initialization to modify the
contents of RWL fields.
4 PWRB-
DVUL
RWL 0x0
Sticky
Power Budgeting Data Value Unlock. When this bit is set, the
Power Budgeting Data Value [7:0] (PWRBDV[7:0]) registers in all
ports may be read and written. When this bit is cleared, then the
PWRBDV registers in all ports are read-only.
5 DLDHRST RW 0x0
Sticky
Disable Link Down Hot Reset. When this bit is set, hot resets due
to the data link layer of the upstream port transitioning to the
DL_Down state are disabled.
All other hot reset conditions are unaffected by this bit.
6 DHRSTSEI RW 0x0
Sticky
Disable Hot Reset Serial EEPROM Initialization. When this bit is
set, step 6 “serial EEPROM initialization” is skipped in the hot reset
sequence described in section Hot Reset on page 2-5 regardless
of the selected switch operating mode.
31:7 Reserved RO 0x0 Reserved field.
Bit
Field
Field
Name
Type Default
Value
Description