IDT 89HPES16NT2, User Manual

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IDT Link Operation
PES16NT2 User Manual 3 - 4 April 15, 2008
Notes
Figure 3.3 Lane Reversal for Maximum Link Width of x2
When link training occurs, the corresponding lane reversal bits in the PA_SWCTL register are examined.
If a bit is set, then the lanes associated with that link are reversed. This mechanism may be used to
configure lane reversal via the serial EEPROM, slave SMBus, or root.
Link Retraining
Link retraining should not cause either a downstream component or an upstream component to reset or
revert to default values.
Link Down
When a link goes down, all TLPs received by the port and queued in the switch are discarded and all
TLPs received by other ports and destined to the port whose link is down are treated as Unsupported
Requests (UR). While a link is down, it is possible to perform configuration read and write operations to the
PCI-PCI bridge associated with the link. However, it is possible to lose configuration read or write comple-
tions when TLPs queued in the switch are discarded.
1
If this occurs, the root’s completion timer associated
with the transaction(s) will time-out and the transaction will be retired. When a link comes up, flow control
credits for the configured size of the IFB FIFOs are advertised.
Slot Power Limit Support
The Set_Slot_Power_Limit message is used to convey a slot power limit value from the downstream
switch port (port C) to the upstream port of a connected device or switch. A Set_Slot_Power_Limit message
is set by downstream switch ports when either of the following events occurs:
– A configuration write is performed to the corresponding PCIESCAP register when the link associ-
ated with the downstream port is up.
– A link associated with the downstream port transitions from a non-operational state to an opera-
tional (i.e., up) state.
1.
In the case of a configuration write that causes link retraining or a secondary bus reset, a completion corre-
sponding to the configuration write is always returned and never lost.
PExRP[0]
PExRP[1]
PExRP[2]
PExRP[3]
PExRP[4]
PExRP[5]
PExRP[6]
PExRP[7]
PES16NT2
lane 0
lane 1
(a) x2 Port with PExLREV negated
PExRP[0]
PExRP[1]
PExRP[2]
PExRP[3]
PExRP[4]
PExRP[5]
PExRP[6]
PExRP[7]
PES16NT2
lane 1
lane 0
(b) x2 Port with PExLREV asserted
PExRP[0]
PExRP[1]
PExRP[2]
PExRP[3]
PExRP[4]
PExRP[5]
PExRP[6]
PExRP[7]
PES16NT2
lane 0
(c) x1 Port with PExLREV negated
PExRP[0]
PExRP[1]
PExRP[2]
PExRP[3]
PExRP[4]
PExRP[5]
PExRP[6]
PExRP[7]
PES16NT2
lane 0
(d) x1 Port with PExLREV asserted