IDT Non-Transparent Mode Operation
PES16NT2 User Manual
10 - 108
April 15, 2008
Notes
PCEE_PCICMD - PCI Command (0x004)
Bit
Field
Field
Name
Type
Default
Value
Description
0
IOAE
RW
0x0
I/O Access Enable.
When this bit is cleared, the non-
transparent bridge does not respond to I/O access.
0x0 -(disable) Disable I/O space.
0x1 - (enable) Enable I/O space.
1
MAE
RW
0x0
Memory Access Enable.
When this bit is cleared, the non-
transparent bridge does not respond to memory space
access.
0x0 -(disable) Disable memory space.
0x1 - (enable) Enable memory space.
2
BME
RW
0x0
Bus Master Enable.
When this bit is cleared the non-
transparent bridge does not issue requests (e.g., memory,
I/O and MSIs since they are in-band writes) on behalf of
devices on the other side of the bridge and responds to
non-posted transactions with a Unsupported Request (UR)
completion. This bit does not affect completions in either
direction or the forwarding of non-memory or I/O requests.
0x0 - (disable) Disable request forwarding.
0x1 - (enable) Enable request forwarding.
3
SSE
RO
0x0
Special Cycle Enable.
Not applicable.
4
MWI
RO
0x0
Memory Write Invalidate.
Not applicable.
5
VGAS
RO
0x0
VGA Palette Snoop
. Not applicable.
6
PERRE
RW
0x0
Parity Error Enable.
The Master Data Parity Error bit is
set in the PCI Status register if this bit is set and the non-
transparent bridge receives a poisoned completion or gen-
erates a poisoned write. If this bit is set, then the Master
Data Parity Error bit in the PCI Status register is never set.
0x0 - (disable) Disable Master Parity Error bit reporting.
0x1 - (enable) Enable Master Parity Error bit reporting.
7
ADSTEP
RO
0x0
Address Data Stepping.
Not applicable.
8
SERRE
RW
0x0
SERR Enable.
Non-fatal and fatal errors detected by the
bridge are reported to the Root Complex.
0x0 - (disable) Disable non-fatal and fatal error reporting.
0x1 - (enable) Enable non-fatal and fatal error reporting.
9
FB2B
RO
0x0
Fast Back-to-Back Enable.
Not applicable.
10
INTXD
RW
0x0
INTx Disable.
This bit disables the bridges ability to gener-
ate INTx interrupts. This bit only affects legacy INTx inter-
rupts generated by the bridge and does not affect MSIs
0x0 - (enable) Enable ability to generate INTx interrupt
messages.
0x1 - (disable) Disable ability to generate INTx interrupt
messages.
This bit has no effect on the external side of the non-trans-
parent bridge, as the external side of the non-transparent
bridge never generates INTx interrupts.
15:11
Reserved
RO
0x0
Reserved field.
Summary of Contents for 89HPES16NT2
Page 14: ...DT List of Figures PES16NT2 User Manual viii April 15 2008 Notes...
Page 20: ...IDT Register List PES16NT2 User Manual xiv April 15 2008 Notes...
Page 32: ...IDT PES16NT2 Device Overview PES16NT2 User Manual 1 12 April 15 2008 Notes...
Page 50: ...IDT Link Operation PES16NT2 User Manual 3 6 April 15 2008 Notes...
Page 62: ...IDT Power Management PES16NT2 User Manual 5 4 April 15 2008 Notes...
Page 78: ...IDT SMBus Interfaces PES16NT2 User Manual 6 16 April 15 2008 Notes...
Page 83: ...IDT NTB Upstream Port Failover PES16NT2 User Manual 7 5 April 15 2008 Notes...
Page 84: ...IDT NTB Upstream Port Failover PES16NT2 User Manual 7 6 April 15 2008 Notes...
Page 130: ...IDT Transparent Mode Operation PES16NT2 User Manual 9 44 April 15 2008 Notes...
Page 284: ...IDT Non Transparent Mode Operation PES16NT2 User Manual 10 154 April 15 2008 Notes...