IDT 89HPES16NT2, User Manual

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IDT Transparent Mode Operation
PES16NT2 User Manual 9 - 30 April 15, 2008
Notes
Switch Control and Status Registers
PA_SWSTS Switch Status (0x0A0)
Bit
Field
Field
Name
Type
Default
Value
Description
3:0 SWMODE RO HWINIT Switch Mode. The value of this field encodes the switch
mode sampled on the Switch Mode (SWMODE[3:0]) sig-
nals when exiting reset.
0x0 - Transparent mode
0x1 -Transparent mode with serial EEPROM initialization
0x2 - (ntb) Non-transparent mode
0x3 - (ntbinit) Non-transparent mode with serial EEPROM
initialization
0x4 - (ntbfailover) Non-transparent failover mode
0x5 - ntbfailoverinit) Non-transparent failover mode with
serial EEPROM initialization
0x6 through 0xF - Reserved
4 CCLKDS RO HWINIT Common Clock Downstream. This bit reflects the value
of the CCLKDS signal sampled during the fundamental
reset.
5 CCLKUS RO HWINIT Common Clock Upstream. This bit reflects the value of
the CCLKUS signal sampled during the fundamental reset.
6 MSMBSMODE RO HWINIT Master SMBus Slow Mode. This bit reflects the value of
the MSMBSMODE signal sampled during the fundamental
reset.
7 PALREV RO HWINIT PCI Express Port A Lane Reverse. This bit reflects the
value of the PALREV signal sampled during the fundamen-
tal reset.
8 Reserved RO 0x0 Reserved field.
9 PCLREV RO HWINIT PCI Express Port C Lane Reverse. This bit reflects the
value of the PCLREV signal sampled during the fundamen-
tal reset.
10 REFCLKM RO HWINIT PCI Express Reference Clock Mode Select. This bit
reflects the value of the REFCLKM signal sampled during
the fundamental reset.
11 RSTHALT RO HWINIT Reset Halt. This bit reflects the value of the RSTHALT sig-
nal sampled during the fundamental reset.
12 Reserved RO 0x0 Reserved field.
16:13 MARKER RW 0x0
Sticky
Marker. This field is preserved across a hot reset and is
available for general software use.
A hot reset does not result in modification of this field.
19:17 Reserved RO 0x0 Reserved field.
20 INTA RO 0x0 INTA Aggregated State. Aggregated switch state for
INTA.
0x0 - (negated) INTA negated
0x1 - (asserted) INTA asserted