IDT 89HPES16NT2, User Manual

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IDT Transparent Mode Operation
PES16NT2 User Manual 9 - 22 April 15, 2008
Notes
PA_PCIELCAP - PCI Express Link Capabilities (0x04C)
4 AUXPD RO 0x0 Aux Power Detected . Devices that require AUX power,
set this bit when AUX power is detected.This device does
not require AUX power, hence the value is hardwired to
zero.
5 TP RO 0x0 Transactions Pending. The transparent bridge does not
issue Non-Posted Requests on its own behalf. Therefore,
this field is hardwired to zero.
15:6 Reserved RO 0x0 Reserved field.
Bit
Field
Field
Name
Type
Default
Value
Description
3:0 MAXLNKSPD RO 0x1 Maximum Link Speed . This field is hardwired to 0x1 to
indicate 2.5 Gbps.
9:4 MAXLNKWDTH RWL 0x8 Maximum Link Width . This field indicates the maximum
link width of the given PCI Express link. This field may be
overridden to allow the link width to be forced to a smaller
value. Setting this field to a invalid or reserved value results
in x1 being used.
1 - (x1) x1 link width
2 - (x2) x2 link width
4 - (x4) x4 link width
8 - (x8) x8 link width
others - reserved
11:10 ASPMS RO 0x3 Active State Power Management (ASPM) Support . This
field is hardwired to 0x3 to indicate L0s and L1 Support.
14:12 L0SEL RWL see text L0s Exit Latency . This field indicates the L0s exit latency
for the given PCI Express link. This field depends on
whether a common or separate reference clock is used.
When separate clocks are used, 1 µs to 2 µs is reported
with a read-only value of 0x5.
When a common clock is used, 256 ns to 512 ns is
reported with a read-only value of 0x3
17:15 L1EL RWL 0x2 L1 Exit Latency . This field indicates the L1 exit latency for
the given PCI Express link. Transitioning from L1 to L0
always requires 2.3 µs. Therefore, a value 2 µs to less
than 4 µs is reported with a default value of 0x2.
23:18 Reserved RO 0x0 Reserved field.
31:24 PORTNUM RO Port A - 0x0
Port C - 0x2 Port Number . This field indicates the PCI express port
number.
Bit
Field
Field
Name
Type
Default
Value
Description