IDT 89HPES12T3G2, Preliminary User'S Manual

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IDT Power Management
PES12T3G2 User Manual 6 - 3 January 28, 2013
Notes
The PME_Turn_Off / PME_TO_Ack protocol may be initiated by the root when the switch is in any
power management state.
When the PES12T3G2 receives a PME_Turn_Off message it broadcasts the PME_Turn_Off message
on all active downstream ports. The PES12T3G2 transmits a PME_TO_Ack message on its upstream port
and transitions its link state to L2/L3 Ready after it has received a PME_TO_Ack message on each of its
active downstream ports. This process is called PME_TO_Ack aggregation.
The aggregation of PME_TO_Ack messages on downstream ports is abandoned by the PES12T3G2
when it receives a TLP on its upstream port after it has received a PME_Turn_Off message on that port but
before it has responded with a PME_TO_Ack message. Once a PME_TO_Ack message has been sched-
uled for transmission on the upstream port and the PME_TO_Ack aggregation process has completed,
received TLPs at that point may be discarded.
If the TLP that causes PME_TO_Ack aggregation to be abandoned targets the PES12T3G2, then the
PES12T3G2 responds to the TLP normally. If the TLP that causes aggregation to be abandoned targets a
downstream port and the port is in L0, then the TLP is transmitted on the downstream port. If the down-
stream port is not in L0 (i.e., it is in L2/L3 Ready), then the switch transitions the link to Detect and then to
L0. Once the link is reaches L0, the TLP is transmitted on the downstream port.
When PME_TO_Ack aggregation is abandoned, the PES12T3G2 makes no attempt to abandon the
PME_Turn_Off and PME_TO_Ack protocol on downstream ports. Devices downstream of the PES12T3G2
are allowed to respond with a PME_TO_Ack and transition to L2/L3 Ready. When a TLP is received that
targets the downstream port, then the switch transitions the link to Detect and then to L0. Once the link
reaches L0, the TLP is transmitted on the downstream port.
In order to avoid deadlock, a downstream port that does not receive a PME_TO_Ack message in the
time-out period specified in the PME_TO_Ack Time-Out (PMETOATO) field in its corresponding
PME_TO_Ack Timer (PMETOATIMER) register, declares a time-out, transitions its link to L2/L3 Ready and
signals to the upstream port that a PME_TO_Ack message has been received. If instead of being transi-
tioned to the D3
cold
state, the PES12T3G2 is transitioned to the D0
uninitialized
state, then the PES12T3G2
resumes generation of PM_PME messages.
Power Budgeting Capability
The PES12T3G2 contains the mechanisms necessary to implement the PCI-Express power budgeting
enhanced capability. However, by default, these mechanisms are not enabled. To enable the power
budgeting capability, registers in this capability should be initialized and the Next Pointer (NXTPTR) field in
one of the other enhanced capabilities should be initialized to point to the power budgeting capability. The
Next Pointer (NXTPTR) of the power budgeting capability should be adjusted if necessary.
The power budgeting capability consists of the four power budgeting capability registers defined in the
PCIe 2.0 base specification and eight general purpose read-write registers. See Power Budgeting
Enhanced Capability on page 8-52 for a description of these registers.
The Power Budgeting Capabilities (PWRBCAP) register contains the PCI-Express enhanced capability
header for the power budgeting capability. By default, this register has an initial read-only value of zero. To
enable the power budgeting capability, this register should be initialized via the serial EEPROM. The Power
Budgeting Data Value [0..7] (PWRBDV[0..7) registers are used to hold the power budgeting information for
that port in a particular operating condition.
The PWRBDV registers may be read and written when the Power Budgeting Data Value Unlock
(PWRBDVUL) bit is set in the Switch Control (SWCTL) register. When the PWRBDVUL bit is cleared, these
registers are read-only and writes to these registers are ignored. To enable the power budgeting capability,
the PWRBDV registers should be initialized with power budgeting information via the serial EEPROM.