IDT 89HPES12T3G2, Preliminary User'S Manual

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IDT Link Operation
PES12T3G2 User Manual 3 - 6 January 28, 2013
Notes
Software can verify the link speed by reading the Current Link Speed (CLS) field of the port’s Link Status
Register (PCIELSTS). Note that to force link speed to a value other than the default value, the TLS field
could be configured through Serial EEPROM initialization and full link retraining forced. Finally, note that the
Hardware Autonomous Speed Disable (HASD) bit has no effect on the PES12T3G2 ports and is hardwired
to 0x0.
Link Retraining
Per the PCIe 2.0 specification, link retraining can be done autonomously in response to link problems
(i.e., repeated TLP replay attempts), or as a result of software setting the link retrain (LRET) bit in the PCI
Express Link Control (PCIELCTL) register.
Writing a one to the Link Retrain (LRET) bit in a upstream port’s PCI Express Link Control (PCIELCTL)
register when the REGUNLOCK bit is set in the SWCTL register forces the upstream PCIe link to retrain.
When this occurs the LTSSM transitions directly to the Recovery state.
Writing a one to the Link Retrain (LRET) bit in a downstream port’s PCI Express Link Control
(PCIELCTL) register regardless of the REGUNLOCK bit state in the SWCTL register forces the upstream
PCIe link to retrain. When this occurs the LTSSM transitions directly to the Recovery state.
Writing a one to the Full Link Retrain (FLRET) bit in the Phy Link State 0 (PHYLSTATE0) register of any
port forces that port’s PCIe link to retrain. When this occurs the LTSSM transitions directly to the Detect
state.
When link retraining results in the speed of the link being downgraded from 5.0 Gbps to 2.5 Gbps, the
Link Bandwidth Management Status (LBWSTS) bit is set in the PCI Express Link Status (PCIELSTS)
register (for downstream ports only). Additionally, the PHY LTSSM remains at the downgraded speed until
the link partner requests a link speed upgrade, software sets the LRET bit in the PCIELCTL register, or the
link is fully retrained via the FLRET bit in the PHYLSTATE0 register.
When a link goes down, all TLPs received by that port and queued in the switch are discarded and all
TLPs received by other ports and destined to the port whose link is down are treated as Unsupported
Requests (UR). While a downstream link is down, it is possible to perform configuration read and write
operations to the PCI-PCI bridge associated with that link. When a link comes up, flow control credits for the
configured size of the IFB queues are advertised.
A link down condition on a downstream port’s link may cause the Surprise Down Error Status
(SDOENERR) bit to be set in the port’s AER Uncorrectable Error Status (AERUES) register. The conditions
under which surprise down is reported are described in Section 3.2.1 of the PCIe 2.0 Specification.
Slot Power Limit Support
The Set_Slot_Power_Limit message is used to convey a slot power limit value from a downstream
switch port or root port to the upstream port of a connected device or switch.
Upstream Port
When a Set_Slot_Power_Limit message is received by the upstream switch port, then the fields in the
message are written to the PCI Express Device Capabilities (PCIEDCAP) register of that port.
– Byte 0 bits 7:0 of the message payload are written to the Captured Slot Power Limit Scale
(CSPLS) field.
– Byte 1 bits 1:0 of the message payload are written to the Captured Slot Power Limit Value
(CSPLV) field.