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IDT Clocking, Reset and Initialization

PES12T3G2 User Manual

2 - 8

January 28, 2013

Notes

When slot power is disabled by writing a one to the PCC bit, the corresponding downstream port reset

output is asserted and then slot power is disabled. The time between the assertion of the PxRSTN signal
and the negation of the PxPEP signal is controlled by the value in the Reset Negation to Slot Power
(RST2PWR) field in the HPCFGCTL register.

Power Good Controlled Reset Output

As in the Power Enable Controlled Reset mode, in this mode a downstream port reset output state is

controlled as a side effect of slot power being turned on or off. However, the timing in this mode depends on
the power good state of the slot’s power supply. The operation of this mode is illustrated in Figure 2.4.

Figure 2.4 Power Good Controlled Reset Output Mode Operation

The operation of this mode is similar to that of the Power Enable Controlled Reset mode except that

when power is enabled, the negation of the corresponding port reset output occurs as a result of and after
assertion of the slot’s Power Good (PxPWRGDN) signal is observed. The time between the assertion of the
PxPWRGDN signal and the negation of the PxRSTN signal is controlled by the value in the Slot Power to
Reset Negation (PWR2RST) field in the HPCFGCTL register.

When slot power is disabled by writing a one to the PCC bit, the corresponding downstream port reset

output is asserted and then slot power is disabled. The time between the assertion of the PxRSTN signal
and the negation of the PxPEP signal is controlled by the value in the Reset Negation to Slot Power
(RST2PWR) field in the HPCFGCTL register.

If at any point while a downstream port is not being reset (i.e., PxRSTN is negated) a power fault is

detected (i.e., PxPWRGDN is negated), then the corresponding port reset output is immediately asserted.
Since the PxPWRGDN signal is an I/O expander input, it may not be possible to meet a profile’s power level
invalid to reset asserted timing specification (i.e., PxPWRGDN to PxRSTN). Systems that require a shorter
time interval may implement this functionality external to the PES12T3G2.

PxPEP

PxPWRGDN

T

PWR2RST

PxRSTN

T

RST2PWR

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Summary of Contents for 89HPES12T3G2

Page 1: ...Silver Creek Valley Road San Jose California 95138 Telephone 800 345 7015 408 284 8200 FAX 408 284 2775 Printed in U S A 2013 Integrated Device Technology Inc IDT 89HPES12T3G2 PCI Express Switch Preli...

Page 2: ...PLES CONTAINED IN ANY IDT PUBLICATION OR PUBLIC DISCLOSURE OR THAT IS CONTAINED ON ANY IDT INTERNET SITE IN NO EVENT WILL IDT BE LIABLE FOR ANY DIRECT CONSEQUENTIAL INCIDENTAL INDIRECT PUNITIVE OR SPE...

Page 3: ...s or alternate functions Chapter 5 SMBus Interfaces describes the operation of the 2 SMBus interfaces on the PES12T3G2 Chapter 6 Power Management describes the power management capability structure lo...

Page 4: ...x 1 D ABC x 2 D ABCyD Data Units The following data unit terminology is used in this document In quadwords bit 63 is always the most significant bit and bit 0 is the least significant bit In double w...

Page 5: ...ite RCW Software can read the register bits with this attribute Reading the value will automatically cause the register bits to be reset to zero Writes cause the register bits to be modified Reserved...

Page 6: ...ter to Chapter 8 October 31 2008 In Chapter 8 revised description L0SEL field in the PCIELCAP register and LDIS field in the PCIELCTL register September 15 2010 In Table 1 9 changed Buffer type for PC...

Page 7: ...1 4 Pin Description 1 4 Pin Characteristics 1 9 Port Configuration 1 10 Clocking Reset and Initialization Clocking 2 1 Initialization 2 1 Reset 2 2 Fundamental Reset 2 3 Hot Reset 2 5 Upstream Second...

Page 8: ...5 1 Master SMBus Interface 5 2 Initialization 5 2 Serial EEPROM 5 2 I O Expanders 5 6 Slave SMBus Interface 5 11 Initialization 5 11 SMBus Transactions 5 12 Power Management Introduction 6 1 PME Messa...

Page 9: ...dgeting Enhanced Capability 8 52 Switch Status and Control Registers 8 53 Physical Layer Control and Status Registers 8 60 Power Management Control and Status Registers 8 61 JTAG Boundary Scan Introdu...

Page 10: ...IDT Table of Contents PES12T3G2 User Manual iv January 28 2013 Notes...

Page 11: ...7 Table 5 6 I O Expander 0 Signals 5 9 Table 5 7 I O Expander 2 Signals 5 10 Table 5 8 I O Expander 4 Signals 5 10 Table 5 9 Slave SMBus Address When a Static Address is Selected 5 11 Table 5 10 Slave...

Page 12: ...IDT List of Tables PES12T3G2 User Manual vi January 28 2013 Notes...

Page 13: ...igure 5 7 Serial EEPROM Read or Write CMD Field Format 5 15 Figure 5 8 CSR Register Read Using SMBus Block Write Read Transactions with PEC Disabled 5 16 Figure 5 9 Serial EEPROM Read Using SMBus Bloc...

Page 14: ...IDT List of Figures PES12T3G2 User Manual viii January 28 2013 Notes...

Page 15: ...pansion ROM Base Address Register 0x038 8 17 GPECTL General Purpose Event Control 0x450 8 59 GPESTS General Purpose Event Status 0x454 8 60 GPIOCFG General Purpose I O Configuration 0x41C 8 56 GPIOD G...

Page 16: ...8 35 PMETOATIMER PME_TO_Ack Timer 0X708 8 61 PMLIMIT Prefetchable Memory Limit Register 0x026 8 16 PMLIMITU Prefetchable Memory Limit Upper Register 0x02C 8 17 PVCCAP1 Port VC Capability 1 0x204 8 46...

Page 17: ...nuary 28 2013 Notes VCR0TBL1 VC Resource 0 Arbitration Table Entry 1 0x224 8 50 VCR0TBL2 VC Resource 0 Arbitration Table Entry 2 0x228 8 51 VCR0TBL3 VC Resource 0 Arbitration Table Entry 3 0x22C 8 51...

Page 18: ...IDT Register List PES12T3G2 User Manual xii January 28 2013 Notes...

Page 19: ...or x1 Automatic lane reversal on all ports Automatic polarity inversion Ability to load device configuration from serial EEPROM Legacy Support PCI compatible INTx emulation Bus locking Highly Integra...

Page 20: ...e Ingress Processor TLP Checker Egress Processor Completion Processor Message Processor TLP Generator Hot Plug Controller Application Layer Data Link Layer Physical Layer SerDes Mux Demux SerDes Port...

Page 21: ...MS JTAG_TRST_N JTAG Pins VSS SWMODE 2 0 3 CCLKDS PERSTN REFCLKM MSMBSMODE PE0RP 0 PE0RN 0 PE0RP 3 PE0RN 3 PCI Express Switch SerDes Input PE0TN 0 PE0TP 3 PE0TN 3 PCI Express Switch SerDes Output Port...

Page 22: ...N are defined as being active or asserted when at a logic zero low level All other signals including clocks buses and select lines will be interpreted as being active or asserted when at a logic one h...

Page 23: ...elect This signal selects the fre quency of the reference clock input 0x0 100 MHz 0x1 125 MHz This pin should be static and not change following the negation of PERSTN Signal Type Name Description MSM...

Page 24: ...ion pin type Input Alternate function I O expander interrupt 0 input GPIO 3 I O General Purpose I O This pin can be configured as a general purpose I O pin GPIO 4 I O General Purpose I O This pin can...

Page 25: ...ERSTN I Fundamental Reset Assertion of this signal resets all logic inside PES12T3G2 and initiates a PCI Express fundamental reset RSTHALT I Reset Halt When this signal is asserted during a PCI Expres...

Page 26: ...ption REFRES0 I O Port 0 External Reference Resistor Provides a reference for the Port 0 SerDes bias currents and PLL calibration circuitry A 3 kOhm 1 resis tor should be connected from this pin to gr...

Page 27: ...tial2 Serial Link PE0RP 3 0 I PE0TN 3 0 O PE0TP 3 0 O PE2RN 3 0 I PE2RP 3 0 I PE2TN 3 0 O PE2TP 3 0 O PE4RN 3 0 I PE4RP 3 0 I PE4TN 3 0 O PE4TP 3 0 O PEREFCLKN 0 I HCSL Diff Clock Input Refer to Table...

Page 28: ...pstream port port 0 as an unsupported request i e the device does not exist Additionally SMBus accesses to configuration registers of a non existent device have an undefined effect Figure 1 3 illustra...

Page 29: ...ector consisting of the signals listed in Table 2 2 is sampled by the PES12T3G2 during a Fundamental Reset when PERSTN is negated The boot configuration vector defines essential parameters for switch...

Page 30: ...rs for downstream ports The value may be overridden by modifying the SCLK bit in the downstream port s PCIELSTS register CCLKUS Y Common Clock Upstream The assertion of this pin indicates that the ups...

Page 31: ...e link training state within 20 ms of the clearing of the Fundamental Reset condition Within 100 ms of the clearing of the Fundamental Reset condition all of the stacks are able to process configurati...

Page 32: ...hould be structured in a manner so as to ensure proper configuration prior to initiation of these side effects A warm reset initiated by a configuration request writing a one to the Fundamental Reset...

Page 33: ...rogress proceed to step 5 5 The PCI Express stacks and associated logic are held in a quasi reset state in which the following actions occur All links enter an active link training state within 20 ms...

Page 34: ...r BCTL When an Upstream Secondary Bus Reset occurs the following sequence is executed 1 Each downstream port whose link is up propagates the reset by transmitting TS1 ordered sets with the hot reset b...

Page 35: ...ts are tri stated A system designer should use a pull down on these signals if they are used as reset outputs The PES12T3G2 ensures through hardware that the minimum PxRSTN assertion pulse width is no...

Page 36: ...orresponding port reset output occurs as a result of and after assertion of the slot s Power Good PxPWRGDN signal is observed The time between the assertion of the PxPWRGDN signal and the negation of...

Page 37: ...ed and for others not to be inverted Lane Reversal The PCIe specification describes an optional lane reversal feature The PES12T3G2 supports the auto matic lane reversal feature outlined in the PCIe s...

Page 38: ...sociated with that port are powered down Dynamic Link Width Re Configuration Background The PCI Express 2 0 specification includes support for dynamic upconfiguration of link widths This optional capa...

Page 39: ...pport in the PES12T3G2 The PES12T3G2 supports dynamic link width upconfiguration and down configuration in response to link partner requests The PES12T3G2 ports do not autonomously initiate link width...

Page 40: ...ed in the PCIe 2 0 specification Link Speed Negotiation in the PES12T3G2 The PES12T3G2 ports support per lane data rates of 5 0 Gbps and 2 5 Gbps The highest data rate of each link is determined dynam...

Page 41: ...the bandwidth is required Software may also choose to change the link speed due to link reliability reasons i e a link that has reliability problems at 5 0 Gbps may be down graded to 2 5 Gbps As ment...

Page 42: ...k being downgraded from 5 0 Gbps to 2 5 Gbps the Link Bandwidth Management Status LBWSTS bit is set in the PCI Express Link Status PCIELSTS register for downstream ports only Additionally the PHY LTSS...

Page 43: ...L0 Fully operational link state L0s Automatically entered low power state with shortest exit latency L1 Lower power state than L0s May be automatically entered or directed by software by placing the d...

Page 44: ...rt will only request entry into the L1 state when all of the downstream ports which are not in a low power state i e D3 and whose link is not down are in the L1 state Link Status Associated with each...

Page 45: ...be used in the link The PES12T3G2 s downstream ports ignore the link partner s desired de emphasis and always choose the de emphasis setting in the SDE field of the port s PCIELCTL2 register Low Swing...

Page 46: ...IDT Link Operation PES12T3G2 User Manual 3 10 January 28 2013 Notes...

Page 47: ...ng the GPIO pins as outputs since an incorrect configuration could cause damage to external components as well as the PES12T3G2 GPIO Configuration Associated with each GPIO pin is a bit in the GPIOFUN...

Page 48: ...ister is driven on the pin System designers should treat the GPIO outputs as asynchronous outputs The actual value of the output pin can be determined by reading the GPIOD register GPIO Pin Configured...

Page 49: ...n the unified configuration shown in Figure 5 1 a the master and slave SMBuses are tied together and the PES12T3G2 acts both as an SMBus master as well as an SMBus slave on this bus This requires that...

Page 50: ...ial EEPROM the master SMBus interface reads configuration blocks from the serial EEPROM and updates corresponding registers in the PES12T3G2 Any PES12T3G2 software visible register in any port may be...

Page 51: ...ble word initialization sequence this value is always 0x0 The final DATA field contains the double word initialization value Figure 5 2 Single Double Word Initialization Sequence Format The second typ...

Page 52: ...ure 5 4 Configuration Done Sequence Format The checksum in the configuration done sequence enables the integrity of the serial EEPROM initializa tion to be verified Since uninitialized EEPROMs typical...

Page 53: ...ith the byte address of the serial EEPROM location to be read and the Operation OP field to read The Busy BUSY bit should then be checked If the EEPROM is not busy then the read operation may be initi...

Page 54: ...while I O expander four is used to provide link status and activity LED control I O expander signals associated with LED control i e link status and activity are active low i e driven low when an LED...

Page 55: ...ough I O 1 7 to I O expander register 7 Read value of I O expander register 0 to obtain the current state of the lower eight I O expander bits i e I O 0 0 through I O 0 7 Read value of I O expander re...

Page 56: ...e Chapter 4 General Purpose I O Whenever the PES12T3G2 needs to change the state of an I O expander signal output a master SMBus transaction is initiated to update the state of the I O expander This w...

Page 57: ...ll correspond to those at the time the SMBus transac tions are initiated It is not possible to toggle SMBus I O expander outputs by modifying data values during serial EEPROM initialization During a F...

Page 58: ...O 0 1 I Unused 2 I O 0 2 I Unused 3 I O 0 3 I Unused 4 I O 0 4 O Unused 5 I O 0 5 O Unused 6 I O 0 6 O Unused 7 I O 0 7 O Unused 8 I O 1 0 I Unused 9 I O 1 1 I Unused 10 I O 1 2 I P2PWRGDN Port 2 pow...

Page 59: ...ecified by the SSMBADDR 5 3 1 signals as shown in Table 5 9 3 I O 0 3 O Unused 4 I O 0 4 O P4LINKUPN Port 4 link up status output 5 I O 0 5 O Unused 6 I O 0 6 O Unused 7 I O 0 7 O Unused 8 I O 1 0 O P...

Page 60: ...ata associated with a command then the command is NACKed This indicates to the master that the transaction should be retried Bit Field Name Description 0 END End of transaction indicator Setting both...

Page 61: ...Code field described in Table 5 10 1 BYTCNT Byte Count The byte count field is only transmitted for block type SMBus transactions SMBus word and byte accesses do not contain this field The byte count...

Page 62: ...ed and not that the operation completed without error 7 WERR Read Only and Clear Write Error This bit is set if the last CSR write SMBus transaction was not claimed by a device Success indicates that...

Page 63: ...set if an unexpected NACK is observed during a master SMBus transaction when accessing the serial EEPROM This bit has the same function as the NAERR bit in the SMBUSSTS register The setting of this b...

Page 64: ...CCODE START END S PES12T3G2 Slave SMBus Address Wr A A CCODE START END S PES12T3G2 Slave SMBus Address Rd DATALM DATALL A A A A A P ADDRU A S PES12T3G2 Slave SMBus Address Wr A N CCODE START END P PE...

Page 65: ...R A ADDRL A CCODE START END ADDRU A DATA A P PEC A ADDRU N A ADDRL CMD status S PES12T3G2 Slave SMBus Address Wr A A CMD read A ADDRL A CCODE START Word S PES12T3G2 Slave SMBus Address Wr A CCODE STAR...

Page 66: ...IDT SMBus Interfaces PES12T3G2 User Manual 5 18 January 28 2013 Notes...

Page 67: ...he entire device When the upstream port enters a low power state and the PME_TO_Ack messages are received then the entire device is placed into a low power state The PES12T3G2 supports the following d...

Page 68: ...This includes both the case when the downstream port is in the D3hot state or the entire switch is in the D3hot state The generation of a PME message by downstream ports necessitates the implementati...

Page 69: ...ownstream port that does not receive a PME_TO_Ack message in the time out period specified in the PME_TO_Ack Time Out PMETOATO field in its corresponding PME_TO_Ack Timer PMETOATIMER register declares...

Page 70: ...IDT Power Management PES12T3G2 User Manual 6 4 January 28 2013 Notes...

Page 71: ...upstream port serves as the add in card s PCIe interface In this application the upstream port may be hot plugged into a slot on the main system Finally Figure 7 3 illustrates the use of the PES12T3G2...

Page 72: ...implemented or on the add in board When located on the add in board state changes are communicated between the hot plug controller asso ciated with the slot and the add in card via hot plug messages T...

Page 73: ...external I O Expander module and through in band presence detect The Presence Detect Control PDETECT field in the Hot Plug Configuration Control HPCFGCTL register may be used to control the mechanism...

Page 74: ...ts Hot Plug Interrupts and Wake up The hot plug controller associated with a downstream slot may generate an interrupt or wake up event Hot plug interrupts are only generated when the Hot Plug Interru...

Page 75: ...tionality associated with the port remains unchanged INTx MSI and PME events from other sources are also unaffected The enhanced hot plug signalling mechanism supported by the PES12T3G2 is graphically...

Page 76: ...rge voltage Since no clock is present during physical connection the device will maintain all outputs in a high impedance state even when no clock is present The I O cells meet VI requirements for hot...

Page 77: ...ts contain an MSI capability structure which is not present in the upstream port Reading from an upstream port offset not defined in Table 8 2 or a downstream offset not defined in Table 8 3 returns a...

Page 78: ...ced Capability PCIe Virtual Channel Enhanced Capability Device Serial Number Enhanced Capability Advanced Error Reporting Enhanced Capability 0x000 0x040 0x0D0 0x0F0 Type 1 Configuration Header PCI Ex...

Page 79: ...0x01A on page 8 14 0x01B Byte P0_SLTIMER SLTIMER Secondary Latency Timer Register 0x01B on page 8 14 0x01C Byte P0_IOBASE IOBASE I O Base Register 0x01C on page 8 14 0x01D Byte P0_IOLIMIT IOLIMIT I O...

Page 80: ...C4 on page 8 35 0x0D0 0x0DC Reserved 0x0F0 Dword P0_SSIDSSVIDCAP SSIDSSVIDCAP Subsystem ID and Subsystem Vendor ID Capability 0x0F0 on page 8 37 0x0F4 Dword P0_SSIDSSVID SSIDSSVID Subsystem ID and Sub...

Page 81: ...DWord P0_VCR0TBL3 VCR0TBL3 VC Resource 0 Arbitration Table Entry 3 0x22C on page 8 51 0x280 Dword P0_PWRBCAP PWRBCAP Power Budgeting Capabilities 0x280 on page 8 52 0x284 Dword P0_PWRBDSEL PWRBDSEL P...

Page 82: ...c Register Definition 0x000 Word Px_VID VID Vendor Identification Register 0x000 on page 8 10 0x002 Word Px_DID DID Device Identification Register 0x002 on page 8 10 0x004 Word Px_PCICMD PCICMD PCI Co...

Page 83: ...ress Capability 0x040 on page 8 19 0x044 DWord Px_PCIEDCAP PCIEDCAP PCI Express Device Capabilities 0x044 on page 8 20 0x048 Word Px_PCIEDCTL PCIEDCTL PCI Express Device Control 0x048 on page 8 21 0x0...

Page 84: ...Dword Px_AERUEM AERUEM AER Uncorrectable Error Mask 0x108 on page 8 40 0x10C Dword Px_AERUESV AERUESV AER Uncorrectable Error Severity 0x10C on page 8 42 0x110 Dword Px_AERCES AERCES AER Correctable E...

Page 85: ...er Budgeting Power Budget Capability 0x28C on page 8 53 0x300 Dword Px_PWRBDV0 PWRBDV 7 0 Power Budgeting Data Value 7 0 0x300 0X31C on page 8 53 0x304 Dword Px_PWRBDV1 PWRBDV 7 0 Power Budgeting Data...

Page 86: ...0x1 enable Enable I O space 1 MAE RW 0x0 Memory Access Enable When this bit is cleared the bridge does not respond to memory and prefetchable memory space access from the primary bus specified by MBAS...

Page 87: ...he bridge This bit has no effect on interrupts forwarded from the secondary to the primary interface 15 11 Reserved RO 0x0 Reserved field Bit Field Field Name Type Default Value Description 2 0 Reserv...

Page 88: ...fault Value Description 7 0 RID RWL Revision ID This field contains the revision identification number for the device See section Revision ID on page 1 4 Bit Field Field Name Type Default Value Descri...

Page 89: ...ent BIST Bit Field Field Name Type Default Value Description 31 0 BAR RO 0x0 Base Address Register Not applicable Bit Field Field Name Type Default Value Description 31 0 BAR RO 0x0 Base Address Regis...

Page 90: ...O addressing 0x1 io32 32 bit I O addressing 3 1 Reserved RO 0x0 Reserved field 7 4 IOBASE RW 0xF I O Base The IOBASE and IOLIMIT registers are used to control the forwarding of I O transactions betwee...

Page 91: ...15 DPE RW1C 0x0 Detected Parity Error This bit is set by the bridge whenever it receives a poisoned TLP on the secondary side regardless of the state of the PERRE bit in the PCI Command register Bit...

Page 92: ...primary interface of the bridge PMBASEU specifies the remaining bits Bit Field Field Name Type Default Value Description 0 PMCAP RO 0x1 Prefetchable Memory Capability Indicates if the bridge supports...

Page 93: ...scription 15 0 IOBASEU RW 0xFFFF I O Address Base Upper This field specifies the upper 16 bits of IOBASE When the IOCAP field in the IOBASE register is cleared this field becomes read only with a valu...

Page 94: ...2 INTB Bridge generates INTB interrupts 0x3 INTC Bridge generates INTC interrupts 0x4 INTD Bridge generates INTD interrupts Bit Field Field Name Type Default Value Description 0 PERRE RW 0x0 Parity Er...

Page 95: ...served field 6 SRESET RW 0x0 Secondary Bus Reset Setting this bit triggers a secondary bus reset In the upstream port setting this bit initiates a Upstream Second ary Bus Reset In a downstream port se...

Page 96: ...e of the Tag field as a requester 8 6 E0AL RO 0x0 Endpoint L0s Acceptable Latency This field indicates the acceptable total latency that an endpoint can withstand due to transition from the L0s state...

Page 97: ...ld Bit Field Field Name Type Default Value Description 0 CEREN RW 0x0 Correctable Error Reporting Enable This bit controls reporting of correctable errors 1 NFEREN RW 0x0 Non Fatal Error Reporting Ena...

Page 98: ...ional effect on the behavior of the bridge 15 Reserved RO 0x0 Reserved field Bit Field Field Name Type Default Value Description 0 CED RW1C 0x0 Correctable Error Detected This bit indicates the status...

Page 99: ...IT L0s Exit Latency This field indicates the L0s exit latency for the given PCI Express link The default value of 0x5 corre sponds to a L0s exit latency of 1 s to 2 s 17 15 L1EL RWL 0x2 L1 Exit Latenc...

Page 100: ...ult Value Description 1 0 ASPM RW 0x0 Active State Power Management ASPM Control This field controls the level of ASPM supported by the link The initial value corresponds to disabled The value contain...

Page 101: ...0x0 Extended Sync When set this bit forces transmission of addi tional ordered sets when exiting the L0s state and when in the recovery state 8 CLKPWRMGT RO 0x0 Enable Clock Power Management The PES12...

Page 102: ...ror has occurred The value of this field is undefined in the PCIe base 2 0 specifica tion 11 LTRAIN RO 0x0 Link Training When set this bit indicates that link training is in progress Specifically this...

Page 103: ...s initiated by the downstream component that was indi cated as an autonomous change If the LBN field in the PCIELCAP register is cleared this field is hardwired to zero This field is hardwired to zero...

Page 104: ...imit Scale This field specifies the scale used for the Slot Power Limit Value SPLV 0x0 x1 1 0x 0x1 xp1 0 1x 0x2 xp01 0 01x 0x3 xp001 0 001x A Set_Slot_Power_Limit message is generated using this field...

Page 105: ...cted Changed Enable This bit when set enables the generation of a Hot Plug interrupt or wake up event on a pres ence detect change event This bit is read only and has a value of zero when the correspo...

Page 106: ...Power on 0x1 off Power off 11 EIC RW 0x0 Electromechanical Interlock Control This field always returns a value of zero when read If an electromechanical interlock is imple mented a write of a one to t...

Page 107: ...osed 0x1 open MRL open 6 PDS RO 0x1 Presence Detect State This bit indicates the presence of a card in the slot corresponding to the port and reflects the state of the Presence Detect status 0x0 empty...

Page 108: ...d 5 0 Gbps operation Set ting this field to an unsupported value produces undefined results 0x1 gen1 2 5 Gbps 0x2 gen2 5 0 Gbps others reserved 4 ECOMP RW 0x0 Sticky Enter Compliance Software is permi...

Page 109: ...mV for low swing 0x4 300 mV for full swing and 200 mv for low swing 0x5 200 mV for full swing and 100 mv for low swing 0x6 0x7 Reserved This register is intended for debug compliance testing purpose...

Page 110: ...en the link operates at 2 5 Gbps 15 1 Reserved RO 0x0 Reserved field Bit Field Field Name Type Default Value Description 31 0 Reserved RO 0x0 Reserved field Bit Field Field Name Type Default Value Des...

Page 111: ...e a PME Bits 27 30 and 31 are set to indicate that the bridge will forward PME messages The switch does not forward PME messages in D3cold This func tionality may be supported in the system by routing...

Page 112: ...upstream port never generates a PME this bit will never be set in that port 21 16 Reserved RO 0x0 Reserved field 22 B2B3 RO 0x0 B2 B3 Support Does not apply to PCI Express 23 BPCCE RO 0x0 Bus Power Cl...

Page 113: ...ield Field Name Type Default Value Description 31 0 UADDR RW 0x0 Upper Message Address This field specifies the upper portion of the DWORD address of the MSI memory write transaction If the contents o...

Page 114: ...ration register number as defined by Section 7 2 2 of the PCI Express Base Specification Rev 1 0a 11 8 EREG RW 0x0 Extended Register Number This field selects the extended con figuration register numb...

Page 115: ...rise down error is detected and the SDERR bit in the PCIELCAP reg ister is set 11 6 Reserved RO 0x0 Sticky Reserved field 12 POISONED RW1C 0x0 Sticky Poisoned TLP Status This bit is set when a poisone...

Page 116: ...in the advanced capability structure the First Error Pointer field FEPTR in the AERCTL register is not updated and an error is not reported to the root complex This bit does not affect the state of th...

Page 117: ...TR in the AERCTL register is not updated and an error is not reported to the root complex This bit does not affect the state of the corresponding bit in the AERUES register 19 ECRC RW 0x0 Sticky ECRC...

Page 118: ...Control Protocol Error Severity If the corresponding event is not masked in the AERUEM register then when the event occurs this bit controls the severity of the reported error If this bit is set the e...

Page 119: ...rted as a fatal error When this bit is cleared the event is reported as an uncorrectable error 31 22 Reserved RO 0x0 Reserved field Bit Field Field Name Type Default Value Description 0 RCVERR RW1C 0x...

Page 120: ...the AERCES register the corresponding event is not reported to the root complex 11 9 Reserved RO 0x0 Reserved field 12 RPLYTO RW 0x0 Sticky Replay Timer Time Out Mask When this bit is set the corre s...

Page 121: ...uncorrectable error Bit Field Field Name Type Default Value Description 31 0 HL RO 0x0 Sticky Header Log This field contains the 3rd doubleword of the TLP header that resulted in the first reported u...

Page 122: ...XTPTR RWL 0x0 Next Pointer The value of 0x0 indicates that there are no extended capabilities Bit Field Field Name Type Default Value Description 2 0 EVCCNT RO 0x0 Extended VC Count The value 0x0 indi...

Page 123: ...address of the Virtual Channel Capability structure in double quad words 16 bytes The value of zero indicates that the VC arbitration table is not present Bit Field Field Name Type Default Value Desc...

Page 124: ...LOFF RO Upstream 0x2 Down stream 0x0 Port Arbitration Table Offset This field contains the offset of the port arbitration table from the base address of the Virtual Channel Capability structure in dou...

Page 125: ...Reserved RO 0x0 Reserved field 16 PATS RO 0x0 Port Arbitration Table Status This bit indicates the coherency status of the port arbitration table associated with the VC resource and is valid only whe...

Page 126: ...nding port arbitration period 19 16 PHASE4 RW 0x4 Phase 4 This field contains the port ID for the corresponding port arbitration period 23 20 PHASE5 RW 0x6 Phase 5 This field contains the port ID for...

Page 127: ...s the port ID for the corresponding port arbitration period 23 20 PHASE21 RW 0x2 Phase 21 This field contains the port ID for the corresponding port arbitration period 27 24 PHASE22 RW 0x4 Phase 22 Th...

Page 128: ...mpatibility with version 1 of the specification If the power budgeting capability is used then this field should be initialized with data from a serial EEPROM 31 20 NXTPTR RWL 0x0 Next Pointer Bit Fie...

Page 129: ...t is set in the Switch Control SWCTL register When the PWRBDVUL bit is cleared this regis ter is read only and writes are ignored If the power budgeting capability is used then this field should be in...

Page 130: ...set all of the switch logic except the SMBus interface remains in a reset state In this state reg isters in the device may be initialized by the slave SMBus inter face When this bit is cleared normal...

Page 131: ...t the polarity of the PxAIN output is inverted in all ports 5 IPXPIN RW 0x0 Sticky Invert Polarity of PxPIN When this bit is set the polarity of the PxPIN output is inverted in all ports 6 IPXPEP RW 0...

Page 132: ...W 0x14 Sticky Reset Negation This field contains the delay from negation of a downstream port s reset to disabling of a downstream port s power in units of 10 mS A value of zero corresponds to no dela...

Page 133: ...g a Fundamental Reset this bit is set when serial EEPROM initialization completes or when an error is detected 25 NAERR RW1C 0x0 No Acknowledge Error This bit is set if an unexpected NACK is observed...

Page 134: ...CHECK SUM RW 0x0 Sticky Ignore Checksum Errors When this bit is set serial EEPROM initialization checksum errors are ignored i e the checksum always passes 21 18 Reserved RO 0x0 Reserved field 22 SMBD...

Page 135: ...ce 16 8 Reserved RO 0x0 Reserved field 23 17 IOE2ADDR RWL 0x0 Sticky I O Expander 2 Address This field contains the SMBus address assigned to I O expander 2 on the master SMBus interface 31 24 Reserve...

Page 136: ...rved RO 0x0 Reserved field Bit Field Field Name Type Default Value Description 1 0 Reserved RO 0x0 Reserved field 2 P2GPES RO 0x0 Port 2 General Purpose Event Status When this bit is set the correspon...

Page 137: ...d For the upstream port writing of a one to this bit always results in the action specified by this bit to take effect after 1ms The PES12T3G2 always returns a completion to the requester before the e...

Page 138: ...IDT Configuration Registers PES12T3G2 User Manual 8 62 January 28 2013 Notes...

Page 139: ...3G2 Test Access Point The system logic utilizes a 16 state TAP controller a six bit instruction register and five dedicated pins to perform a variety of functions The primary use of the JTAG TAP Contr...

Page 140: ...T active low Asynchronous reset for JTAG TAP controller internal pull up JTAG_TCK Input JTAG Clock Test logic clock JTAG_TMS and JTAG_TDI are sampled on the rising edge JTAG_TDO is output on the falli...

Page 141: ...E0RP 3 0 I O PE0TN 3 0 O C PE0TP 3 0 O PE2RN 3 0 I O PE2RP 3 0 I O PE2TN 3 0 O C PE2TP 3 0 O PE4RN 3 0 I O PE4RP 3 0 I O PE4TN 3 0 O C PE4TP 3 0 O PEREFCLKN 0 I PEREFCLKP 0 I REFCLKM I O SMBus MSMBADD...

Page 142: ...s or output enables Therefore the SAMPLE PRELOAD instruction must first be used to load suitable values into the boundary scan cells so that inappropriate values are not driven out onto the system pin...

Page 143: ...ster allows an instruction to be shifted serially into the device at the rising edge of JTAG_TCK The instruction is then used to select the test to be performed or the test register to be accessed or...

Page 144: ...te rapid testing of a given device all other devices are put into BYPASS mode Instruction Definition Opcode EXTEST Mandatory instruction allowing the testing of board level interconnec tions Data is t...

Page 145: ...e contains a Device ID register it must also contain a BYPASS register The only difference is that the BYPASS register will not be the default register selected during the TAP controller reset When th...

Page 146: ...nterfere with normal system operation the TAP controller should be forced into the Test Logic Reset controller state by continuously holding JTAG_TRST_N low and or JTAG_TMS high when the chip is in no...

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