IDT 89HPES12T3G2, Preliminary User'S Manual

Page: 129 / 146

IDT Configuration Registers
PES12T3G2 User Manual 8 - 53 January 28, 2013
Notes
PWRBPBC - Power Budgeting Power Budget Capability (0x28C)
PWRBDV[7:0] - Power Budgeting Data Value [7:0] (0x300 - 0X31C)
Switch Status and Control Registers
SWSTS - Switch Status (0x400)
Bit
Field
Field
Name
Type Default
Value
Description
0 SA RWL 0x0 System Allocated. When this bit is set, it indicates that the power
budget for the device is included within the system power budget
and that reported power data for this device should be ignored.
If the power budgeting capability is used, then this field should be
initialized with data from a serial EEPROM.
31:1 Reserved RO 0x0 Reserved field.
Bit
Field
Field
Name
Type Default
Value
Description
31:0 DV RW Undefined
Sticky
Data Value. This 32-bit field is used to hold power budget data in
the format described in Section 7.15.3 in the PCIe 2.0 Base Specifi-
cation.
This field may be read and written when the Power Budgeting Data
Value Unlock (PWRBDVUL) bit is set in the Switch Control
(SWCTL) register. When the PWRBDVUL bit is cleared, this regis-
ter is read-only and writes are ignored.
If the power budgeting capability is used, then this field should be
initialized with data from a serial EEPROM.
Bit
Field
Field
Name
Type Default
Value
Description
2:0 SWMODE RO HWINIT Switch Mode. These configuration pins determine the Whitney
switch operating mode.
0x0 - Normal Switch Mode
0x1 - Normal Switch Mode with Serial EEPROM initialization
0x2 - 0x7 Reserved
4:3 Reserved RO 0x0 Reserved field.
5 CCLKDS RO HWINIT Common Clock Downstream. This bit reflects the value of the
CCLKDS signal sampled during Fundamental Reset.
6 CCLKUS RO HWINIT Common Clock Upstream. This bit reflects the value of the
CCLKUS signal sampled during Fundamental Reset.
7 MSMB-
SMODE
RO HWINIT Master SMBus Slow Mode. This bit reflects the value of the
MSMBSMODE signal sampled during Fundamental Reset.
8 REFCLKM RO HWINIT PCI Express Reference Clock Mode Select. This bit reflects the
value of the REFCLKM signal sampled during Fundamental Reset.
9 RSTHALT RO HWINIT Reset Halt. This bit reflects the value of the RSTHALT signal sam-
pled during Fundamental Reset.