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IDT 89HPEB383, User Manual

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3. Data Path > Prefetching Algorithm

27

PEB383 User Manual

July 25, 2011

Integrated Device Technology, Inc.

Confidential - NDA Required

The PEB383 uses flow control buffers in the PCI Core for three categories of downstream traffic. The 
amount of flow control buffer space availability is conveyed to the other end of the component using 
flow control credits. The PEB383 advertises infinite credits for completions as it ensures enough buffer 
space is available to store the returned completion data before initiating a read request. The PEB383 
advertises initial flow control credits as follows. Each credit of data is 16 bytes. 

3.5

Prefetching Algorithm

 The PEB383 prefetches the data by default for the transaction that uses Memory Read Line or Memory 
Read Multiple command. The PEB383 does not prefetch the data by default for the transaction that 
uses the memory read command since the bridge does not know whether or not the transaction address 
falls in prefetchable region. 

The prefetch algorithm is configured for various commands as follows: 

•

Memory read – Controlled by P_MR, MRL_66 and MRL_33 of the 

“Prefetch Control Register”

. 

The default value of these bits indicates that either one Dword in 32-bit bus mode or two Dwords 
in 64-bit bus mode is prefetched. 

•

Memory read line – Controlled by P_MRL, MRL_66 and MRL_33 of the 

“Prefetch Control 

Register”

. The default value of these bits indicates that either 128 bytes in 32-bit bus mode or 

256 bytes in 64-bit bus mode is prefetched. The PEB383 prefetches one cacheline if P_MRL is set 
to 0. 

•

Prefetch algorithm for memory read multiple command is controlled by P_MRM, MRM_66 and 
MRM_33 of the 

“Prefetch Control Register”

. The default value of these bits indicates that either 

256 bytes in 32-bit bus mode or 384 bytes in 64-bit bus mode is prefetched. The PEB383 
prefetches two cachelines if P_MRM is set to 0. 

Table 9: Initial Credit Advertisement

Credit Type

Initial Advertisement

Posted Header (PH)

0x08

Posted Data (PD)

0x020

Non-Posted Header (NPH)

0x04

Non-Posted Data (NPD)

0x01

Completion Header (CPLH)

0x00 (Infinite)

Completion Data (CPLD)

0x000 (Infinite)

Summary of Contents for 89HPEB383

Page 1: ...ver Creek Valley Road San Jose California 95138 Telephone 800 345 7015 408 284 8200 FAX 408 284 2775 Printed in U S A 2011 Integrated Device Technology Inc IDT 89HPEB383 PCI Express Bridge User Manual July 2011 ...

Page 2: ...MPLES CONTAINED IN ANY IDT PUBLICATION OR PUBLIC DISCLOSURE OR THAT IS CONTAINED ON ANY IDT INTERNET SITE IN NO EVENT WILL IDT BE LIABLE FOR ANY DIRECT CONSEQUENTIAL INCIDENTAL INDIRECT PUNITIVE OR SPECIAL DAMAGES HOWEVER THEY MAY ARISE AND EVEN IF IDT HAS BEEN PREVIOUSLY ADVISED ABOUT THE POSSIBILITY OF SUCH DAMAGES The code examples also may be subject to United States export control laws and ma...

Page 3: ... 15 2 4 EEPROM Interface Signals 18 2 5 JTAG Interface Signals 19 2 6 Power up Signals 19 2 7 Power Supply Signals 20 3 Data Path 21 3 1 Overview 21 3 1 1 Upstream Data Path 21 3 1 2 Downstream Data Path 22 3 2 Transaction Management 23 3 2 1 Upstream Transaction Management 23 3 2 2 Downstream Transaction Management 24 3 3 Buffer Structure 24 3 3 1 Upstream Non posted Buffer 24 3 3 2 Upstream Post...

Page 4: ...g 45 5 2 5 Type 1 to Special Cycle Forwarding 46 5 3 PCIe Enhanced Configuration Mechanism 46 5 4 Configuration Retry Mechanisms 47 6 Bridging 49 6 1 Overview 49 6 2 Flow Control Advertisements 49 6 3 Buffer Size and Management 50 6 4 Assignment of Requestor ID and Tag 50 6 5 Forwarding of PCIe to PCI 50 6 5 1 PCIe Memory Write Request 50 6 5 2 PCIe Non posted Requests 50 6 6 Forwarding of PCI to ...

Page 5: ...rface 74 9 3 PCI as Originating Interface 75 9 3 1 Received PCI Errors 76 9 3 2 Unsupported Request Completion Status 79 9 3 3 Completer Abort Completion Status 79 9 4 Timeout Errors 79 9 4 1 PCIe Completion Timeout Errors 80 9 4 2 PCI Delayed Transaction Timeout Errors 80 9 5 Other Errors 80 9 6 Error Handling Tables 81 10 Reset and Clocking 87 10 1 Reset 87 10 1 1 PCIe Link Reset 88 10 1 2 PCI B...

Page 6: ...ess 111 13 6 1 Register Access from JTAG 111 13 6 2 Write Access to Registers from the JTAG Interface 111 13 6 3 Read Access to Registers from JTAG Interface 112 13 7 Dedicated Test Pins 113 13 8 Accessing SerDes TAP Controller 113 14 Register Descriptions 115 14 1 Overview 115 14 2 PCI Configuration Space 117 14 3 Register Map 120 14 3 1 PCI Identification Register 123 14 3 2 PCI Control and Stat...

Page 7: ...4 5 6 EEPROM Control Register 166 14 5 7 Secondary Bus Device Mask Register 167 14 5 8 Short term Caching Period Register 169 14 5 9 Retry Timer Status Register 170 14 5 10 Prefetch Control Register 171 14 6 PCIe Capability Registers 173 14 6 1 PCIe Capabilities Register 173 14 6 2 PCIe Device Capabilities Register 175 14 6 3 PCIe Device Control and Status Register 177 14 6 4 PCIe Link Capabilitie...

Page 8: ...e Offset Address Calculation 207 14 9 2 PCIe Per Lane Transmit and Receive Registers 208 14 9 3 PCIe Transmit and Receive Status Register 208 14 9 4 PCIe Output Status and Transmit Override Register 209 14 9 5 PCIe Receive and Output Override Register 210 14 9 6 PCIe Debug and Pattern Generator Control Register 211 14 9 7 PCIe Pattern Matcher Control and Error Register 212 14 9 8 PCIe SS Phase and...

Page 9: ...ts vii 16 Packaging 235 16 1 Pinouts and Mechanical Diagrams 236 16 1 1 QFP Package Pinout 236 16 1 2 QFP Package Drawing 237 16 1 3 QFN Package Pinout 239 16 1 4 QFN Package Drawing 240 16 2 Thermal Characteristics 242 16 3 Moisture Sensitivity 244 17 Ordering Information 245 Glossary i Index iii ...

Page 10: ...Contents viii PEB383 User Manual July 25 2011 Integrated Device Technology Inc Confidential NDA Required ...

Page 11: ...gure 20 Arbitration Pointers Example 2 61 Figure 21 Interrupt Handling Diagram 63 Figure 22 PCIe Flowchart of Device Error Signaling and Logging Operations 67 Figure 23 Transaction Error Forwarding with PCIe as Originating Interface 68 Figure 24 Transaction Error Forwarding with PCI as Originating Interface 75 Figure 25 Reset Timing 88 Figure 26 PCIe Clocking 90 Figure 27 PCI Clocking 91 Figure 28...

Page 12: ... Inc Confidential NDA Required Figure 43 Input Timing Measurement Waveforms 232 Figure 44 Output Timing Measurement Waveforms 233 Figure 45 PCI TOV max Rising Edge AC Test Load 233 Figure 46 PCI TOV max Falling Edge AC Test Load 233 Figure 47 PCI TOV min AC Test Load 234 ...

Page 13: ...elayed Transaction 76 Table 17 ECRC Errors 81 Table 18 Poisoned TLP Errors 81 Table 19 Malformed TLP Errors 82 Table 20 Link and Flow Control Errors 83 Table 21 Uncorrectable Data Address Errors 84 Table 22 Received Master Target Abort Error 85 Table 24 Request Errors 86 Table 23 Completion Errors 86 Table 25 Reset Summary 87 Table 26 Reset Timing 88 Table 27 PCI Clocking 91 Table 28 PCIe Link Sta...

Page 14: ...racteristics 221 Table 46 PCI Clock PCI_CLK Specification 222 Table 47 PCIe Differential Transmitter Output Specification 223 Table 48 PCIe Differential Receiver Input Specifications 227 Table 49 Reference Clock PCIE_REFCLK_n p Electrical Characteristics 230 Table 50 Boundary Scan Test Signal Timings 231 Table 51 Reset Timing 231 Table 52 Thermal Specifications 66MHz 242 Table 53 Thermal Specifica...

Page 15: ...noted by a lowercase n An active high signal has an active state of logic 1 or the higher voltage level and is not denoted by a special character The following table illustrates the non differential signal naming convention Differential Signal Notation Differential signals consist of pairs of complement positive and negative signals that are measured at the same time to determine a signal s active...

Page 16: ...early design and functional information about a device It is available at the G2 gate which precedes the definition and planning phase Version 0 5 This specification describes early design and functional information about a device It is available after the G2 gate but during the definition and planning phase Version 0 75 This specification describes the majority of functional information about a d...

Page 17: ...TA min and max temperatures to 0 and 70 respectively In Section 15 3 updated old Table 43 and added new Table 44 for Power Dissipation values May 28 2010 In Chapter 16 Packaging updated QFP package drawing Added new Chapter 17 Ordering Information August 3 2010 In Chapter 17 added Tape and Reel to ordering codes November 23 2010 In Chapter 16 replaced existing QFN package drawing with revised PSC ...

Page 18: ...About this Document 4 PEB383 User Manual July 25 2011 Integrated Device Technology Inc Confidential NDA Required ...

Page 19: ...ce bus bridge that connects the PCI Express PCIe protocol to the PCI bus standard see Figure 1 The PEB383 s PCIe Interface supports a x1 lane PCIe configuration This enables the bridge to offer exceptional throughput performance of up to 2 5 Gbps per transmit and receive direction The device s PCI Interface can operate up to 66 MHz This interface offers designers extensive flexibility by supportin...

Page 20: ...re and forward for optimal latency performance Supports two modes of addressing Transparent For efficient flow through configurations Non transparent For address remapping of the PCIe and the PCI domains Compliant to the following specifications PCI Express Base Specification Revision 1 1 PCI Express to PCI PCI X Bridge Specification Revision 1 0 PCI to PCI Bridge Specification Revision 1 2 PCI Lo...

Page 21: ... ID SSVID Legacy mode support for subtractive decode Exclusive access using PCI_LOCKn Packaged in a 14x14mm 128 pin TQFP and a 10x10mm 132 pin QFN 1 2 2 PCIe Features 1 lane 128 byte maximum payload Advanced error reporting capability End to end CRC ECRC check and generation Up to four outstanding memory reads 512 byte read completion buffer ASPM L0s link state power management ASPM L1 Legacy inte...

Page 22: ...e Downstream read completion buffer Rx PHY SERDES Con figur atio n Reg ister s Data Link Layer 1K Replay buffers PCIe Primary Interface PCI Interface Secondary Interface Target interface 5 1 2 4 e n t r y u p s t r e a m p o s t e d w r i t e b u f f e r s M aster interface Transaction Layer TxPHY SERDES Data Link Layer Transaction Layer ordering Orderi ng Address decoding PCI Arbiter JTAG EEPROM ...

Page 23: ...loss and congestion ACK noACK protocol and End to End CRC ECRC Ensures reliable data delivery if bit errors occur Replay buffer Replays packets that are not acknowledged by the receiver NAK In contrast PCI is a parallel data interface at the physical layer PCI is a non packetized protocol When a bus master starts a read or a write transaction it indicates only the starting transaction address to t...

Page 24: ...0 bits in Secondary Retry Count Register A write initiated on the PCIe Interface with the target on the downstream PCI bus is written into the downstream posted write buffer The PEB383 acts as the master for the transaction and arbitrates for the PCI bus and initiates the write transaction The downstream posted write buffer is managed as a FIFO There will always be space available in the buffer to...

Page 25: ...R Card Application Figure 5 Motherboard Application 80E2000_TA002_01 PCI Bus x1 PCIe PEB383 Camera Video Decoder Camera Video Decoder Camera Video Decoder Camera Video Decoder 80E2040_TA001_01 PCI 10x10 mm footprint Supports up to four PCI devices off x1 PCIe PCIe PEB383 PCI Slot PCI Slot Processor Chipset CPU PCIe Slot Peripherals Graphics Memory ...

Page 26: ...nal Overview Typical Applications 12 PEB383 User Manual July 25 2011 Integrated Device Technology Inc Confidential NDA Required Figure 6 ExpressCard Application 80E2010_TA001_01 x1 PCIe PEB383 PCI I O Controller ...

Page 27: ...he types defined in the following table Table 1 Pin Types Pin Type Definition 3 3 OD 3 3V CMOS open drain output 3 3 3 state 3 3V CMOS tri state output 3 3 Bidir 3 3V CMOS bi directional 3 3 Bidir PU 3 3V CMOS bi directional with 265K 45K pull up resistor 3 3 Bidir OD 3 3V CMOS bi directional open drain 3 3 In 3 3V CMOS input 3 3 In PU 3 3V CMOS input with 265K 45K pull up resistor 3 3 Out 3 3V CM...

Page 28: ...nsmitter and the receiver Place a 0603 or 0402 0 075uF to 0 1uF ceramic capacitor on each TXD_n TXD_p signal PCIE_RXD_n PCIE_RXD_p PCIE Diff In Receive Data These differential pair signals receive PCIe 8b 10b encoded symbols and an embedded clock from the link partner DC blocking capacitors must be placed in the link between the transmitter and the receiver however the DC blocking capacitors are n...

Page 29: ...l clock or from one of the PCI_CLKO 4 0 signals see Clocking None PCI_CLKO 4 0 PCI Out PCI Output Clocks see Clocking Point to point connection to PCI device IDT recommends a 33 Ohm series termination resistor In Master clocking mode PCI_CLKO 4 should be connected to PCI_CLK PCI_DEVSELn PCI Bidir Device Select A target device asserts this signal when it decodes its address on the bus The master sa...

Page 30: ...Register on page 129 Note The PCI bus arbiter can be placed on the last bus master by bit 8 of PCI Miscellaneous 0 Register on page 129 PCI_GNTn 3 0 outputs connect directly to the PCI device s PCI_GNTn inputs Pull ups are not required on unused outputs PCI_INTDn PCI In Interrupt D Pull up 2 4K to VIO_PCI PCI_INTCn PCI In Interrupt C Pull up 2 4K to VIO_PCI PCI_INTBn PCI In Interrupt B Pull up 2 4...

Page 31: ...his signal indicates a parity error occurred during the current data phase The bus target that receives the data asserts this signal Pull up 8 2K to VIO_PCI PCI_PMEn PCI In Power Management Event This signal indicates a power management event occurred see Power Management Pull up 8 2K to VIO_PCI PCI_REQn 3 0 PCI In PCI Bidir Bus Request These signals are used to request access to the PCI bus They ...

Page 32: ... VIO_PCI PCI_TRDYn PCI Bidir Target Ready The bus target asserts this signal to indicate it is ready to complete the current data phase Pull up 8 2K to VIO_PCI Table 4 EEPROM Interface Signals Name Pin Type Description Design Recommendation SR_CLK 3 3 Out Serial ROM clock This signal is derived from REFCLKn p see System Diagram No pull up or pull down resistor is required SR_CSn 3 3 Out Serial ROM...

Page 33: ... Set This signal controls the state of the TAP controller Connect to 3 3V using a 2K pull up resistor JTAG_TRSTn 3 3 In PU Test Reset This signal forces the TAP controller into an initialized state This signal must be pulsed or pulled low externally to reset the TAP controller If JTAG is not used connect this pin to a 2K pull down resistor If JTAG is used connect to output of AND gate where inputs...

Page 34: ... SerDes Connect these signals to the 1 05V source through a ferrite bead b b For more information see Analog Power Supply Filtering in the PEB383 Board Design Guidelines VDDA_PCIE Analog power 3 3V analog power for SerDes Connect these signals to the 3 3V source through a ferrite bead b VDDA_PLL Analog power 1 05V analog power for PLL Connect these signals to the 1 05V source through a ferrite bea...

Page 35: ...f two different sized buffers for each transaction type posted non posted and completion see Figure 7 The first stage buffering in the PCI Core which supports the store and forward method meets the synchronization requirements of PCI and PCIe This buffer design also provides optimized throughput and improved latencies The second stage buffering in the PCIe Core which supports the cut through metho...

Page 36: ...rences synchronization and error handling requirements S c r a m b l e r Posted FIFO 512 by tes Non Posted FIFO 4 Entr ies CompletionFI FO 64 bytes R etry Bu ffer 1 KB Error Message TLP EH U C SR PME_n M a s t e r I n t e r f a c e T a r g e t I n t e r f a c e PostedBuffer 512 bytes N on Posted Q ueue 8 Entr i es D ownstream R ead CompletionBuffer 512 by te s PMC PME Mesaage TLP Posted Request No...

Page 37: ...s and are then made visible to TLP arbiter The TLPs are processed by the TLP arbiter only after ordering rules are satisfied The TLP arbiter selects one of the five input TLPs error message PME message posted completion and non posted TLPs in a round robin mode if sufficient credits and retry buffer space is available for the specific TLPs The TLP arbiter continues to check the available credit an...

Page 38: ...ks for LCRC and sequence number errors for packets received from the physical layer unit If there are no errors LCRC and sequence number fields are stripped and resultant TLP is sent to Transaction layer unit The Transaction layer unit checks for ECRC errors and framing violations based on header fields and ECRC fields in the TLP received from the Data link layer unit It extracts routing informati...

Page 39: ...eight request queue entries and its data is stored in a 32 bit register Non posted write requests are forwarded onto the PCIe Core in two PCIe clock cycles Request information is forwarded in the first cycle while 32 bit data is forwarded in the second cycle 3 3 2 Upstream Posted Buffer The upstream posted buffer is a FIFO of size 512 bytes that stores memory write transactions that originate on t...

Page 40: ...I side 3 3 4 Downstream Posted Buffer The 512 byte downstream posted write buffer stores the payload of memory write transactions that originate on the PCIe Interface and are destined for PCI devices The amount of space assigned to each transaction is dynamic The PEB383 uses an 8 deep request FIFO to store the request information including the first and last Dwords byte enables The PEB383 initiate...

Page 41: ...s falls in prefetchable region The prefetch algorithm is configured for various commands as follows Memory read Controlled by P_MR MRL_66 and MRL_33 of the Prefetch Control Register The default value of these bits indicates that either one Dword in 32 bit bus mode or two Dwords in 64 bit bus mode is prefetched Memory read line Controlled by P_MRL MRL_66 and MRL_33 of the Prefetch Control Register ...

Page 42: ...bus To enable Short Term Caching set the STC_EN bit in the PCI Miscellaneous Control and Status Register When enabled the PEB383 does not discard the additional prefetched data when the read transaction completes on the initiating bus The PEB383 then continues to prefetch data up to the amount specified in the Prefetch Control Register If the initiator generates a new transaction that requests the...

Page 43: ...gisters are effectively inversely decoded to determine the address ranges on the PCI Interface for transactions that are forwarded upstream to the PCIe Interface 4 2 Memory mapped I O Space Memory transactions are forwarded across the PEB383 when their address falls within a window defined by one of the following registers PCI Memory Base and Limit Register PCI PFM Base and Limit Register The memo...

Page 44: ...ory transactions on the PCI bus are ignored VGA_EN bit in PCI Bridge Control and Interrupt Register The PEB383 forwards memory transactions downstream from its PCIe Interface to its PCI Interface if a memory address is in the range defined by the Memory Base and Memory Limit registers when the base is less than or equal to the limit as shown in Figure 9 A memory transaction on the PCI Interface th...

Page 45: ...actions Memory Enable bit in PCI Control and Status Register Bus Master Enable bit in PCI Control and Status Register VGA Enable bit in PCI Bridge Control and Interrupt Register The PEB383 forwards memory transactions downstream from its PCIe Interface to its PCI Interface if a memory address is in the range defined by the Prefetchable Memory Base and Prefetchable Memory Limit registers Conversely...

Page 46: ... response of the bridge to I O transactions is controlled by the following configuration register bits I O Space Enable bit in PCI Control and Status Register Bus Master Enable bit in PCI Control and Status Register ISA Enable bit in PCI Bridge Control and Interrupt Register VGA Enable bit in PCI Bridge Control and Interrupt Register The I O Enable bit must be set for any I O transaction to be for...

Page 47: ...ytes of each 1 KB block within the first 64 KB of address space even if the address is within the I O base and limit All other transactions on the PCI bus are forwarded upstream if they fall outside the range defined by the I O base and limit registers If the ISA Enable bit is clear then all PCI bus I O addresses outside the range defined by the I O base and limit registers are forwarded upstream ...

Page 48: ...esses to VGA registers from the PCIe Interface to the PCI Interface and block forwarding from PCI to PCIe of these same accesses The VGA_16BIT_EN bit in the PCI Bridge Control and Interrupt Register selects between 10 bit and 16 bit VGA I O address decoding and is applicable when the VGA Enable bit is 1 VGA memory addresses are 0x0A_0000 through 0x0B_FFFF Secondary Interface 0x0_C000 0x0_FFFF 0x0_...

Page 49: ...6 Bits I O Limit and I O Limit Upper 16 Bits and in the first 64 KB of PCI I O Space 0000 0000h to 0000 FFFFh If this bit is set and the I O address meets the stated constraints the PEB383 blocks the forwarding of I O transactions downstream if the I O address is in the top 768 bytes of each naturally aligned 1 KB block If the ISA Enable bit is clear the PEB383 forwards downstream all I O addresse...

Page 50: ...xD000 0x0_xFFF 0x0_xC00 0x0_xCFF 0x0_x000 0x0_x0FF 0x0_x400 0x0_x4FF 0x0_x800 0x0_x8FF Primary Interface Downstream Upstream 0x0_x900 0x0_x9FF 0x0_x500 0x0_x7FF 0x0_x100 0x0_x3FF Secondary Interface 0x0_xD000 0x0_xFFF 0x0_xC00 0x0_xCFF 0x0_x000 0x0_x0FF 0x0_x400 0x0_x4FF 0x0_x800 0x0_x8FF Primary Interface Downstream Upstream 0x0_x900 0x0_x9FF 0x0_x500 0x0_x7FF 0x0_x100 0x0_x3FF ...

Page 51: ...ss remapping process PriSecNPDiff PriNPBase SecNPBase where PriSecNPDiff Defines the difference between the Primary Non prefetchable Base and the Secondary Non prefetchable Base PriNPBase Defined in the previous paragraph SecNPBase Defined by Secondary Bus Non prefetchable Address Remap Control Register and Secondary Bus Non prefetchable Upper Base Address Remap Register SecNPAddr PriNPAddr PriSec...

Page 52: ...chable Address Remap Control Register and Secondary Bus Prefetchable Upper Base Address Remap Register to SecFPLimit will not be claimed by the bridge on the PCI bus The Secondary Bus Non prefetchable Limit is described in the following equation SecNPLimit PriNPLimit PriSecNPDiff where PriNPLimit Defined by PCI Memory Base and Limit Register and the additional Primary Bus Non prefetchable Upper Li...

Page 53: ...gister PriNTMALimit SecNTMALimit PriSecNTMADiff where SecNTMALimit Defined by NTMA Secondary Lower Limit Register and NTMA Secondary Upper Limit Register PriSecNTMADiff See previous bullet A memory cycle whose address falls within a NTMA window on the PCI bus will have its address on the PCIe link modified by the following equation PriNTMAAddr SecNTMAAddr PriSecNTMADiff where SecNTMAAddr Secondary...

Page 54: ...e cycles to the PCI bus This allows I O addresses to be translated down into the address range that is available on the PCI bus There is no enable bit for I O address remapping any non zero value in this register remaps the I O transactions to a different address location as described in this section NTMA Window Prefetchable Window Non prefetchable Window NTMA Window Prefetchable Window Non prefet...

Page 55: ...that do not fall between the base and limit registers are handled as Unsupported Requests UR When the LEGACY bit is set the PROG field of PCI Class Register is changed to 0x1 indicating to software that a subtractive bridge is present When the LEGACY bit is set all PCIe capabilities are hidden from software and the following occurs 1 Next pointer in PCI Power Management Capability Register is set ...

Page 56: ...4 Addressing Legacy Mode 42 PEB383 User Manual July 25 2011 Integrated Device Technology Inc Confidential NDA Required ...

Page 57: ...transactions access devices that reside downstream of the PEB383 Type 1 transactions are converted to Type 0 transactions if they target devices that reside on the downstream PEB383 bus If the transaction is intended for a device that is downstream of the bus directly below the PEB383 the transaction is passed through the PEB383 as a Type 1 configuration transaction If the transaction is not targe...

Page 58: ...evice configuration in a hierarchical bus system The Bus Number field contained in the header of a Type 1 configuration transaction specifies a unique PCI bus in the PCI bus hierarchy The PEB383 compares the specified Bus Number with two register fields Secondary Bus Number and Subordinate Bus Number in PCI Bus Number Register that are programmed by system software or firmware to determine whether...

Page 59: ... Number value and the conditions for conversion to a Special Cycle transaction are not met the PEB383 forwards the transaction to the PCI bus as a Type 0 configuration transaction In this case a device connected to the PCI Interface of the bridge is the target of the Type 0 configuration transaction To translate and convert a PCIe Type 1 configuration transaction to a PCI Type 0 configuration tran...

Page 60: ...equest transaction it converts it to a Special Cycle on its PCI Interface when the following conditions are met by the transaction The Bus Number field matches the Secondary Bus Number register value The Device Number field is all ones equals 0b1_1111 The Function Number field is all ones equals 0b111 The Register Address and Extended Register Address are both all zeros equal 0b00_0000 and 0b0000 ...

Page 61: ...appropriate error completion on PCIe If the configuration request to PCI does not complete either successfully or with an error prior to timer expiration the bridge is required to return a completion with Configuration Retry Status CRS on PCIe for that request After the PEB383 returns a completion with CRS on PCIe it continues to keep the configuration transaction active on the PCI bus For PCI the...

Page 62: ...5 Configuration Transactions Configuration Retry Mechanisms 48 PEB383 User Manual July 25 2011 Integrated Device Technology Inc Confidential NDA Required ...

Page 63: ...ceiver on the other bus link The PCI Interface can operate in 32 bit PCI mode up to 66 MHz Transactions flow through the PEB383 can be classified as follows PCIe to PCI PCI to PCIe 6 2 Flow Control Advertisements The flow control method on the PCI Interface is managed through retries or disconnects where as on the PCIe link it is managed using flow control credits On the PCI Interface the PEB383 i...

Page 64: ...stream transactions the PEB383 sets the Tag field to a request enqueued entry number 6 5 Forwarding of PCIe to PCI The PEB383 forwards posted non posted and upstream read completions to the PCI devices and stores the non posted TLPs state information to return the completion TLPs to the PCIe Interface 6 5 1 PCIe Memory Write Request The PEB383 forwards the received PCIe Memory Write Requests to th...

Page 65: ...rmation is preserved and no additional bytes are requested for the transactions that fall into the non prefetchable address range for example Configuration I O and Memory read commands 6 6 Forwarding of PCI to PCIe The PEB383 forwards posted and non posted requests and downstream read completions to PCIe devices and stores the non posted requests state information to return the delayed completions...

Page 66: ... the PCI requester repeats the initial request and terminates the delayed transaction If short term caching is enabled see STC_EN in PCI Miscellaneous Control and Status Register the PEB383 responds to subsequent requests with the incremental addresses issued by the master until the programmed number of data bytes are transferred to the master or the short term discard timer is expired see ST_DIST...

Page 67: ...ons see PCIe as Originating Interface PCI Interface As a Master As a Target 0000b Interrupt Acknowledge NA NA 0001b Special Cycle Yes NA 0010b I O Read Yes Yes 0011b I O Write Yes Yes 0100b Rsvd NA NA 0101b Rsvd NA NA 0110b Memory Read Yes Yes 0111b Memory Write Yes Yes 1000b Rsvd NA NA 1001b Rsvd NA NA 1010b Configuration Read Yes NA 1011b Configuration Write Yes NA 1100b Memory Read Multiple Yes...

Page 68: ... Yes Yes MRdLk Memory Read Request Locked NA Yes MWr Memory Write Request Yes Yes IORd I O Read Request Yes Yes IOWr I O Write Request Yes Yes CfgRd0 Configuration Read Type 0 NA Yes CfgWr0 Configuration Write Type 0 NA Yes CfgRd1 Configuration Read Type 1 NA Yes CfgWr1 Configuration Write Type 1 NA Yes Msg Message Request Yes Yes MsgD Message Request with Data Payload NA Yes MsgD Vendor Defined V...

Page 69: ...3 Locked Transaction Unlock messages support locked transaction sequences in the downstream direction This type of message indicates the end of a locked sequence The PEB383 supports locked transactions in the downstream direction and uses unlocked messages to unlock itself from the PCIe Interface see Exclusive Access 6 9 4 Slot Power Limit These messages are transmitted to downstream devices by th...

Page 70: ... even if the relaxed ordering attribute bit is set However the device allows a Read completion with the relaxed ordering attribute bit set to pass a posted transaction Table entries with 1 and 2 are defined as follows 1 Indicates the ordering relationship when the relaxed ordering attribute bit is clear in the second transaction header information 2 Indicates the ordering relationship when the rel...

Page 71: ... received prior to the locked request are completed on the bus While in target lock state thePEB383 handles all the received TLPs with UR but continues to accept the transactions on the PCI Interface When thePEB383 enters into full lock state all upstream transactions on the PCI Interface are retried and all the downstream requests on the PCIe Interface except Memory transactions are handled as UR...

Page 72: ...6 Bridging Exclusive Access 58 PEB383 User Manual July 25 2011 Integrated Device Technology Inc Confidential NDA Required ...

Page 73: ...est master given grant 7 2 Block Diagram The bus arbiter handles internal requests from the PCI Core and external requests from devices on the PCI bus see Figure 17 When the arbiter is enabled the PEB383 asserts the grant for PCI devices and for the PCI Core When the arbiter is disabled there must be an external arbiter on the PCI bus that handles PEB383 requests through the PCI_REQ 0 n signal and...

Page 74: ...e bus on the PEB383 After servicing the requesters when the bus is in idle state the arbiter is parked on the last served requester The priority method is shown in Figure 18 Note that any one request input can only be mapped to high or low priority If for example PCI_REQ2n is mapped to low priority then the H2 state is skipped over Figure 18 PCI Arbitration Priority The PEB383 also keeps track of ...

Page 75: ...o requests occur at the same time in this example L3 and H1 then L3 is granted and the pointers advance as shown in Figure 20 Figure 20 Arbitration Pointers Example 2 Once L3 is completed the input requests are sampled again H0 and H1 are now requesting the bus H0 would then obtain access to the bus because the new priority ordering is H PEB383 H0 H1 H2 H3 L The initial ordering of the requests is...

Page 76: ...7 PCI Arbitration PCI Arbitration Scheme 62 PEB383 User Manual July 25 2011 Integrated Device Technology Inc Confidential NDA Required ...

Page 77: ...I X The PEB383 s PCI Interface forwards legacy INTx assertion de assertions in the form of Assert_INTx and Deassert_INTx messages on its PCIe link The PEB383 handles MSI and MSI X transactions as PCI memory write transactions When the bridge receives an MSI MSI X transaction on its PCI Interface it forwards it as a memory write TLP on its PCIe link Both INTx messages and MSI MSI X transactions flo...

Page 78: ...ded into the posted buffer A De assert message always follows an Assert message More then one interrupt pin can toggle at any point of time however a round robin arbitration schedules the interrupt message transmission There is no buffering for interrupt messages before loading them into the upstream posted buffer Therefore only one pair of Assert_INTx and Deassert_INTx messages is loaded into the...

Page 79: ...tion has an error severity level programmable by software and a corresponding error message generated on PCIe Each detected error condition has a default error severity level fatal or non fatal and when enabled has a corresponding error message generated on PCIe The error severity level is software programmable PCIe link error message generation is controlled by the following bits SERR_EN in the P...

Page 80: ...et for the corresponding errors on the PCIe Interface regardless of the error reporting enable bits The PEB383 also supports Advisory Non Fatal error messages in the case where a TLP Error detected is a Advisory Non Fatal Error and the Advisory Non Fatal Error mask bit ANFE in the PCIe Correctable Error Mask Register is not masked then a Correctable error message is generated instead of a Non Fata...

Page 81: ...9 Error Handling Overview 67 PEB383 User Manual July 25 2011 Integrated Device Technology Inc Confidential NDA Required Figure 22 PCIe Flowchart of Device Error Signaling and Logging Operations ...

Page 82: ...able 14 provides the translation a bridge has to perform when it forwards a non posted PCIe request read or write to PCI and the request is completed immediately on PCI either normally or with an error condition Table 13 Error Forwarding Requirements Step A to Step B for Received PCIe Errors Received PCIe Error Step A Forwarded PCI Error Mode 1 Parity Step B Write Request or Read Completion with P...

Page 83: ...isoned TLPs When the bridge receives a poisoned TLP it completes the following while forwarding it to the PCI Interface 1 If the severity of the PTLP in the PCIe Uncorrectable Error Severity Register is Non Fatal and the ANFE Mask bit is clear in PCIe Correctable Error Mask Register then A Correctable error message is generated if the COR_ERR_EN bit is set in the PCIe Device Control and Status Reg...

Page 84: ...ster and the bridge sees the PCI_PERRn pin asserted when forwarding a write request transaction with bad parity to the PCI bus The PERR_AD bit in the PCIe Secondary Uncorrectable Error Status Register is set Secondary Header is Logged and Secondary First Error Pointer is updated if enabled No error message is generated when PCI_PERRn is seen asserted by the bridge when forwarding a Poisoned TLP tr...

Page 85: ... message is generated on PCIe as per the severity level of UDERR bit in PCIe Secondary Uncorrectable Error Severity Register if the UDERR Mask bit is clear in PCIe Secondary Uncorrectable Error Mask Register and either SERR_EN bit is set in the PCI Control and Status Register or FTL_ERR_EN NFTL_ERR_EN bit is set in the PCIe Device Control and Status Register 7 S_SERR bit is set in the PCI Control ...

Page 86: ...Status bit is set in the PCIe Secondary Uncorrectable Error Status Register 4 Header is logged in the PCIe Secondary Header Log 1 Register and the SUFEP field is updated in the PCIe Secondary Error Capabilities and Control Register if PERR_AD Mask bit is clear in the PCIe Secondary Uncorrectable Error Mask Register and SUFEP is not valid 5 Error Fatal or Non Fatal message is generated on PCIe as p...

Page 87: ...3 R_MA bit is set in the PCIe Secondary Uncorrectable Error Status Register 4 Header is logged in the PCIe Secondary Header Log 1 Register and SUFEP is updated in the PCIe Secondary Error Capabilities and Control Register if R_MA Mask bit is clear in PCIe Secondary Uncorrectable Error Mask Register and ERR_PTR is not valid 5 Error Fatal or Non Fatal message is generated on PCIe as per the severity...

Page 88: ...e PCI Interface for posted requests it takes the following actions 1 Drops the entire transaction 2 R_TA bit is set in PCI Secondary Status and I O Limit and Base Register 3 R_TA bit is set in PCIe Secondary Uncorrectable Error Status Register 4 Header is logged in the PCIe Secondary Header Log 1 Register and ERR_PTR is updated in the PCIe Secondary Error Capabilities and Control Register if R_TA ...

Page 89: ...generated and the SERR_EN bit is set in PCI Control and Status Register 7 FTL_ERR_DTD NFTL_ERR_DTD bit is set in PCIe Device Control and Status Register 9 3 PCI as Originating Interface This section describes how the PEB383 handles errors for upstream transactions from PCI to PCIe see Figure 24 The bridge supports TLP poisoning as a Transmitter to permit proper forwarding of parity errors that occ...

Page 90: ...and Status Register if the S_PERESP bit is set The PERR pin is not asserted on the PCI bus 4 UDERR bit is set in PCIe Secondary Uncorrectable Error Status Register 5 Header is logged in the PCIe Secondary Header Log 1 Register and ERR_PTR is updated in the PCIe Secondary Error Capabilities and Control Register if UDERR Mask bit is clear in PCIe Secondary Uncorrectable Error Mask Register and ERR_P...

Page 91: ...PCI Control and Status Register if an error message Fatal Non Fatal is generated and the SERR_EN bit is set in PCI Control and Status Register 8 FTL_ERR_DTD NFTL_ERR_DTD bit is set in PCIe Device Control and Status Register 9 3 1 3 Uncorrectable Data Error on PCI Delayed Read Completions When the PEB383 detects PERR asserted by the initiating PCI master while forwarding a non poisoned read complet...

Page 92: ...evice Control and Status Register 7 S_SERR bit is set in PCI Control and Status Register if an error message Fatal Non Fatal is generated and the SERR_EN bit is set in PCI Control and Status Register 8 FTL_ERR_DTD NFTL_ERR_DTD bit is set in PCIe Device Control and Status Register 9 3 1 5 Uncorrectable Attribute Error When the PEB383 detects an Uncorrectable Attribute Error and parity error detecti...

Page 93: ... transaction initiated on the secondary interface results in a completion with Unsupported Request status the PEB383 returns 0xFFFF_FFFFto the originating master and normally terminates the read transaction on the originating interface by asserting TRDY When a non posted write transaction results in a completion with Unsupported Request status the PEB383 normally completes the write transaction on...

Page 94: ...ction Timeout Errors If a delayed transaction timeout is detected the PEB383 does the following 1 Error Fatal or Non Fatal message is generated on PCIe as per the severity level of DTDTE bit in PCIe Secondary Uncorrectable Error Severity Register if DTDTE Mask bit is clear in PCIe Secondary Uncorrectable Error Mask Register or DISCARD_SERR bit is set PCI Bridge Control and Interrupt Register and e...

Page 95: ...pped Table 18 Poisoned TLP Errors Error Details Primary Reporting Mechanism Secondary Reporting Mechanism Poisoned TLP Error 1 PCIe Device Control and Status Register COR_ERR_DTD FTL_ERR_DTD 2 PCIe Correctable Error Status Register ANFE in case of Advisory Non Fatal condition 3 PCIe Uncorrectable Error Status Register PTLP 4 PCI Control and Status Register S_SERR if a Fatal error message is sent a...

Page 96: ...s not match length specified in Completion TLP payload does not match length Mismatch between TD and presence of ECRC Address Length combination crosses 4KByte Received INTx message with TC 0 Received Power Management message with TC 0 Received Error message with TC 0 Received Unlock message with TC 0 TLP Type field uses undefined value Illegal byte enables 1 FBE 0 when Length 1DW 2 LBE 0 when len...

Page 97: ...ut subsequent UpdateFC contains non zero credit value Invalid that is non outstanding AckNack_Seq_Num in received Ack Nak DLLP 1 PCIe Uncorrectable Error Status Register DLPE 2 PCIe Device Control and Status Register FTL_ERR_DTD NFTL_ERR_DTD 3 Optional ERR_FATAL or ERR_NONFATAL message sent 4 PCI Control and Status Register S_SERR if error message is generated and SERR_EN is set same register TLP ...

Page 98: ...egister MDP_D if PCI Bridge Control and Interrupt Register S_PERESP PCI_PERRn asserted on the PCI Interface while forwarding a posted write transaction from PCIe 1 PCI Secondary Status and I O Limit and Base Register MDP_D if PCI Bridge Control and Interrupt Register S_PERESP 2 PCIe Secondary Uncorrectable Error Status Register PERR_AD PCI_SERRn detected on the PCI interface while forwarding trans...

Page 99: ...sk Register or MA_ERR bit is set in PCI Bridge Control and Interrupt Register and PCI Control and Status Register SERR_EN is set 2 PCIe Device Control and Status Register FTL_ERR_DTD NFTL_ERR_DTD 1 PCI Secondary Status and I O Limit and Base Register R_MA 2 PCIe Secondary Uncorrectable Error Status Register R_MA Master Abort on the PCI bus while forwarding a non posted write transaction from PCIe ...

Page 100: ...on 1 PCI Control and Status Register R_TA 1 PCI Secondary Status and I O Limit and Base Register S_TA Received Unexpected Completion Error 1 PCIe Uncorrectable Error Status Register UXC if not masked 2 PCIe Device Control and Status Register COR_ERR_DTD if ANFE N A Completion Timeout Error 1 PCIe Uncorrectable Error Status Register CTO if not masked 2 PCIe Device Control and Status Register COR_ER...

Page 101: ...ble 25 Reset Summary Reset Level PCI Definition Trigger EEPROM Load PEB383 Actions 0 Cold reset Warm reset PCIE_PERSTn Yes Initialize all registers to known state including sticky Drive and release PCI_RSTn 1 ms after PCIE_PERSTn is released 1 Hot reset Reset message or DL_down state Yes Initialize all registers to known state except sticky Drive and release PCI_RSTn 1 ms after PEB383 is completed...

Page 102: ...IE_PERSTn all of PEB383 s registers are in their power on reset state including sticky bits Clock PCIE_REFCLK_n p and power must be valid prior to the release of PCIE_PERSTn The timing diagram for a cold reset is displayed in Figure 25 while its values are listed in Table 26 Figure 25 Reset Timing 10 1 1 2 Warm Reset Level 0 A warm reset occurs without cycling power This is achieved by bringing PC...

Page 103: ...set on the PCI bus using PCI_RSTn There are four conditions that cause the bridge to drive reset onto the PCI bus 1 Assertion of PCIE_PERSTn cold warm reset 2 Receipt of a hot reset message on the PCIe link hot reset 3 PCIe link going into a DL_down state hot reset 4 Setting the PCI bus reset bit S_RESET in the PCI Bridge Control and Interrupt Register level 2 Software must ensure there are no req...

Page 104: ...he receive data is clocked into the PEB383 with the recovered clock The elastic buffer operates on the recovered byte clock from K28 5 and the internal generated 125 MHz clock The two clocks can vary by twice the ppm tolerance of the reference clock tolerance on any one device 300ppm Buffer overflow is prevented by discarding skip characters Figure 26 PCIe Clocking PCS PHY PCS PCIE_REFCLK_p PCIE_R...

Page 105: ...he decoder sets the divider ratios for programmable PLL as a function of PCI_M66EN and the PCI Miscellaneous Clock Straps Register PCI_M66EN selects 66 MHz when high and 33 MHz when low The PCI Miscellaneous Clock Straps Register allows this pin to be overwritten and one of the following speeds used 25 33 50 and 66 MHz Prior to the configuration of the PCI bus speed the PCI clock is in bypass mode...

Page 106: ...ected to the PCI_CLK signal The track length of the clock nets should be matched in length 10 2 2 2 Slave Mode Clocking In slave clocking PCI_CLKO 0 is disabled through the Clock Out Enable Function and Debug Register and an external clock source drives the PEB383 using PCI_CLK and the PCI devices a This setting is based on the value of CS_MODE in the PCI Miscellaneous Clock Straps Register ...

Page 107: ...ages during power management events The Power Management PM module connects with the Physical Layer sub block to transition the Link State into low power states when it receives a power state change request from a upstream component or when an internal event forces the link state entry into low power states in ASPM PCIe link states are not visible directly to legacy bus driver software but are der...

Page 108: ...vings even when the PEB383 is in the D0 state After a period of idle link time the ASPM function engages the physical layer protocol that places idle link in the power saving state Once in the lower power state transitions to the fully operative L0 state can be triggered by transactions from the PCIe or PCI Interface The L0 L1 entry capability of the PEB383 is determined by the Root Complex readin...

Page 109: ...L3 Ready The L2 L3 Ready state is a staging point for the L2 or L3 states The process is initiated after the PM module software transitions the PEB383 into the D3 state and requests power management software to initiate the removal of power and clocks After the PCIe link enters the L2 L3 Ready state the PEB383 is ready for power removal TLP and DLLP communication over link cannot occur while the P...

Page 110: ...s D0 Yes D0 On On On L0s Standby state No Yes D0 On On On L1 Low power standby Yes D3hot Yes On On On L2 L3 ready Stagging point for power removal Yes No On On On L3 Off N A N A Off Off Off L0s L1 L0 L2 L3 Ready L3 LDn Return to L0 through LTSSM L0s Return tp L0 through LTSSM Recovery state L2 L3 Ready Psudo state to prepare component for loss of power and ref clock Link reinitialization through L...

Page 111: ...state the device can later be transitioned into the D3Cold state by removing power from the device D3Hot is a useful state for reducing power consumption by idle components in an otherwise running system Once the PEB383 is programmed to the D3Hot state it initiates L1 entry process The NO_SOFT_RST bit in the PCI Power Management Control and Status Register is set to 1 in the PEB383 when software p...

Page 112: ...ate change The PEB383 sends a PM_PME message to the root complex during a power management event The bridge does not support a wake up function through Beacon and WAKE It does not support PME generation from the D3Cold state since the PEB383 does not support Auxiliary power A PM_PME message are posted TLP packets that are always routed in the direction of the root complex To send a PM_PME message ...

Page 113: ...onal PCIe link in standby D0 L1 D0 Operational PCIe Link in L1 D3hot L0 D3hot D0 PME onlya a The PEB383 drives PCI_CLKO 4 0 does not assert PCI_RSTn responds to PCI_PMEn does not participate in bus transactions PEB383 sending PME message when in D3hot or when injecting a PME_TO_Ack TLP when PEB383 transitions between L1 and L2 L3 ready D3hot L1 D3hot D0 PME only Power saving mode or waiting to tra...

Page 114: ...re logic clock is gated for additional power savings Mode5 is D3_hot link is in L1 and internal clock is gated Mode6 is D3_hot link in L1 internal clock is gated and external PCI_CLK 3 0 is gated Table 30 Power saving modes Input Conditions power saving activities Mode state ASPMa a ASPM enabled via ASPM_CTL bit of PCIe Link Control Register PCI_CLK 3 0 gate enableb b PCI_CLK 3 0 gating enabled vi...

Page 115: ...020A AT25040A AT25080A AT25160A AT25320A and AT25640A The primary purpose of the EEPROM Controller is to modify some of the default values of the Read only and Read Write registers in the PEB383 s CSR space for more information see Register Descriptions After reset is de asserted the Controller initiates the read instructions to the external EEPROM and reads its contents If an EEPROM is present th...

Page 116: ...es address byte enables and data is required to program one CSR register Table 31 describes the data structure to be maintained by the external EEPROM After the reset is de asserted the EEPROM Controller initiates a read of the first two locations of the external EEPROM to get the identification code The identification code must be 0x28AB Initially it initiates a read transaction with 9 bit addres...

Page 117: ... EEPROM Controller that is EEPROM locations can be written and read by the root complex The root complex initiates configuration write transactions to program the EEPROM Control Register using a write command The EEPROM Controller initiates a WREN Write Enable instruction first followed by a WRITE instruction The Controller sets the BUSY bit in the register when it initiates a write instruction to...

Page 118: ...te count 7 0 Any value 0003h Byte count 15 8 Any value but total value of Byte count 15 0 should be multiple of 6 0004h CSR register m Address 7 0 Any number 0005h CSR register m byte enable 3 0 CSR register m Address 11 8 Any number 0006h CSR register m Data 7 0 Any number 0007h CSR register m Data 15 8 Any number 0008h CSR register m Data 23 16 Any number 0009h CSR register m Data 31 24 Any numb...

Page 119: ...lock For read or write instructions in support of addresses greater than 0xFFH in 9 bit addressing mode the 8th bit of the address is transmitted in place of the third bit of the opcode of that instruction thus the address phase consists of 8 clock cycles The timing for different instructions of the EEPROM Controller are provided in the following figures Figure 31 9 bit EEPROM Read Timing FFFEh CS...

Page 120: ...tial NDA Required Figure 32 16 bit EEPROM Read Timing Figure 33 9 bit EEPROM Write Timing SR_CSn Opcode Address Data SR_CLK SR_DIN SR_DOUT High Z SR_CSn Opcode Address Data SR_CLK SR_DIN SR_DOUT High Z SR_CSn SR_CLK Opcode Address Data SR_DOUT High Z SR_DIN SR_CSn SR_CLK Opcode Address Data SR_DOUT High Z SR_DIN ...

Page 121: ...ction Timing Figure 36 EEPROM RDSR Instruction Timing SR_CSn SR_CLK Opcode Address Data SR_DOUT High Z SR_DIN SR_CSn SR_CLK Opcode Address Data SR_DOUT High Z SR_DOUT High Z SR_DIN SR_CSn SR_CLK SR_DIN SR_DOUT High Z SR_CSn SR_CLK SR_DIN SR_DOUT High Z SR_CLK SR_DIN High Z SR_CSn SR_DOUT Opcode Data SR_CLK SR_DIN High Z SR_CSn SR_DOUT Opcode Data Note RDSR means Read Status Register Instruction ...

Page 122: ...12 Serial EEPROM Functional Timing 108 PEB383 User Manual July 25 2011 Integrated Device Technology Inc Confidential NDA Required ...

Page 123: ... Scan Architecture standards There are five standard pins associated with the interface JTAG_TMS JTAG_TCK JTAG_TDI JTAG_TDO and JTAG_TRSTn that allow full control of the internal TAP Test Access Port controller The JTAG Interface has the following features Contains a 5 pin Test Access Port TAP controller with support for the following registers Instruction register IR Boundary scan register Bypass...

Page 124: ...gister The PEB383 uses an Instruction register to control the operation of the JTAG logic Bit combinations that are not equivalent to any instruction are equivalent to the BYPASS instruction 13 4 Bypass Register This register is a 1 bit shift register that provides a single bit scan path between the JTAG_TDI input and the JTAG_TDO output This abbreviated scan path is selected by the BYPASS instruc...

Page 125: ...G Interface Complete the following steps to write to a device register through the JTAG Interface 1 Move to the TAP controller Shift IR state and program the instruction register with the instruction of the DR by writing into Instruction Register bits with 0xFFFF_FFFF_FFFF_FFFD 2 Move to the Shift DR state and shift the data 31 0 R W 1 and the address 9 0 serially in the TDI pin To prevent corrupt...

Page 126: ...gh the JTAG Interface 1 Move to the TAP controller Shift IR state and program the instruction register with IRAC instruction by writing into Instruction Register bits with 0xFFFF_FFFF_FFFF_FFFD This step is optional if the instruction register is already programmed during the write cycle 2 Move to the Shift DR state and shift the R W 0 and the address 9 0 serially in the TDI pin To prevent corrupt...

Page 127: ...AP controller into a daisy chain TEST_BCE uses a pad with a built in pull up When TEST_ BCE is low the bridge s JTAG pins access only the top level TAP controller When TEST_BCE is high the daisy chain mode is selected see Figure 39 13 8 Accessing SerDes TAP Controller The SerDes has an internal TAP controller that uses IDCODE instruction for the IP identification and CRSEL instruction for writing ...

Page 128: ...13 JTAG Accessing SerDes TAP Controller 114 PEB383 User Manual July 25 2011 Integrated Device Technology Inc Confidential NDA Required ...

Page 129: ...s when the UNLOCK bit is high HwInitWO Hardware Initialized Write Once The field may be written once EEPROM or CFG and then it becomes read only Hot reset does not reset read only attribute Cold or warm reset does reset read only attribute All HwInitWO bits in the same 32 bit register must be written at the same time R W Read write R W1C Read Write 1 to clear writing a 0 has no effect These regist...

Page 130: ...y 25 2011 Integrated Device Technology Inc Confidential NDA Required ReservedP The value in this field must be preserved during a write access Undefined This value is undefined after reset because it is based on a bit setting a pin setting or a power up setting ...

Page 131: ...0x004 124 Class Code Revision ID 0x008 128 BIST Header Type Master Latency TImer CacheLine Size 0x00C 129 Base Address Register 0 Reserved 0x00000000 0x010 Base Address Register 1 Reserved 0x00000000 0x014 Secondary Latency Timer Subordinate Bus Number Secondary Bus Number Primary Bus Number 0x018 130 Secondary Status I O Limit I O Base 0x01C 131 Memory Status Memory Base 0x020 134 Prefetchable Me...

Page 132: ...extensions Reserved 0x00 PMCSR 0x0A4 164 Table 35 PCIe Capability Registers 31 0 Offset Page PCIe Capability Register Next Pointer Capability ID 0x0C0 173 Device Capability 0x0C4 175 Device Status Device Control 0x0C8 177 Link Capability 0x0CC 180 Link Status Link Control 0x0D0 182 Table 36 Advanced Error Reporting Capability Registers 31 0 Offset Page PCIe Enhanced Capability Header 0x100 188 Unc...

Page 133: ...96 0x128 196 Secondary Uncorrectable Error Status Register 0x12C 197 Secondary Uncorrectable Error Mask Register 0x130 198 Secondary Uncorrectable Error Severity Register 0x134 199 Secondary Error Capabilities and Control Register 0x138 200 Secondary Header Log Register 0x13C 200 0x140 201 0x144 202 0x148 202 Table 36 Advanced Error Reporting Capability Registers Continued 31 0 Offset Page ...

Page 134: ...PCI PFM Base and Limit Register 0x028 PCI_PFM_B_UPPER PCI PFM Base Upper 32 Address Register 0x02C PCI_PFM_L_UPPER PCI PFM Limit Upper 32 Address Register 0x030 PCI_IO_UPPER PCI I O Address Upper 16 Register 0x034 PCI_CAP PCI Capability Pointer Register 0x038 Reserved 0x03C PCI_MISC2 PCI Bridge Control and Interrupt Register 0x040 SEC_RETRY_CNT Secondary Retry Count Register 0x044 PCI_MISC_CSR PCI...

Page 135: ...ister 0x0BC PREF_CTRL Prefetch Control Register 0x0C0 PCIE_CAP PCIe Capabilities Register 0x0C4 PCIE_DEV_CAP PCIe Device Capabilities Register 0x0C8 PCIE_DEV_CSR PCIe Device Control and Status Register 0x0CC PCIE_LNK_CAP PCIe Link Capabilities Register 0x0D0 PCIE_LNK_CSR PCIe Link Control Register 0x0E4 AR_SBNPCTRL Secondary Bus Non prefetchable Address Remap Control Register 0x0E8 AR_SBNPBASE Sec...

Page 136: ...og 3 Register 0x128 PCIE_HL4 PCIe Header Log 4 Register 0x12C PCIE_SERR_STAT PCIe Secondary Uncorrectable Error Status Register 0x130 PCIE_SERR_MASK PCIe Secondary Uncorrectable Error Mask Register 0x134 PCIE_SERR_SEV PCIe Secondary Uncorrectable Error Severity Register 0x138 PCIE_ECAP_CTRL PCIe Secondary Error Capabilities and Control Register 0x13C PCIE_SEC_HL1 PCIe Secondary Header Log 1 Regist...

Page 137: ...PCI_ID Reset value 0x8113_10E3 Register offset 0x000 Bits 7 6 5 4 3 2 1 0 31 24 DID 23 16 DID 15 08 VID 07 00 VID Bits Name Description Type Reset value 31 16 DID Device ID This field indicates the silicon device identification number RWL 0x8113 15 0 VID Vendor ID This field indicates the silicon vendor identification number By default the PEB383 device reports a value of 0x10E3 indicating the ven...

Page 138: ... bad ECRC Read Completion or Write Request on the PCIe Interface regardless of the state the Parity Error Response bit in the Command register 0 Data poisoning and bad ECRC not detected by the bridge on its PCIe Interface 1 Data poisoning or bad ECRC detected by the bridge on its PCIe Interface R W1C 0 30 S_SERR Signaled System Error This bit is set when the bridge sends an ERR_FATAL or ERR_NONFAT...

Page 139: ...pplicable for PCIe It always reads 0 R 00 24 MDP_D Master Data Parity Error 0 No uncorrectable data error detected on the PCIe Interface 1 Uncorrectable data error detected on the PCIe Interface This field is set by the PEB383 if its Parity Error Response Enable bit is set and either of the following conditions occurs The PEB383 receives a Completion marked poisoned on the PCIe Interface The PEB38...

Page 140: ...field does not apply for PCIe bridges It always reads 0 R 0 06 PERESP Parity Error Response Enable This bit controls the PEB383 s setting of the Master Data Parity Error bit in the Status register in response to a received poisoned TLP from PCIe 0 Disable the setting of the Master Data Parity Error bit 1 Enable the setting of the Master Data Parity Error bit R W 0 05 VGAPS VGA Palette Snoop This f...

Page 141: ... Respond to all Memory Requests on the PCIe Interface as Unsupported Request Received Forward all memory requests from the PCI Interface to the PCIe Interface 1 Enable forwarding of memory transactions to the PCI Interface and any internal function R W 0 00 IOS I O Space Enable This bit controls the PEB383 s response as a target to I O transactions on the PCIe Interface that address a device that ...

Page 142: ...n Type Reset value 31 24 BASE Base Class This field indicates the device is a bridge R 0x06 23 16 SUB Sub Class This field indicates the device is a PCI to PCI bridge R 0x04 15 08 PROG Program Interface This field reads 0 when the LEGACY bit is clear see PCI Miscellaneous Clock Straps Register and reads 0x1 when the legacy bit is set When set to 0x1 it indicates to software that a subtractive deco...

Page 143: ...ridge R 0x01 15 08 Reserved Reserved Latency timer in PCI Interface R 0 07 00 CLINE Cacheline Sizea 04 4 x 32 bit word 16 bytes 08 8 x 32 bit word 32 bytes 10 16 x 32 bit word 64 bytes 20 32 x 32 bit word 128 bytes This field specifies the system cacheline size in units of 32 bit words It is used by the PCI master to determine the PCI read transaction that is memory read memory read line or memory...

Page 144: ...rship as a bus master on the PCI Interface 00000 PCI reset value R W Undefined 26 24 S_LTIMER_8 Set to 000 to force 8 cycle increments for the Secondary Latency Timer R 000 23 16 SUB_BUS_NUM Subordinate Bus Number The system software programs this field with the PEB383 s highest numbered downstream secondary bus number This value is used by the PEB383 to respond to Type 1 Configuration transaction...

Page 145: ...otential target Data parity error as a target of a write transaction Data parity error as a master of a read transaction 0 Device did not detect a parity error 1 Device detected a parity error R W1C 0 30 S_SERR Received System Error This bit reports the assertion of PCI_SERRn on the PCI Interface 1 PCI_SERRn was detected on the PCI Interface 0 PCI_SERRn was not detected R W1C 0 29 R_MA Received Ma...

Page 146: ...e fast back to back transactions when the transactions are from the same master but to different targets R 1 22 Reserved Reserved R 0 21 DEV66 66 MHz Capable PCI Bus This bit is hardwired to 1 indicating that the secondary bus interface can operate at a 66 MHz clock rate R 1 20 16 Reserved Reserved R 00000 15 12 IO_LA 3 0 I O Limit Address The PEB383 uses this field for I O address decoding These ...

Page 147: ...r Map 133 PEB383 User Manual July 25 2011 Integrated Device Technology Inc Confidential NDA Required 03 00 ADD_CAP2 Addressing Capability The PEB383 supports 32 bit I O addressing R 0x1 Continued Bits Name Description Type Reset value ...

Page 148: ...This field is used in conjunction with the Memory Base Address for forwarding memory mapped I O transactions These bits define the upper bound for the memory address range The upper 12 bits correspond to address bits 31 20 of the address range Bits 19 0 of the address range are 0xFFFFF R W 0 19 16 Reserved Reserved R 0 15 04 BA Memory Base Address This field defines the lower bound of the address ...

Page 149: ...ding memory mapped I O transactions These bits define the upper bound for the memory address range The upper 12 bits correspond to address bits 31 20 of the address range Bits 19 0 of the address range are 0xFFFFF R W 0 19 16 ADD_LA_64 Addressing Capability Memory Base Address The PEB383 supports 64 bit addressing R 0x1 15 04 BA Prefetchable Memory Base Address This field defines the lower bound o...

Page 150: ...n conjunction with BA in the PCI PFM Base and Limit Register to specify the lower bound of the 64 bit prefetchable address range The 32 bits relate to address bits 63 32 of the Prefetchable Base Address bits R W 0x0 Register name PCI_PFM_L_UPPER Reset value 0x0000_0000 Register offset 0x02C Bits 7 6 5 4 3 2 1 0 31 24 LA 23 16 LA 15 08 LA 07 00 LA Bits Name Description Type Reset value 31 00 LA Pre...

Page 151: ...onjunction with IO_LA in the PCI Secondary Status and I O Limit and Base Register to define the upper bound 32 bit address range used for decoding I O transactions from the PCIe Interface to the PCI Interface These bits relate to address bits 31 16 of I O Limit Address R W 0x0000 15 00 IO_BA I O Base Address Upper 16 bits This field is used in conjunction with IO_BA in the PCI Secondary Status and...

Page 152: ...x0000_00A0 Register offset 0x034 Bits 7 6 5 4 3 2 1 0 31 24 Reserved 23 16 Reserved 15 08 Reserved 07 00 CAP_PTR Bits Name Description Type Reset value 31 08 Reserved Reserved R 0x0 07 00 CAP_PTR Capabilities Pointer By default the next capability pointer is 0xA0 PCI Power Management Capability Register If it is desired to link in SSID Capability Register then this value should be changed to 0x60 ...

Page 153: ...saction on the PCIe Interface when the Secondary Discard Timer expires and a Delayed Transaction is discarded from a queue in the bridge The severity is selectable only if Advanced Error Reporting is supported 0 Do not generate ERR_NONFATAL or ERR_FATAL on the PCIe Interface as a result of the expiration of the Secondary Discard Timer Note that an error message can still be sent if Advanced Error ...

Page 154: ...counts 215 PCI clock cycles 1 Secondary Discard Timer counts 210 PCI clock cycles R W 0 24 DISCARD1 Primary Discard Timer This bit does not apply to PCIe It always reads 0 R 0 23 S_FPTP_EN Fast Back to Back Enable The PEB383 cannot generate fast back to back transactions as a master on the PCI Interface R 0 22 S_RESET Secondary Bus Reset This bit forces the assertion of PCI_RST on the PCI Interfac...

Page 155: ...aken that is all data is discarded 1 Report UR Completions from PCIe by signaling Target Abort on the PCI Interface when the PCI Interface is operating in PCI mode For posted transactions initiated from the PCIe Interface and Master Aborted on the PCI Interface the bridge must return an ERR_NONFATAL by default or ERR_FATAL transaction provided the SERR Enable bit is set in the Command register The...

Page 156: ...nd is not used in the decoding If this bit is set the forwarding of VGA addresses is independent of the following The value of the ISA Enable bit The I O address range and memory address ranges defined by the I O Base and Limit registers the Memory Base and Limit registers and the Prefetchable Memory Base and Limit registers of the bridge The forwarding of VGA addresses is qualified by the I O Ena...

Page 157: ...he address range defined by the I O Base and Limit registers that are in the first 64 KB of PCI I O address space top 768 bytes of each 1 KB block R W 0 17 SERR_EN SERR Enable This bit controls the forwarding of PCI SERR assertions to the PCIe Interface The PEB383 transmits an ERR_FATAL or ERR_NONFATAL cycle on the PCIe Interface when PCI_SERRn is asserted on the PCI Interface This bit is set when...

Page 158: ...ion Note A bridge must generate parity or ECC if applicable even if parity error reporting is disabled Also a bridge must always forward data with poisoning from PCI to PCIe on an uncorrectable PCI data error regardless of the setting of this bit 0 Ignore uncorrectable address attribute and data errors on the PCI Interface 1 Enable uncorrectable address attribute and data error detection and repor...

Page 159: ...fault R W 0 23 21 Reserved Reserved R 0 20 ARB External arbiter control 0b0 disable external arbiter 0b1 enable external arbiter HwInitWO 0 19 17 Reserved Reserved R 0 16 PARK PARK bus parking policy 0b0 park on last served device 0b1 park on the bridge HwInitWO 0 15 14 DTL0 Delayed Transaction Limit for PCI Device 3 0b01 max one delayed transaction for device 3 0b10 max two delayed transaction fo...

Page 160: ...action for device 0 0b10 max two delayed transaction for device 0 0b11 max three delayed transaction for device 0 0b00 max four delayed transaction for device 0 R W 0b10 7 4 Reserved Reserved R 0 3 0 SEC_RT_CNT This field defines the number of retries that the PEB383 will receive on the secondary bus for a requested transaction before its internal retry counter expires When the counter expires the...

Page 161: ... 0 R W 1 29 EN_ARB3 Enable Arbiter 3 0 PEB383 disables PCI_REQ3n for arbitration 1 The bridge enables PCI_REQ3n for arbitration R W 1 28 EN_ARB2 Enable Arbiter 2 0 PEB383 disables PCI_REQ2 for arbitration 1 PEB383 enables PCI_REQ2 for arbitration R W 1 27 EN_ARB1 Enable Arbiter 1 0 PEB383 disables PCI_REQ1 for arbitration 1 PEB383 enables PCI_REQ1 for arbitration R W 1 26 EN_ARB0 Enable Arbiter 0 ...

Page 162: ... ARB_PRI2 Arbiter Priority 2 0 PEB383 assigns low priority to PCI_REQ2 1 PEB383 assigns high priority to PCI_REQ2 R W 0 17 ARB_PRI1 Arbiter Priority 1 0 PEB383 assigns low priority to PCI_REQ1 1 PEB383 assigns high priority to PCI_REQ1 R W 0 16 ARB_PRI0 Arbiter Priority 0 0 PEB383 assigns low priority to PCI_REQ0 1 PEB383 assigns high priority to PCI_REQ0 R W 0 15 Reserved Reserved R 0 14 11 CPL_I...

Page 163: ...r The PEB383 returns the Completion with CRS completion status for the received Type 1 configuration requests if this timer is expired before receiving the Completion from the targeted secondary device 000 25 us 001 40 us 010 50 us 011 100 us 100 200 us 101 500 us 110 1 ms 111 10 ms R W 001 07 00 Reserved Reserved R 0x00 Continued Bits Name Description Type Reset value ...

Page 164: ...33 66 nominal PCI_CLKO Note For normal operation leave this bit in its default state R W 1 7 LEGACY Legacy Mode When set to 1 the PEB383 operates in legacy mode for more information see Legacy Mode R W 0 6 5 Reserved Reserved R 0 4 PCGE PCI clock gate enable 0b0 PCI_CLK 3 0 clock gating disabled 0b1 PCI_CLK 3 0 clock gating enabled when in D3_hot and in 33MHZ mode In addition the bits BPCCE and B2...

Page 165: ... Inc Confidential NDA Required 2 0 CS_MODE Clock Speed Mode This field defines the clock speed when OP_MODE is set to 1 according to the following code points 0bX00 25 MHz PCI mode 0bX01 33 MHz PCI mode 0bX10 50 MHz PCI mode 0bX11 66 MHz PCI mode R W 000 Continued Bits Name Description Type Reset value ...

Page 166: ...on that a single upstream non posted read request will create The amount of completion buffer allocated is the MIN of these bits and the read request 11 1024 bytes 10 512 bytes 01 256 bytes 00 256 bytes R W 11 7 5 Reserved Reserved R 0 4 0 UPST_PWR_THRES This field defines the threshold for the upstream posted writes and indicates the length of posted write data to be accumulated in the upstream p...

Page 167: ... 31 CPL_TO_EN Completion Timeout Enable This bit enables disables the Completion Timeout function The PEB383 handles an upstream non posted request as if completion is returned with UR if the completion is not returned before its Completion Timeout Timer is expired 0 Disable Completion Timeout Timer 1 Enable Completion Timeout Timer R W 1 30 00 CPL_TO_VALUE Completion Timeout Value This 31 bit reg...

Page 168: ...upplied to the PCI secondary devices CLKOUT_ENB 0 0 Disable PCI_CLK_OUT 0 1 Enable PCI_CLK_OUT 0 CLKOUT_ENB 1 0 Disable PCI_CLK_OUT 1 1 Enable PCI_CLK_OUT 1 CLKOUT_ENB 2 0 Disable PCI_CLK_OUT 2 1 Enable PCI_CLK_OUT 2 CLKOUT_ENB 3 0 Disable PCI_CLK_OUT 3 1 Enable PCI_CLK_OUT 3 CLKOUT_ENB 4 0 Disable PCI_CLK_OUT 4 1 Enable PCI_CLK_OUT 4 R W 11111 07 02 Reserved Reserved R 0 01 UNLOCK Setting this bi...

Page 169: ...ed ST_DIST_ EN Reserved SEC_DIST _EN 07 00 Reserved Bits Name Description Type Reset value 31 11 Reserved Reserved R 0 10 ST_DIST_EN Short Term Discard Timer Enable 0 Secondary discard timer value sets to either 0x03FF 1K PCI clock cycles or 0x7FFF 32 K PCI clock cycles 1 Secondary discard timer value sets to 0x003F 64 PCI clock cycles R W 0 9 Reserved Reserved R 0 8 SEC_DIST_EN Secondary Discard ...

Page 170: ...on transparent address range are mapped to different address locations according to following device specific registers 14 4 1 NTMA Control Register Register name NTMA_CTRL Reset value 0x0000_0000 Register offset 0x068 Bits 7 6 5 4 3 2 1 0 31 24 NTMA_LBA 23 16 NTMA_LBA Reserved 15 08 Reserved 07 00 Reserved NTMA_ RMP Reserved Bits Name Description Type Reset value 31 20 NTMA_LBA NTMA primary lower...

Page 171: ... 0x0000_0000 Register offset 0x06C Bits 7 6 5 4 3 2 1 0 31 24 NTMA_UBA 23 16 NTMA_UBA 15 08 NTMA_UBA 07 00 NTMA_UBA Bits Name Description Type Reset value 31 00 NTMA_UBA NTMA Primary upper base address R W 0x0 Register name NTMA_SEC_LBASE Reset value 0x0000_0000 Register offset 0x070 Bits 7 6 5 4 3 2 1 0 31 24 NTMA_LBA 23 16 NTMA_LBA Reserved 15 08 Reserved 07 00 Reserved Bits Name Description Typ...

Page 172: ...0000_0000 Register offset 0x074 Bits 7 6 5 4 3 2 1 0 31 24 NTMA_UBA 23 16 NTMA_UBA 15 08 NTMA_UBA 07 00 NTMA_UBA Bits Name Description Type Reset value 31 00 NTMA_UBA NTMA Secondary upper base address R W 0x0 Register name NTMA_SEC_LOWER_LIMIT Reset value 0x0000_0000 Register offset 0x078 Bits 7 6 5 4 3 2 1 0 31 24 NTMA_LLA 23 16 NTMA_LLA Reserved 15 08 Reserved 07 00 Reserved Bits Name Descriptio...

Page 173: ...ides a mechanism for add in card vendors to distinguish their add in cards from one another even though the add in cards may have the same PCI bridge on them and therefore the same Vendor ID and Device ID Values in this register must be loaded and valid prior to system software accessing the PCI configuration space Note that by default the SSID capability is not linked in via PCI Capability Pointe...

Page 174: ...gister name SSID_CAP Reset value 0x0000_A00D Register offset 0x060 Bits 7 6 5 4 3 2 1 0 31 24 Reserved 23 16 Reserved 15 08 CAP_PTR 07 00 CAP_ID Bits Name Description Type Reset value 31 16 Reserved Reserved R 0x0 15 08 CAP_PTR Capabilities Pointer This register contains the head pointer for the capability list in PCI configuration space R 0xA0 07 00 CAP_ID Capability ID R 0x0D ...

Page 175: ...tten by EEPROM Register name SSID_ID Reset value 0x0000_0000 Register offset 0x064 Bits 7 6 5 4 3 2 1 0 31 24 SSID 23 16 SSID 15 08 SSVID 07 00 SSVID Bits Name Description Type Reset value 31 16 SSID Sub System ID This value identifies the add in card or subsystem and is assigned by the vendor RWL 0 15 0 SSVID Sub System vendor ID This value identifies the manufacturer of the add in card or subsys...

Page 176: ...l EEPROM programming that indicates how auxiliary power is routed to the PEB383 device in the system Given the right power supplies the PEB383 can assert the PME signals in D3COLD In the absence of Serial EEPROM information the PEB383 will report PME support for power levels down to D3HOT RWL 01111 26 D2_SP D2 Support This field always returns 0 since the PEB383 does not support the D2 power manag...

Page 177: ...agement Interface Specification Revision 1 2 R 011 15 8 NXT_PTR Next Pointer This field points to the next capability option PCIe Capabilities Register 0x0C0 Note This read only value will be changed to 0x00 when the LEGACY bit is set to 1 in the PCI Miscellaneous Clock Straps Register R 0xC0 7 0 CAP_ID Capability ID This field contains the value 0x01 indicating a power management capability optio...

Page 178: ...e bus power clock control policies defined in Section 4 7 1 have been disabled When the Bus Power Clock Control mechanism is disabled the bridge s PMCSR PowerState field cannot be used by the system software to control the power or clock of the bridge s secondary bus This bit will be set if PCGE is set in PCI Miscellaneous Clock Straps Register and the PCI_CLK is 33MHz or less R 0x0 22 B2B3S B2_B3...

Page 179: ...s field always returns 0 since the PEB383 device does not support the DATA field R 0x0 8 PME_EN Power PME Enable This field enables PME assertion The initial value of this field depends on whether the device woke from power off or D3COLD From power off this field starts disabled From D3COLD this field contains the enable condition going into the D3COLD state 0 Disable PME generation 1 Enable PME g...

Page 180: ...OM device is present 00 No EEPROM 01 9 bit address 10 16 bit address Note A blank EEPROM is indicated with 0b00 If this occurs these bits must be written with the appropriate values before the EEPROM can be accessed R W Undefined 25 BUSY This bit indicates the serial EEPROM is busy with Read Write operation Software must poll this bit before initiating a write read to the external EEPROM through a...

Page 181: ... DEVMSK_4 Reserved DEVMSK_1 Reserved 15 08 Reserved 07 00 Reserved Bits Name Description Type Reset Value 31 30 Reserved Reserved R 0 29 DEVMSK_13 Device Mask 13 0 Rerouting disabled for device 13 1 Block assertion of PCI_AD Pin 29 for configuration transactions to device 13 assert pin PCI_AD Pin 31 instead R W 0 28 26 Reserved Reserved Masking for devices 12 11 and 10 is not implemented Operation...

Page 182: ... pin PCI_AD Pin 31 instead R W 0 20 DEVMSK_4 Device Mask 4 0 Rerouting disabled for device 4 1 Block assertion of PCI_AD Pin 20 for configuration transactions to device 4 assert pin PCI_AD Pin 31 instead R W 0 19 18 Reserved Reserved Masking for devices 3 and 2 is not implemented Operation of the PEB383 is unaffected by the value of these bits R 0 17 DEVMSK_1 Device Mask 1 0 Rerouting disabled for...

Page 183: ...Period Register Register name STERM_CACHING_PERIOD Reset value 0x0000_0040 Register offset 0x0B4 Bits 7 6 5 4 3 2 1 0 31 24 ST_CACHE 23 16 ST_CACHE 15 08 ST_CACHE 07 00 ST_CACHE Bits Name Description Type Reset value 31 00 ST_CACHE Short Term caching period This field indicates the number of PCI clock cycles allowed before short term caching is discarded R W 0x0000_ 0040 ...

Page 184: ..._DIS_ STAT Reserved SEC_R_ STAT Bits Name Description Type Reset value 31 03 Reserved Reserved R 0x0 2 SEC_DIS_STAT Secondary Discard Timer status For more information on this timer see DISCARD2 in PCI Bridge Control and Interrupt Register 0 Secondary discard timer has not expired 1 Secondary discard timer has expired R 0 1 Reserved Reserved R 0 0 SEC_R_STAT Secondary Retry timer status For more i...

Page 185: ... for memory read command R W 0 25 P_MRL 0 The PEB383 prefetches one cacheline of data 1 The PEB383 prefetches as per the value specified in MRL_66 MRL_33 fields on behalf of the PCI master for memory read line command R W 1 24 P_MRM 0 The PEB383 prefetches two cachelines of data 1 The PEB383 prefetches as per the value specified in MRM_66 MRM_33 fields on behalf of PCI master for memory read multi...

Page 186: ...hreshold parameter for Memory read multiple command in 66 MHz PCI mode Unit is 64 byte chunk 6 h00 64 bytes 6 h01 128 bytes 6 h3F 4096 bytes R W 0x01 5 0 MRM_33 This bit indicates the threshold parameter for Memory read multiple command in 33 MHz PCI mode Unit is 64 byte chunk 6 h00 64 bytes 6 h01 128 bytes 6 h3F 4096 bytes R W 0x01 Continued Bits Name Description Type Reset value ...

Page 187: ...its 7 6 5 4 3 2 1 0 31 24 Reserved INT_MN SLOT_IMP 23 16 DP_TYPE CAP_VER 15 08 NXT_PTR 07 00 CAP_ID Bits Name Description Type Reset value 31 30 Reserved PCIe Reserved It always reads 0 R 00 29 25 INT_MN PCIe Interrupt Message Number The PEB383 device does not have slot status or root port status It always reads 0 R 00000 24 SLOT_IMP PCIe Slot Implemented This field is not applicable for a bridge ...

Page 188: ...s 174 PEB383 User Manual July 25 2011 Integrated Device Technology Inc Confidential NDA Required 07 00 CAP_ID Capability ID This field contains the value 0x10 indicating a PCIe capability option R 0x10 Continued Bits Name Description Type Reset value ...

Page 189: ...0 001x This value is set by the Set_Slot_Power_Limit Message The default value is 00 R 00 25 18 PL_VAL PCIe Captured Slot Power Limit Value In combination with the Slot Power Limit Scale value this field specifies the upper limit on power supplied by the slot Power limit in Watts calculated by multiplying the value in this field by the value in the Slot Power Limit Scale field This value is set by...

Page 190: ...eptable latency for transition from L1 to L0 state This field is set to 0b000 since the PEB383 is not an endpoint R 000 8 6 L0S_LAT PCIe Endpoint L0s Acceptable Latency This field indicates the acceptable latency for transition from L0s to L0 state This field is set to 0b000 since the PEB383 is not an endpoint R 000 5 EXT_TAG PCIe Extended Tag Field Supported This field contains the value 0 indica...

Page 191: ...Reset value 31 22 Reserved PCIe Reserved It always reads 0 R 0x000 21 TRAN_PND PCIe Transaction Pending This field indicates the PEB383 issued Non Posted Requests that have not been completed 0 No pending completion of Non Posted Requests 1 Pending completion of Non Posted Requests R 0 20 AUX_PWR_DTD PCIe Aux Power Detected This field indicates whether the PEB383 detected AUX power The PEB383 howe...

Page 192: ...try Status CRS in response to Configuration Requests to the target devices below the bridge R W 0 14 12 MAX_RD_SIZE PCIe Max Read Request Size This field sets the maximum read request size for the PEB383 as a requestor 000 128 bytes 001 256 bytes 010 512 bytes 011 1024 bytes 100 2048 bytes 101 4096 bytes 110 111 Reserved R W 010 11 EN_SNP_NREQ PCIe Enable Snoop Not Required The PEB383 does not set...

Page 193: ...est Reporting Enable This field controls reporting of unsupported requests 0 No error reporting 1 Error reporting enabled R W 0 2 FTL_ERR_EN PCIe Fatal Error Reporting Enable This bit in conjunction with other bits controls sending ERR_FATAL messages for more information see Figure 22 0 No error reporting 1 Error reporting enabled R W 0 1 NFTL_ERR_EN PCIe Non Fatal Error Reporting Enable This bit ...

Page 194: ...0 20 DLL_LNK_ACT_ REP_CAP Data Link Layer Link Active Reporting Capable For a downstream port this bit must be set to 1 if the component can report the DL_Active state of the Data Link Control and Management State Machine For a hot plug capable downstream port this bit must be set to 1 For upstream ports and components that do not support this capability this bit must be hardwired to 0 Note The PE...

Page 195: ... 1 in this bit Note The PEB383 does not support CLK_PWR_MGT This field always reads 0 R 0 17 15 L1_EXIT PCIe L1 Exit Latency L1 exit latency is between 2 and 4 us RWL 010 14 12 L0S_EXIT PCIe L0s Exit Latency The PEB383 L0s exit latency will be as 256 512ns which will be reported as 0b011 This value can be overwritten by the serial EEPROM 000 Less than 64 ns 001 64 ns to less than 128 ns 010 128 ns...

Page 196: ...State Machine This bit is hardwired to 0 R 0 28 SLT_CLK_CONFIG Slot Clock Configuration This bit indicates the PEB383 uses the same physical reference clock that the platform provides on the connector This bit can be loaded from the serial EEPROM as part of the PCB configuration information R 0 27 26 Reserved Reserved R 0 25 20 NEG_LNK_WIDTH Negotiated Link Width This field indicates the negotiate...

Page 197: ...tencies 0 Asynchronous reference clock 1 Distributed common reference clock R W 0 5 RETRAIN PCIe Retrain Link This field is reserved for a bridge device It always reads 0 R 0 4 LNK_DIS PCIe Link Disable This field is reserved for a bridge device It always reads 0 R 0 3 RCB PCIe Read Completion Boundary This field is set by system software to indicate the read completion boundary value of the upstr...

Page 198: ...t value 0x0000_0000 Register offset 0x0E4 Bits 7 6 5 4 3 2 1 0 31 24 SEC_NP_LBASE 23 16 SEC_NP_LBASE Reserved 15 08 Reserved IO_SIZE 07 00 Reserved NP_REMA PP_EN Reserved Bits Name Description Type Reset value 31 20 SEC_NP_LBASE Secondary non prefetchable lower base R W 0x000 19 13 Reserved Reserved R 0x00 12 8 IO_SIZE This field describes how many upper bits of a downstream I O address are discar...

Page 199: ...A 23 16 SEC_NP_UBA 15 08 SEC_NP_UBA 07 00 SEC_NP_UBA Bits Name Description Type Reset value 31 00 SEC_NP_UBA Secondary bus non prefetchable upper base R W 0x000 Register name AR_SBPPRECTRL Reset value 0x0000_0000 Register offset 0x0EC Bits 7 6 5 4 3 2 1 0 31 24 SEC_PRE_LBA 23 16 SEC_PRE_LBA Reserved 15 08 Reserved 07 00 Reserved PRE_REM AP_EN Reserved Bits Name Description Type Reset value 31 20 S...

Page 200: ...BASEUPPER Reset value 0x0000_0000 Register offset 0x0F0 Bits 7 6 5 4 3 2 1 0 31 24 SEC_PRE_UBA 23 16 SEC_PRE_UBA 15 08 SEC_PRE_UBA 07 00 SEC_PRE_UBA Bits Name Description Type Reset value 31 00 SEC_PRE_UBA Secondary bus non prefetchable upper base R W 0x000 Register name AR_PBNPBASEUPPER Reset value 0x0000_0000 Register offset 0x0F4 Bits 7 6 5 4 3 2 1 0 31 24 PRI_NP_UBA 23 16 PRI_NP_UBA 15 08 PRI_...

Page 201: ...ial NDA Required 14 7 6 Primary Bus Non prefetchable Upper Limit Remap Register Register name AR_PBNPLIMITUPPER Reset value 0x0000_0000 Register offset 0x0F8 Bits 7 6 5 4 3 2 1 0 31 24 PRI_NP_ULA 23 16 PRI_NP_ULA 15 08 PRI_NP_ULA 07 00 PRI_NP_ULA Bits Name Description Type Reset value 31 00 PRI_NP_ULA Primary bus non prefetchable upper Limit R W 0x0000_000 0 ...

Page 202: ...scription Type Reset value 31 20 NXT_CAP_OFF Next Capability Offset This field contains the offset to the next PCIe capability structure or 0x000 if no other items exist in the linked list of capabilities For Extended Capabilities implemented in device configuration space this offset is relative to the beginning of PCI compatible configuration space and thus must always be either 0x000 for termina...

Page 203: ...rved DLPE Reserved Undefined Bits Name Description Type Reset value 31 21 Reserved Reserved R 0x000 20 UR Unsupported Request Error Status R W1CS 0 19 ECRC ECRC Error Status R W1CS 0 18 MAL_TLP Malformed TLP Status R W1CS 0 17 RXO Receiver Overflow Status R W1CS 0 16 UXC Unexpected Completion Status R W1CS 0 15 CA Completer Abort Status R W1CS 0 14 CTO Completion Timeout Status R W1CS 0 13 FCPE Fl...

Page 204: ...eserved 07 00 Reserved DLPE Reserved Undefined Bits Name Description Type Reset value 31 21 Reserved Reserved R 0x000 20 UR Unsupported Request Error Mask R WS 0 19 ECRC ECRC Error Mask R WS 0 18 MAL_TLP Malformed TLP Mask R WS 0 17 RXO Receiver Overflow Mask R WS 0 16 UXC Unexpected Completion Mask R WS 0 15 CA Completer Abort Mask R WS 0 14 CTO Completion Timeout Mask R WS 0 13 FCPE Flow Control...

Page 205: ...C ECRC Error Severity R WS 0 18 MAL_TLP Malformed TLP Severity R WS 1 17 RXO Receiver Overflow Severity R WS 1 16 UXC Unexpected Completion Severity Note In the PCI Express Base Specification Revision 1 1 Unexpected Completions are only reported as correctable errors this bit should not be set to 1 R WS 0 15 CA Completer Abort Severity R WS 0 14 CTO Completion Timeout Severity R WS 0 13 FCPE Flow ...

Page 206: ... Reserved Reserved R 0x00000 13 ANFE Advisory Non Fatal Error Status R W1CS 0 12 RT_TO Replay Timer Timeout Status R W1CS 0 11 9 Reserved Reserved R 000 8 RN_RO REPLAY_NUM Rollover Status R W1CS 0 7 B_DLLP Bad DLLP Status This bit is set to indicate the following conditions Calculated CRC was not equal to received CRC R W1CS 0 6 B_TLP Bad TLP Status This bit is set to indicate the following condit...

Page 207: ... 0x114 Bits 7 6 5 4 3 2 1 0 31 24 Reserved 23 16 Reserved 15 08 Reserved ANFE RT_TO Reserved RN_RO 07 00 B_DLLP B_TLP Reserved RXE Bits Name Description Type Reset value 31 14 Reserved Reserved R 0x00000 13 ANFE Advisory Non Fatal Error Mask R WS 1 12 RT_TO Replay Timer Timeout Mask R WS 0 11 9 Reserved Reserved R 000 8 RN_RO REPLAY_NUM Rollover Mask R WS 0 7 B_DLLP Bad DLLP Mask R WS 0 6 B_TLP Ba...

Page 208: ...erved EC_EN 07 00 EC_CAP EG_EN EG_CAP ERR_PTR Bits Name Description Type Reset value 31 9 Reserved Reserved R 0x0000_00 8 EC_EN ECRC Check Enable 0 Disable 1 Enable R WS 0 7 EC_CAP ECRC Check Capable This bit indicates the PEB383 can check ECRC R 1 6 EG_EN ECRC Generation Enable 0 Disable 1 Enable R WS 0 5 EG_CAP ECRC Generation Capable This bit indicates the PEB383 can generate ECRC R 1 4 0 ERR_P...

Page 209: ...ster offset 0x11C Bits 7 6 5 4 3 2 1 0 31 24 HEADER 127 120 23 16 HEADER 119 112 15 08 HEADER 111 104 07 00 HEADER 103 96 Bits Name Description Type Reset value 31 00 HEADER 127 96 Header of TLP associated with error RS 0 Register name PCIE_HL2 Reset value 0x0000_0000 Register offset 0x120 Bits 7 6 5 4 3 2 1 0 31 24 HEADER 95 88 23 16 HEADER 87 80 15 08 HEADER 79 72 07 00 HEADER 71 64 Bits Name De...

Page 210: ... Register offset 0x124 Bits 7 6 5 4 3 2 1 0 31 24 HEADER 63 56 23 16 HEADER 55 48 15 08 HEADER 47 40 07 00 HEADER 39 32 Bits Name Description Type Reset value 31 00 HEADER 63 32 Header of TLP associated with error RS 0 Register name PCIE_HL4 Reset value 0x0000_0000 Register offset 0x128 Bits 7 6 5 4 3 2 1 0 31 24 HEADER 31 24 23 16 HEADER 23 16 15 08 HEADER 15 08 07 00 HEADER 07 00 Bits Name Descr...

Page 211: ... PEB383 never sets this bit R 0 12 SERR_AD SERR Assertion Detected No Header Log R W1CS 0 11 PERR_AD PERR Assertion Detected R W1CS 0 10 DTDTE Delayed Transaction Discard Timer Expired Status No Header Log R W1CS 0 9 UADD_ERR Uncorrectable Address Error Status R W1CS 0 8 UATT_ERR Uncorrectable Attribute Error Status R W1CS 0 7 UDERR Uncorrectable Data Error Status R W1CS 0 6 USCM Uncorrectable Spl...

Page 212: ...ror Mask No Header Log R WS 0 12 SERR_AD SERR Assertion Detected Mask No Header Log R WS 1 11 PERR_AD PERR Assertion Detected Mask R WS 0 10 DTDTE Delayed Transaction Discard Timer Expired Mask No Header Log R WS 1 9 UADD_ERR Uncorrectable Address Error Mask R WS 1 8 UATT_ERR Uncorrectable Attribute Error Mask R WS 1 7 UDERR Uncorrectable Data Error Mask R WS 1 6 USCM Uncorrectable Split Completio...

Page 213: ...Log R WS 0 12 SERR_AD SERR Assertion Detected Severity No Header Log R WS 1 11 PERR_AD PERR Assertion Detected Severity R WS 0 10 DTDTE Delayed Transaction Discard Timer Expired Severity No Header Log R WS 0 9 UADD_ERR Uncorrectable Address Error Severity R WS 1 8 UATT_ERR Uncorrectable Attribute Error Severity R WS 1 7 UDERR Uncorrectable Data Error Severity R WS 0 6 USCM Uncorrectable Split Comp...

Page 214: ... 1 0 31 24 Reserved 23 16 Reserved 15 08 Reserved 07 00 Reserved SUFEP Bits Name Description Type Reset value 31 05 Reserved Reserved R 0 04 00 SUFEP Secondary Uncorrectable First Error Pointer RS 0x00 Register name PCIE_SEC_HL1 Reset value 0x0000_0000 Register offset 0x13C Bits 7 6 5 4 3 2 1 0 31 24 TRAN_ATT 31 24 23 16 TRAN_ATT 23 16 15 08 TRAN_ATT 15 08 07 00 TRAN_ATT 07 00 Bits Name Descriptio...

Page 215: ...served 15 08 Reserved TRAN_CU 07 00 TRAN_CL TRAN_ATT 35 32 Bits Name Description Type Reset value 31 12 Reserved Reserved R 0 11 08 TRAN_CU Transaction Command Upper This value is transferred on C BE 3 0 during the second address phase of a DAC transaction RS 0x0 07 04 TRAN_CL Transaction Command Lower This value is transferred on C BE 3 0 during the first address phase RS 0x0 3 0 TRAN_ATT 35 32 T...

Page 216: ...lue transferred on AD 31 0 during the first and second address phases The first address phase is logged in this field and the second address is logged in PCIe Secondary Header Log 4 Register RS 0x0 Register name PCIE_SEC_HL4 Reset value 0x0000_0000 Register offset 0x148 Bits 7 6 5 4 3 2 1 0 31 24 TRAN_ADD 63 56 23 16 TRAN_ADD 55 48 15 08 TRAN_ADD 47 40 07 00 TRAN_ADD 39 32 Bits Name Description Ty...

Page 217: ...er name REPLAY_LATENCY Reset value 0x0000_0000 Register offset 0x208 Bits 7 6 5 4 3 2 1 0 31 24 Reserved 23 16 Reserved 15 08 REPLAY_L AT_EN REPLAY_LATENCY 07 00 REPLAY_LATENCY Bits Name Description Type Reset value 31 16 Reserved Reserved R 0 15 REPLAY_LAT_EN Replay Latency Enable R W 0 14 00 REPLAY_LATENCY Replay Latency timer value is overwritten by this value if REPLAY_LAT_EN is set to b1 R W ...

Page 218: ...d UPDATE_LATENCY 23 16 UPDATE_LATENCY 15 08 ACKNAK_ LAT_EN Reserved ACKNAK_LATENCY 07 00 ACKNAK_LATENCY Bits Name Description Type Reset value 31 UPDATE_LAT_EN Update Latency Enable R W 0x0 30 28 Reserved Reserved R 0 27 16 UPDATE_LATENCY Update Latency timer value is overwritten with this value if UPDATE_LAT_EN is set to b1 R W 0x009 15 ACKNAK_LAT_EN Ack Nak Latency Enable R W 0x0 14 13 Reserved ...

Page 219: ...ame N_FTS Reset value 0x0000_0020 Register offset 0x210 Bits 7 6 5 4 3 2 1 0 31 24 Reserved 23 16 Reserved 15 08 Reserved 07 00 N_FTS Bits Name Description Type Reset value 31 08 Reserved Reserved R 0x0 07 00 N_FTS This register indicates the N_FTS count value to be advertised to the other end component Note This value should fall in the L0s exit latency value range reported by the PEB383 R W 0x20...

Page 220: ...14 Register Descriptions Advanced Error Reporting Capability Registers 206 PEB383 User Manual July 25 2011 Integrated Device Technology Inc Confidential NDA Required ...

Page 221: ...the SerDes is in reset nor when the reference clock is stopped Table 38 SerDes Per lane and Clock Control and Status Register Map Offset Register Name See PCIe Per Lane Transmit and Receive Registers 0x000 PCIE_TXRX_STAT_0 PCIe Transmit and Receive Status Register 0x004 PCIE_OUT_STAT_0 PCIe Output Status and Transmit Override Register 0x008 PCIE_RX_OVRD_0 PCIe Receive and Output Override Register ...

Page 222: ...er offset 0x000 Bits 7 6 5 4 3 2 1 0 31 24 Reserved LOS_CTL Reserved 23 16 RX_EQ_VAL Reserved RX_ALIGN _EN Reserved HALF_ RATE 15 08 Reserved TX_BOOST 07 00 TX_BOOST Reserved Bits Name Description Type Reset Value 31 30 Reserved Reserved R 01 29 28 LOS_CTL LOS filtering mode control R Undefined 27 24 Reserved Reserved R Undefined 23 21 RX_EQ_VAL Receive Equalization control R 0b010 20 Reserved Res...

Page 223: ...et 0x004 Bits 7 6 5 4 3 2 1 0 31 24 OVRD Reserved TX_BOOST 23 16 TX_BOOST ReservedP 15 08 ReservedP 07 00 ReservedP LOS Reserved Bits Name Description Type Reset Value 31 OVRD Enable override of relevant bits 16 30 in this register R W 0 30 26 Reserved Reserved R W 00000 25 22 TX_BOOST Transmit Boost control Programmed boost value ratio of drive level of transition bit to non transition bit is boo...

Page 224: ...Reset Value 31 15 ReservedP Preserve state on writes R Undefined 14 OVRD_2 Enable override of relevant bits 0 13 in this register R W 0 13 12 LOS_CTL LOS filtering mode control 00 Disabled 01 10 Reserved 11 Heavy filtering The LOS signal is synchronous to the output of the prescaler Heavy filtering means 128 5 cycles of no signal for LOS to be asserted R W 01 11 8 ReservedP Preserve state on write...

Page 225: ...RIGGER_ ERR MODE 15 08 Reserved 07 00 Reserved Bits Name Description Type Reset Value 31 30 Reserved Reserved R 0 29 20 PATO Pattern for modes 3 5 Program the desired pattern in these 10 bits when using modes 3 5 Note This field returns to its reset value on reset R W 0x00 19 TRIGGER_ERR Insert a single error into a LSB Note This field returns to its reset value on reset R W 0 18 16 MODE Pattern t...

Page 226: ...If OV14 is 1 and COUNT 2 15 1 signals overflow of counter Note This bit may require two reads to get a stable value a a Read operation on this register is pipelined Two reads may be needed to get current value The value is volatile that is the value may change at any time The second read resets the counter R W Undefined 30 16 COUNT Current error count If OV14 field is active then multiply count by...

Page 227: ...L 23 16 SS_PVAL DTHR 15 08 OV14 COUNT 07 00 COUNT Bits Name Description Type Reset Value 31 28 Reserved Reserved R 0 27 17 SS_PVAL Phase value from zero referencea a Read operation on this register is pipelined Two reads may be needed to get current value The value is volatile that is the value may change at any time The second read resets the counter R W 0x000 16 DTHR Bits below the useful resolu...

Page 228: ...gister offset 0x034 Bits 7 6 5 4 3 2 1 0 31 24 Reserved 23 16 Reserved 15 08 Reserved FVAL 07 00 FVAL DTHR_F Bits Name Description Type Reset Value 31 14 Reserved Reserved R W 0 13 1 FVAL Frequency is 1 526 VAL ppm from the reference Value is a signed integer format 2 s complement Note This field may require two reads to get a stable value R W 0 0 DTHR_F Bits below the useful resolution Note This ...

Page 229: ...ts are no longer valid Register name PCIE_CTL_STAT Reset value Undefined Register offset 0x420 Bits 7 6 5 4 3 2 1 0 31 24 Reserved TX_LVL LOS_LVL 23 16 LOS_LVL ACJT_LVL 15 08 Reserved 07 00 Reserved Bits Name Description Type Reset Value 31 Reserved Reserved R 1 30 26 TX_LVL Fine Resolution setting of Tx signal level Equation Pk Pk output level without attenuation 1230 x 48 tx_lvl 2 63 5 mV Vdiff ...

Page 230: ... controls R W 0 30 26 TX_LVL Fine Resolution setting of Tx signal level Equation Pk Pk output level without attenuation 1230 x 48 tx_lvl 2 63 5 mV Vdiff pp Note TX_LVL should be set to 0x1010 which results in an output of 1Vp p For more information on available settings see Table 39 R W 0x10 25 21 LOS_LVL Loss of Signal Detector level R W 0x10 20 16 ACJT_LVL AC JTAG Receiver Comparator level This ...

Page 231: ...01101 1055 7 14 0xE 5 b01110 1065 4 15 0xF 5 b01111 1075 0 16 0x10 5 b10000 1084 7 17 0x11 5 b10001 1094 4 18 0x12 5 b10010 1104 1 19 0x13 5 b10011 1113 8 20 0x14 5 b10100 1123 5 21 0x15 5 b10101 1133 1 22 0x16 5 b10110 1142 8 23 0x17 5 b10111 1152 5 24 0x18 5 b11000 1162 2 25 0x19 5 b11001 1171 9 26 0x1A 5 b11010 1181 6 27 0x1B 5 b11011 1191 3 28 0x1C 5 b11100 1200 9 29 0x1D 5 b11101 1210 6 30 0x...

Page 232: ... PCIe and SerDes Control and Status Registers 218 PEB383 User Manual July 25 2011 Integrated Device Technology Inc Confidential NDA Required ...

Page 233: ...gs PCI Symbol Parameter Minimum Maximum Units TSTG Storage temperature 55 125 o C TC Case temperature under bias 40 120 oC Voltage with respect with ground VDD 1 05V DC core logic supply voltage 0 5 2 0 V VDD_PCIE 1 05V DC PCIe digital supply voltage 0 3 1 7 V VDDA_PLL 1 05V DC PLL analog supply voltage 0 5 2 0 V VDD_PCI 3 3V DC I O supply voltage 0 5 4 1 V VDDA_PCIE 3 3V DC PCIe analog supply vol...

Page 234: ...Interface I O voltage VDD_PCI 5 25 V Vripple1 Power Supply Ripple for Voltage Supplies VDD and VDD_PCI 100 mVpp Vripple2 Power Supply Ripple for Voltage Supplies VDD_PCIE VDDA_PCIE VDDA_PLL 50 mVpp TA Ambient temperature 0 85 o C a b a No heat sink no air flow b Higher ambient temperatures are permissible provided TJUNC is not violated For heat sink and air flow requirements for higher temperature...

Page 235: ...dge Activity Typical Power W 1 0V_A W 3 3V_A W 1 0V W 3 3V W D0 L0 Fully Active Links 0 398 0 022 0 065 0 036 0 275 D0 L0 0 Link Activity 0 225 0 022 0 065 0 031 0 108 Table 45 DC Operating Characteristics Symbol Parameter Condition Minimum Maximum Units Notes VOL_PCI PCI Output Low Voltage IOL 1500uA 0 1VDD_PCI V VOH_PCI PCI Output High Voltage IOH 500uA 0 9VDD_PCI V VOH_33 3 3 CMOS Output High V...

Page 236: ... Min Max Units Notes TF_PCI PCI Clock Frequency 25 66 MHz a a The clock frequency may not change beyond the spread spectrum limits except while device reset is asserted TC_PCI PCI Clock Cycle Time 15 40 ns a b b The minimum clock period must not be violated for any single clock cycle TCH_PCI PCI Clock High Time 6 ns TCL_PCI PCI Clock Low Time 6 ns TSR_PCI PCI Clock Slew Rate 1 6 V ns c c This slew...

Page 237: ...t after a transition See Note 2 TTX EYE Minimum TX Eye Width 0 75 UI The maximum Transmitter jitter can be derived as TTX MAX JITTER 1 TTX EYE 0 25 UI This parameter is measured with the equivalent of a zero jitter reference clock See Notes 2 and 3 TTX EYE MEDIAN to MAX JITTER Maximum time between the jitter median and maximum deviation from the median 0 125 UI Jitter is defined as the measurement...

Page 238: ...le 50 UI Minimum time a Transmitter must be in Electrical Idle Used by the Receiver to start looking for an Electrical Idle Exit after successfully receiving an Electrical Idle ordered set TTX IDLE SET to IDLE Maximum time to transition to a valid Electrical Idle after sending an Electrical Idle ordered set 20 UI After sending an Electrical Idle ordered set the Transmitter must meet all Electrical...

Page 239: ...d to D and D lines and a common mode return loss greater than or equal to 6 dB over a frequency range of 50 MHz to 1 25 GHz This input impedance requirement applies to all valid input levels the reference impedance for return loss measurements is 50 Ohms to ground for both D and D line that is as measured by a vector Network Analyzer with 50 Ohm probes see Figure 4 25 Note that the series capacito...

Page 240: ...r Manual July 25 2011 Integrated Device Technology Inc Confidential NDA Required Figure 40 Transmitter Eye Voltage and Timing Diagram1 1 This diagram is an excerpt from PCI Express Base Specification Revision 1 1 Revision 1 1 Transmitter Compliance Eye Diagrams page 225 ...

Page 241: ...YE MEDIAN to MAX JITTER Maximum time between the jitter median and maximum deviation from the median 0 3 UI Jitter is defined as the measurement variation of the crossing points VRX DIFF 0V in relation to recovered TX UI To be measured after the clock recovery function in Section 4 3 3 2 of the PCI Express Base Specification Revision 1 1 See Notes 8and 9 VRX CM ACp RMS AC Peak Common Mode Input Vo...

Page 242: ...ual to 10 dB with a differential test input signal of no less than 200 mV peak value 400mV differential peak to peak swing around ground applied to D and D lines and a common mode return loss greater than or equal to 6 dB no bias required over a frequency range of 50 MHz to 1 25 GHz This input impedance requirement applies to all valid input levels The reference impedance for the return loss measu...

Page 243: ...July 25 2011 Integrated Device Technology Inc Confidential NDA Required Figure 41 Minimum Receiver Eye Timing and Voltage Compliance Specification1 1 This diagram is an excerpt from PCI Express Base Specification Revision 1 1 Differential Receiver RX Input Specifications page 230 ...

Page 244: ...he PCIe Specification Fin_DC Reference Clock Duty Cycle 40 50 60 JCLK REF Total Phase Jitter rms 3 psrms See a a Total Permissible Phase Jitter on the Reference Clock is 3 ps rms This value is specified with assumption that the measurement is performed with a 20 GSamples s scope with more than 1 million samples The zero crossing times of each rising edges are recorded and an average Reference Cloc...

Page 245: ...CR JT_TCK Rise Time 25 ns 0 8V to 2 0V a TBSCF JT_TCK Fall Time 25 ns 2 0V to 0 8V a TSIS1 Input Setup to JT_TCK 10 ns b b See Figure 43 TBSIH1 Input Hold from JT_TCK 10 ns b TBSOV1 JT_TDO Output Valid Delay from falling edge of JT_TCK 15 ns c d c Outputs precharged to VDD33 d See Figure 44 TOF1 JT_TDO Output Float Delay from falling edge of JT_TCK 15 ns c e e A float condition occurs when the out...

Page 246: ...ins AC timing waveforms for the PEB383 Figure 43 Input Timing Measurement Waveforms PCI_CLK clock stable to de assertion of device reset 100 us Power up strapping hold from de assertion of device reset 0 ns THIZ Assertion of reset to outputs tri state 10 ns Table 51 Reset Timing Continued Symbol Parameter Min Max Units Notes CLK INPUT Valid Vtest Vtest Vtest TIS TIH Vtl Vth Vth Vtl Vmax ...

Page 247: ... Confidential NDA Required Figure 44 Output Timing Measurement Waveforms Figure 45 PCI TOV max Rising Edge AC Test Load Figure 46 PCI TOV max Falling Edge AC Test Load Vtest CLK OUTPUT FLOAT Vtrise OUTPUT DELAY RISE OUTPUT DELAY FALL Vtfall TOV TOV TOF Vtl Vth Output Test Point 10pF 25Ω Output 10pF 25Ω VCC33 Test Point ...

Page 248: ...trical Characteristics AC Timing Waveforms 234 PEB383 User Manual July 25 2011 Integrated Device Technology Inc Confidential NDA Required Figure 47 PCI TOV min AC Test Load Output Test Point 10pF 1KΩ 1KΩ VCC33 ...

Page 249: ...User Manual July 25 2011 Integrated Device Technology Inc Confidential NDA Required 16 Packaging Topics discussed include the following Pinouts and Mechanical Diagrams Thermal Characteristics Moisture Sensitivity ...

Page 250: ..._PCI PCI_PMEn 90 8 VDD JTAG_TDI 89 9 VSS VSS 88 10 PCI AD 5 VDD 87 11 PCI_AD 6 JTAG_TDO 86 12 PCI_AD 7 JTAG_TMS 85 13 PCI_CBEn 0 JTAG_TRSTn 84 14 PCI AD 8 JTAG TCK 83 15 VSS IO PCI RSTn 82 16 PCI_AD 9 PCI_CLK 81 17 PCI_AD 10 PCI_GNTn 3 80 18 PCI_AD 11 VSS_IO 79 19 PCI AD 12 VDD_PCI 78 20 PCI_AD 13 PCI_GNTn 2 77 21 VIO_PCI PCI_GNTn 1 76 22 VSS PCI_GNTn 0 75 23 VDD_PCI PCI REQn 3 74 24 PCI_AD 14 VSS...

Page 251: ...16 Packaging Pinouts and Mechanical Diagrams 237 PEB383 User Manual July 25 2011 Integrated Device Technology Inc Confidential NDA Required 16 1 2 QFP Package Drawing ...

Page 252: ...16 Packaging Pinouts and Mechanical Diagrams 238 PEB383 User Manual July 25 2011 Integrated Device Technology Inc Confidential NDA Required 16 1 2 1 QFP Package Drawing Page 2 ...

Page 253: ...16 Packaging Pinouts and Mechanical Diagrams 239 PEB383 User Manual July 25 2011 Integrated Device Technology Inc Confidential NDA Required 16 1 3 QFN Package Pinout ...

Page 254: ...16 Packaging Pinouts and Mechanical Diagrams 240 PEB383 User Manual July 25 2011 Integrated Device Technology Inc Confidential NDA Required 16 1 4 QFN Package Drawing ...

Page 255: ...16 Packaging Pinouts and Mechanical Diagrams 241 PEB383 User Manual July 25 2011 Integrated Device Technology Inc Confidential NDA Required 16 1 4 1 QFN Package Drawing Page 2 ...

Page 256: ...ay be affected Failure mechanisms and failure rate of a device has an exponential dependence on the silicon operating temperatures Therefore the control of the package and by extension the Junction temperature is essential to ensure product reliability The PEB383 is specified safe for operation when the Junction temperature is within the recommended limits as shown in Table 42 Table 52 Thermal Spe...

Page 257: ... turbulent Heat sink design and thermal characteristics Heat sink attachment method PWB size layer count and conductor thickness Influence of the heat dissipating components assembled on the PWB neighboring effects The results in Table 53 and Table 52 are based on a JEDEC Thermal Test Board configuration JESD51 9 and does not factor in the system level characteristics described above As such these...

Page 258: ...a Usage Based on above θJA data and specified conditions the Junction temperature of the PEB383 with a 0 m s airflow can be determined using the following formula TJ θJA P TAMB Where TJ is the Junction temperature P is the Power consumption TAMB is the Ambient temperature 16 3 Moisture Sensitivity The moisture sensitivity level MSL for the PEB383 is 3 ...

Page 259: ...mmercial Temp 89HPEB383ZBEM 89HPEB383ZBEM8 128 ball TQFP package Commercial Temp 89HPEB383ZAEMG 89HPEB383ZAEMG8 128 ball Green TQFP package Commercial Temp 89HPEB383ZBEMG 89HPEB383ZBEMG8 128 ball Green TQFP package Commercial Temp NN A AA A Operating Voltage Device Temp H Product Family 89 Serial Switching Product PEB PCIe Bridge 1 0V 0 1V Core Voltage Legend A Alpha Character N Numeric Character ...

Page 260: ...PEB383 User Manual July 25 2011 Integrated Device Technology Inc Confidential NDA Required 17 Ordering Information 246 ...

Page 261: ...PCIe port that points in the direction away from the root complex for example a root complex port Egress port A PCIe port that transmits a packet to another PCIe device Endpoint A type of PCIe device or mode of operation that function as requesters or completers of PCIe transactions examples include Ethernet USB and graphic devices If a PCIe port is not configured as a root complex or a switch the...

Page 262: ...t can supply it immediately This type of memory access minimizes the time required to retrieve target memory Requester PCIe The device that originates a PCIe transaction A requester can be either a root complex or an endpoint device Requester ID PCIe This value uniquely identifies the requester of a transaction It consists of a requester s bus number device number and function number Root complex ...

Page 263: ...ycle 46 Type 1 to Type 0 45 Type 1 to Type 1 45 D D state transitions 98 D0 state 97 D3cold state 97 D3hot state 97 DC and operating characteristics 221 device power states 97 device register map 120 document conventions document status 2 numeric conventions 2 symbols 2 downstream data path 22 non transparent registers 184 E ECRC error 70 EEPROM controller 101 EEPROM device 102 EEPROM image 104 er...

Page 264: ...encing 221 prefetchable memory addressing 31 prefetching algorithm 27 R recommended operating conditions 220 register map 120 requestor ID 50 reset PCI 89 PCIe 88 round robin arbitration 60 S SerDes TAP controller 113 short term caching 28 system errors 80 T TAP controller 110 target abort errors 74 TCK signal 19 TDI signal 19 TDO signal 19 thermal characteristics 242 timeout errors 79 timing wave...

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