IDT 5P49V6965, Register Descriptions And Programming Manual

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19 ©2018 Integrated Device Technology, Inc. August 30, 2018
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6E Family Register Descriptions and Programming Guide
Note: The 5P49V6975 use a pre-trimmed integrated crystal. Therefore, bits D7–D2 in registers 0x12 and 0x13 should be set to 1 to
prevent inaccuracy of the output frequencies.
PLL Pre-Divider Options
The reference presented to the fractional PLL can be either directly connected, divided by two or divided by the any value from the range
of three to 127 as set in the register Ref_Div[6:0]. The phase detector of the PLL has a maximum frequency of 150MHz, therefore the
default is to bypass the pre-divider by setting Bypss_prediv = 1 (
Table 32 ). For the functionality of Sel_prediv2 and bypss_prediv bits, see
Figure 3 . Table 31 and Table 32 explains the bit selections.
Table 29. RAM1 – 0x13: Factory Reserved Bits
Bits Default Value Name Function
D7 0
xtal_load_cap_x2[5:0]
Add 6.92pF load capacitance to X2.
D6 0 Add 3.46pF load capacitance to X2.
D5 0 Add 1.73pF load capacitance to X2.
D4 0 Add 0.86pF load capacitance to X2.
D3 0 Add 0.43pF load capacitance to X2.
D2 0 Add 0.43pF load capacitance to X2.
D1 0 PRIMSRC
The PRIMSRC (primary source) bit sets the polarity of the CLKSEL pin.
D1=0: When CLKSEL is Low, Crystal is selected. When CLKSEL is High, CLKIN input is
selected.
D1=1: When CLKSEL is Low, CLKIN input is selected. When CLKSEL is High, Crystal is
selected.
D0 0 clkok1024 Factory reserved.
Table 30. RAM1 – 0x14: Factory Reserved Bits
Bits Default Value Name Function
D7 0
xtal_reg_amp_sel[3:0] Unused Factory reserved bit.
D6 0
D5 0
D4 0
D3 0
xtal_I_sel[3:0] Unused Factory reserved bit.
D2 0
D1 0
D0 0