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ICS Advent ADIO1600 Series Product Manual Download Page 59

Chapter 9:  Specifications

Manual Number: 00650-004-5

Page 9-3

Digital I/O

(8 Bits on Main 37-Pin D Connector)

Inputs:

Logic high: 2.0 to 5.0 VDC at 20

m

A maximum.

Logic low: -0.5 to +0.8 VDC at -0.2 mA maximum.

Outputs:

Logic high: 2.4V minimum at -0.4 mA source.
Logic low: 0.5V maximum at 8.0 mA sink.

(24 Bits on Auxiliary 37-Pin D Connector)

Inputs:

Logic high: 2.0 to 5.0 VDC at 10

m

A maximum

Logic low: -0.5 to +0.8 VDC at -10

m

A maximum.

Outputs:

Logic high: 2.4V minimum at 200

m

A source.

Logic low: 0.5V maximum at 1.7 mA sink.

Interrupt Channel

Levels:

Levels 2 through 7, and 10-12, 14, and 15; jumper selectable.

Enable:

The two IRQ sources (End of Conversion, CTR2 timeout) are individually enabled via control bits in

the BASE+0 control register.  The IRQ is latched, and the state of the latch is reported in the INT

bit of the status register.  Reading to the control register clears the IRQ latch and prepares the card

to generate the next IRQ.

Programmable Timer

Type:

82C54-2 programmable interval timer.

Counters:

Three 16-bit down counters, two permanently concatenated as a pacing counter with a 1MHz

clock.  One is uncommitted but driven by the 1MHz clock or an external clock source.

Output Drive:

2.2mA at 0.45V (5 LSTTL loads).

Summary of Contents for ADIO1600 Series

Page 1: ...ADIO1600 Series Product Manual MANUAL NUMBER 00650 004 5D ...

Page 2: ...ry 2000 Manual Number 00650 004 ADIO1600 Series Product Manual Page 3 2 The column headings in Table 3 1 should be Unipolar 10V x2 jumper Bipolar 5V x2 jumper Bipolar 10V x1 jumper and Software Gain Set from left to right ...

Page 3: ...nual in our online Support Library Thank you The information in this document is provided for reference only ICS Advent does not assume any liability arising from the application or use of the information or products described herein This document may contain or reference information and products protected by copyrights or patents and does not convey any license under the patent rights of ICS Adve...

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Page 5: ...cts which are not in an as new and re saleable condition are not eligible for credit return and will be returned to the customer Limited Warranty Effective April 1 1998 all products carry a 2 year limited warranty Within two years of purchase ICS Advent will repair or replace at our option any defective product ICS Advent will service the warranty for all standard catalog products for the first tw...

Page 6: ...s made by various manufacturers in performing warranty repairs and building replacement products If ICS Advent repairs or replaces a product its warranty term is not extended ICSAdvent will normally return your replacement or repaired items via Second DayAir Overnight delivery or delivery via other carriers is available at an additional charge Limitation of Liability In no event shall ICS Advent b...

Page 7: ...y Cautions and Warnings are accented with triangular symbols The exclamation symbol is used in all cautions and warnings to help alert you to the important instructions The lightning flash symbol is used on the left hand side of a caution or a warning if the advisory relates to the presence of voltage which may be of sufficient magnitude to cause electrical shock Use caution when servicing any ele...

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Page 9: ...2 3 How to remain CE Compliant 2 3 Chapter 3 Hardware Configuration and Installation 3 1 Option Selection 3 1 Multiplexer Configuration 3 1 Unipolar Bipolar Range 3 1 External Conditioning Module Support 3 1 Input Voltage Range 3 1 Analog Output Voltage Range 3 2 Counter Timer 3 4 Clock Frequency Select 3 4 Selecting and Setting the Base Address 3 4 Selecting a Base Address 3 4 Setting the Base Ad...

Page 10: ...A D Registers 5 3 Digital I O 5 4 Analog Outputs 5 9 Counter Timer Registers 5 10 Chapter 6 A D Converter Applications 6 1 ConnectingAnalog Inputs 6 1 Comments on Noise Interference 6 1 Input Range and Resolution Specifications 6 2 Current Measurements 6 2 Measuring Large Voltages 6 2 Precautions Noise Ground Loops and Overloads 6 3 Chapter 7 Programmable Interval Timer 7 1 Operational Modes 7 1 P...

Page 11: ...dapter Assembly B 5 ADIO1600 ToAdditional Multiplexers CableAdapterAssembly B 7 Appendix C Basic Integer Variable Storage C 1 CE Declaration of Conformity 1 List of Figures Figure 2 1 ADIO1600 Block Diagram 2 4 Figure 3 1 Option Selection Map 3 3 List of Tables Table 3 1 Voltage Range 3 2 Table 3 2 Output Voltage Range 3 2 Table 3 3 Standard BaseAddressAssignments 3 5 Table 3 5 Base Address Exampl...

Page 12: ...nstallation The files contained on the master diskette may also be copied onto your hard disk To do this perform the following 1 Place the master diskette into a floppy drive 2 Change the active drive to the drive that has the master diskette installed For example if the diskette is in drive A type A 3 Type INSTALL and follow the screen prompts Files contained on the disk are stored in separate di...

Page 13: ...Be sure to pay close attention to base address selection 2 Turn off the power switch of your computer and remove the power cords from the wall outlet CAUTION Failure to remove power from the computer could result in electrical shock or damage to your computer system 3 Remove the computer cover 4 Locate an unused full length slot and remove a blank I O backplate Optionally remove a second backplate...

Page 14: ...ified by an instrumentation amplifier with a combination of switch selectable gains of 1 or 2 and software selectable gains of 1000 100 10 and 1 to provide voltage ranges of 0 005 0 01 0 05 0 1 0 5 1 5 and 10 volts bipolar and 0 01 0 1 1 and 10 volts unipolar gain switch must be set to x2 The ADIO1600 uses an industry standard 12 bit successive approximation analog to digital con verter A D with a...

Page 15: ... is extended using a ribbon cable from the side of the board to a 37 pin connector on a rear mounting bracket Counter Timer The ADIO1600 contains a type 8254 counter timer which has three 16 bit programmable down counters Counter Timer 0 is enabled by a digital input IP2 and uses either the internal 1MHz clock or an external clock of up to 10 MHZ Counter Timers 1 and 2 are concatenated and form a ...

Page 16: ...supports the Pascal calling convention such as QuickBASIC C and Pascal and sample programs Addi tionally a utility driver for use with VisualBASIC for Windows is provided How to remain CE Compliant In order for machines to remain CE compliant only CE compliant parts may be used To keep a chassis compliant it must contain only compliant cards and for cards to remain compliant they must be used in c...

Page 17: ...Manual Number 00650 004 5 Page 2 4 ADIO1600 Manual Figure 2 1 ADIO1600 Block Diagram ...

Page 18: ...he maximum voltage span in the unipolar mode is 10V In the bipolar mode inputs can be between positive and negative full scale limits In the unipolar range the JP3 Gain jumper must be in the x2 position Select the unipolar or bipolar range using jumper JP4 located in the upper right hand corner of the card near the I O connector Unipolar UNIP position Bipolar BIP position The two s complement jump...

Page 19: ...lled If the two s complement data option is enabled it will also change the DAC output data registor into the two s complement data format Analog Output Voltage Range Output voltage range is selected manually by on board switches Each analog output has a three switch group that selects the options Switch S2 is for DAC0 and S3 is for DAC1 refer to the OPTION SELECTION MAP or the A1216EST setup soft...

Page 20: ...2 JP4 Analog Input Polarity Unipolar or Bipolar JP5 DAC ADC Data Format 2 s Complement if installed Offset Binary coding if removed JP6 AT16 P Compatibility Jumper Grounds Channel 8 pin 18 Input when installed JP7 AT16 P Compatibility Jumper Grounds Channel 15 pin 11 Input when installed JP8 Selects Single Ended Differential Analog Input Must be set the same as JP9 below JP9 Selects Single Ended D...

Page 21: ...o select the base I O address 1 Check the tables in Table 3 3 for lists of standard address assignments and then check what addresses are used by any other I O peripherals that are installed in your computer Memory addressing is separate from I O addressing so there is no possible conflict with any add on memory that may be installed in your computer We urge that you carefully review the address a...

Page 22: ... 8VDEOH 7 DUG LVN DPH RQWURO 3DUDOOHO 3RUW 37 XV 0RXVH V QFKURQRXV RPPXQLFDWLRQV 20 V QFKURQRXV RPPXQLFDWLRQV 20 3URWRW SH DUG 7 DUG LVN 3DUDOOHO 3RUW 37 6 RPPXQLFDWLRQV 6 RPPXQLFDWLRQV 0 OW 3DUUDOOHO 3RUW 2 V QFKURQRXV RPPXQLFDWLRQV 20 ORSS LVN V QFKURQRXV RPPXQLFDWLRQV 20 Table 3 3 Standard Base Address Assignments ...

Page 23: ...ponding switch off if the bit is zero turn the corresponding switch on n o i t a t n e s e r p e R x e H 3 0 0 n o i t a t n e s e r p e R y r a n i B 1 1 0 0 0 X o N h c t i w S s g n i t t e S d e r i u q e R r e i l p i t l u M n o i s r e v n o C 2 1 8 4 2 1 D I h c t i w S 9 A 8 A 7 A 6 A 5 A g n i t t e S h c t i w S F F O F F O N O N O N O Table 3 5 Base Address Example Using the Setup Prog...

Page 24: ...performed using the ADIO1600 setup program A1216EST EXE on the diskette supplied with your card This program will lead you through the set up and calibration procedure with prompts and graphic displays that show the settings and adjustment trim pots This calibration program also serves as a useful test of the ADIO1600 A D and D A functions and can aid in troubleshooting if problems arise Calibrati...

Page 25: ...ine square saw triangle SAMPLE 3 Direct Register CTR sample displays countdowns on each counter SAMPLE 4 Digital I O using all 8 input bits OP0 OP3 converted to inputs SAMPLE 5 Direct Register A D using counters for start conversions SAMPLE 6 Direct Register A D using External Trig IP0 for start conversions SAMPLE 7 Similar to Sample 5 but using IRQs for end of conversion detection SAMPLE 8 Auxili...

Page 26: ... routines to access a specific A D card type All of the CDM s provide the same functionality eliminating most card specific software design issues These driv ers are provided in the form of OBJ object files that can be linked to any language that supports the Pascal calling convention QuickBASIC VisualBASIC C C Fortran Assembler and Pascal just to name a few Each object file is named the same as t...

Page 27: ...he number of tries remaining before timeout occurs unsigned integer RETRIEVEANALOGCONVERSION unsigned int BASE_ADDRESS Returns a two byte unsigned number that indicates the value of the A D data register This value represents the digital value of the most recently completed analog to digital conversion This routine does not wait for EOC Therefore if you use STARTCONVERSION followed immediately by ...

Page 28: ...avoid changing the channel when only the gain is meant to change the current channel is stored in an external variable CURCH The contents of this variable are combined if required with the desired gain to produce the actual command byte s The contents of CURCH depend upon SETCHANNEL being used to set the channel Otherwise your program must set CURCH directly prior to calling SETGAIN unsigned integ...

Page 29: ...ill use InputStringOfData ASM instructions to acquire data from a FIFO or RAM equipped card in the background at a programmed rate Using the CDM Driver The CDM driver is straightforward to use and varies little even across languages Each CDM is an Object file and has several include files associated with it The C and C include files are called ACCES H and ADCARD H The Pascal Interface files are ca...

Page 30: ...ovide simple access to the full functionality of that MDM s specific sub multiplexer These drivers are provided in the form of OBJ object files that can be linked to any language that supports the Pascal calling convention QuickBASIC VisualBASIC C C Fortran Assembler and Pascal just to name a few Each object file is named the same as the sub multiplexer s six character model number The MDM file is...

Page 31: ...astChannel FirstChannel 1 elements of two byte unsigned integer data This routine performs very little error checking and is designed as a primitive function to acquire data as fast as possible using programmed I O The above are the only functions common to all Multiplexer Driver Modules Although it s pos sible to program for any multiplexer using just these functions doing so negates any advanced...

Page 32: ...arameter 2 has an unknown error ERR_PARAMETER 3 12 Parameter 3 has an unknown error ERR_PARAMETER 4 13 Parameter 4 has an unknown error ERR_PARAMETER 5 14 Parameter 5 has an unknown error ERR_PARAMETER 6 15 Parameter 6 has an unknown error ERR_PARAMETER 7 16 Parameter 7 has an unknown error ERR_PARAMETER 8 17 Parameter 8 has an unknown error ERR_PARAMETER 9 18 Parameter 9 has an unknown error ERR_...

Page 33: ...nction Reads a byte from a hardware port Due to limitations of VisualBASIC the number is returned in an integer Declaration function InPortb byval address as integer as integer InPort Function Reads an integer from a hardware port This function returns the 16 bit value obtained from reading the low byte from address and the high byte from address 1 Declaration function InPort byval address as inte...

Page 34: ...ored in two s complement form All bit patterns must be converted to and from this two s complement form if meaningful display is required Otherwise values returned from the InPortb function will be 128 to 127 rather than 0 to 255 An alternative is to perform all assign ments in hexadecimal rather then decimal form Before the program will execute the GBL file must be modified to include the path to...

Page 35: ... D A t r a t S s u t a t S d n a m m o C C D A W 0 1 V H C G H C f i n o i s r e v n o C 3 S S E R D D A E S A B d e s U t o N n o i s r e v n o C C D A t r a t S 4 S S E R D D A E S A B f i n o i s r e v n o C C D A t r a t S h g i h V H C G H C s t u p t u O C A D o r e Z e c r o F 5 S S E R D D A E S A B d e s U t o N s t u p t u O C A D o r e Z e c r o F 6 S S E R D D A E S A B e t y B w o L C...

Page 36: ... IRQ upon ADC end of conversion IT2 When high Generate an IRQ when Counter 2 times out Note Counter 2 must be in mode 2 to produce interrupts CHGCHV When set high Enable ADC conversion start upon a read to base 4 When set low Enable ADC start upon any write to base 2 CHGCHV must be high to enable hardware start conversions IRQ The returned bit is reserved for future use GATE1 Gate input to Counter...

Page 37: ... but does not clear internal DAC data registers Writing data to the DAC output registers high bytes Base 9 or Base B will re enable the DAC outputs Base 5 Write Performs the same operation as described for Base 4 write operation A D Registers A D data are in true binary form or two s complement by jumper selection and are latched in the A D registers at the end of each conversion The data are read...

Page 38: ...nnector The rear panel connector has two 4 bit ports a 4 bit input port IP0 IP3 and a 4 bit tri statable bi directional input output port OP0 OP3 and 24 bits on the 40 pin on board connector In addition two of the input port lines do double duty IP0 is the also the external A D start conversion trigger and IP2 is the gate input for Counter 0 of the Counter Timer These secondary functions may or ma...

Page 39: ...nput bit Shared with Counter 0 enable gate C0G IP3 Input bit 40 Pin IDC 8255 Base 10 Read Write Parallel Peripheral Interface 8255 Port A 7 B 6 B 5 B 4 B 3 B 2 B 1 B 0 B 7 A P 6 A P 5 A P 4 A P 3 A P 2 A P 1 A P 0 A P Eight bits of digital input output Data written to the port may be readback from the same address Base 11 Read Write Parallel Peripheral Interface 8255 Port B Same format as above Ba...

Page 40: ... e H 3 1 r e t s i g e R y l n O e t i r W To access the board from BASIC for example 1 Determine which ports are to be for input and which for output Determine the proper bit pattern to write to the CONTROL REGISTER as discussed in the following section For example for a configuration of Port A Input Port B Output Port C Upper Input Port C Lower Output The bit pattern would be 1001 1000 Hex 98 Us...

Page 41: ...2XWSXW 3RUW 0RGH 0RGH 3RUW QSXW 2XWSXW 3RUW 8 QSXW 2XWSXW 3RUW GRQ W FDUH Modes of Operation The 8255 offers 3 MODES of operation as set by bits 3 6 and 7 Bit 3 sets the mode for port B and bits 6 7 for port A Port C has no independent modes The 8255 has several input output modes and the user is directed to the 8255 data sheet refer to Appendix D for complete programming details The following inf...

Page 42: ...asic Functional Definitions Two Groups Group A and Group B Each group contains one 8 bit data port and one 4 bit control data port The 8 bit data port can be either input or output Both inputs and outputs are latched The 4 bit port is used for control and status of the 8 bit data port Mode 2 This functional configuration provides a means for communicating with a peripheral device or structure on a...

Page 43: ...BBBBBBB LW LW 6HW 5HVHW FWLYH ODJ 1RWH GRQ W FDUH RQWURO RUG LW 6HW LW 5HVHW Analog Outputs D A Converter DAC registers are write only registers and require a low byte high byte write sequence to load the 12 bit DAC s Note that the registers are double buffered so that the DAC s are not updated until the second high byte is written Thus you can write the low bytes to DAC s 0 and 1 first and then t...

Page 44: ...nary counter that can be used for event or pulse counting delayed triggering or in con junction with other channels for frequency or period measurement Counter 0 may be driven by the internal 1MHz clock or an external clock source Base C Write Read Counter 0 read or write When writing this register is used to load a counter value into the counter The transfer is either a single or double byte tran...

Page 45: ...ese bits select the counter that the control type is destined for SC1 SC0 Function 0 0 Program Counter 0 0 1 Program Counter 1 1 0 Program Counter 2 1 1 Read Write Cmd See Reading and Loading the Counters Page 7 4 RW0 RW1 These bits select the read write mode of the selected counter RW1 RW0 Counter Read Write Function 0 0 Counter Latch Command 0 1 Read Write LS Byte 1 0 Read Write MS Byte 1 1 Read...

Page 46: ...s connect a jumper between the low input and the low level ground at pins 28 or 29 The jumper connected between the low input and the low level ground effectively turns that differential input into a single ended input It s important to understand the difference between input types how to use them effectively and how to avoid ground loops Misuse of inputs is the most common difficulty that users e...

Page 47: ... be converted to voltage for measurement by the A D converter by addition of a shunt resistor installed across the input terminals For example to accommodate 4 20 mA current transmitter inputs connect a 250W shunt resistor across the A D input terminals The resultant 1 5V signal can then be measured The UTB screw terminal accessory board for example in cludes a breadboard area with plated through ...

Page 48: ...nd short to high voltages c Use isolation amplifiers and transformers where necessary There are two types of ground connections on the rear connector of ADIO1600 These are called Power Ground and Low Level Ground Power ground is the noisy or dirty ground that is meant to carry all digital signals and heavy power supply currents Low Level Ground is the signal ground for all analog input functions I...

Page 49: ...8254 modes of operation are described in the following paragraphs to familiarize you with the versatility and power of this device For those interested in more detailed information a full descrip tion of the 8254 programmable interval timer can be found in the Intel or equivalent manufacturers data sheets The following conventions apply for use in describing operation of the 8254 Clock A positive ...

Page 50: ... form Mode 4 Software Triggered Strobe This mode sets the output high and when the count is loaded the counter begins to count down When the counter reaches zero the output will go low for one input period The counter must be reloaded to repeat the cycle A low gate input will inhibit the counter This mode can be used to provide a delayed software trigger for initiating A D conversions Mode 5 Hardw...

Page 51: ...oneous data This is partly caused by carries rippling through the counter during the read operation Also the low and high bytes are read sequentially rather than simultaneously and thus it is possible that carries will be propagated from the low to the high byte during the read cycle To circumvent these problems you can perform a counter latch operation in advance of the read cycle To do this load...

Page 52: ...f operations with the readback command When CNT 0 the counters selected by C0 through C2 are latched simultaneously When STA 0 the counter status byte is read when the counter I O location is accessed The counter status byte provides information about the current output state of the selected counter and its configuration The status byte returned if STA 0 is 7 B 6 B 5 B 4 B 3 B 2 B 1 B 0 B T U O C ...

Page 53: ...sing Counter 0 as a Pulse Counter Note that the counters are down counters so when resetting them it s better to load them with a full count value of 65 535 rather than zero outportb BASEADDRESS F 0x30 counter 0 mode 0 outportb BASEADDRESS C 0xff counter 0 low load byte outportb BASEADDRESS C 0xff counter 0 high load byte Measuring Frequency and Period The two previous sections show how to count p...

Page 54: ...gh That output will remain high until re triggered by the gate input Software Triggered Strobe This is similar to Pulse on Terminal Count except that after loading the output goes high and only goes low for one clock period upon timeout Thus a negative strobe pulse is generated a pro grammed duration after the counter is loaded Hardware Triggered Strobe This is similar to Programmable One Shot exc...

Page 55: ... has to be written to each D A in two consecutive bytes The first byte contains the eight least significant bits of data and the second byte contains the four most significant bits of data The least significant byte should be written first and is stored in an inter mediate register in the D A with no effect on the output When the most significant byte is written it s value is added to the stored l...

Page 56: ...ther lan guages Since the D A s have 12 bit resolution data should be in the range 0 to 4095 decimal or two s complement if selected by the jumper JP5 on the card unsigned value this is our output variable value 2048 we will output half scale outportb base_address 8 value 0xff extract and output lower byte of count outportb base_address 9 value 256 extract and output upper byte of count An assembl...

Page 57: ... selectable 10V 5V 1V 0 5V 0 1V 0 05 V 0 01V 0 005V 0 10V 0 1V 0 0 1V 0 0 01V Coding True binary or two s complement by jumper selection Input Impedance 15 MW CMRR 80dB Common Mode Rejection Ratio with differential inputs CMVR 12VDC Common Mode Rejection Ratio with differential inputs A D Specifications Type Successive approximation Analog Devices 7804 Resolution 12 binary bits Conversion Time 10 ...

Page 58: ...ernal Acquisition Time 2 microsecond typical for full scale step function input resulting in a maximum conversion rate of 100 000 conversions per second D A Specifications Channels 2 independent Type 12 bit double buffered Coding Offset binary or two s complement by jumper selection Non Linearity 0 9 LBS maximum Monotonicity 1 2 bit Output Range 0 2 5V 0 5V 0 10V 2 5V 5V 10V Output Drive 5 mA mini...

Page 59: ...A sink Interrupt Channel Levels Levels 2 through 7 and 10 12 14 and 15 jumper selectable Enable The two IRQ sources End of Conversion CTR2 timeout are individually enabled via control bits in the BASE 0 control register The IRQ is latched and the state of the latch is reported in the INT bit of the status register Reading to the control register clears the IRQ latch and prepares the card to genera...

Page 60: ...ble Clock Frequency DC to 10MHz Active Count Edge Negative edge Min Clock Pulse Width 30nShigh 50nSlow Timer Range 2 5 MHz to 1 pulse hr Environmental Operating Temp 0 to 50o C Storage Temp 20 to 70o C Humidity 0 to 90 RH non condensing Weight 10 oz Power Required 5VDC 800 mA typical ...

Page 61: ...NTER at the command line The program will then prompt you for the desired order of the polynomial then the number of pairs that you wish to use to generate the polynomial You then enter the data pairs and the polynomial is computed and displayed For example given the following data points let s generate a 5th order polynomial to approximate this function x 0 1 2 3 4 5 6 7 8 9 0 1 X f 3 2 3 5 3 4 3...

Page 62: ... polynomials one on the negative side including 0 and one on the positive side also using 0 The results will show a QUALITY of 90 732620 for the negative side and a QUALITY of 0 005131 for the positive side Thus by using two polynomials you have made the positive side very accurate and dramatically improved the negative side Accuracy of the negative side can be further improved by adding points Fo...

Page 63: ...connections or insula tion displacement flat cable types such as AMP 745242 1 may be used The wiring may be directly from the signal sources or may be on ribbon cable from screw terminal accessories such as ICS Advent part number UTB Connections are made to the ADIO1600 card via a 37 pin D type connector that extends through the back of the computer case and a second 40 pin IDC connector on the bo...

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Page 65: ... or insula tion displacement flat cable types such as AMP 745242 1 may be used The wiring may be directly from the signal sources or may be on ribbon cable from screw terminal accessories such as ICS Advent part number UTB The 40 pin IDC connector on the ADIO1600 board surface is the auxiliary 8255 Digital Input Output lines and they appear on a second 37 pin rear panel connector with the followin...

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Page 67: ...art number is CA37 1 The cable adapter will allow the use the lower eight channels of the ADIO1600 for up to eight AT16 P s This adapter is designed to be used with our standard 37 pin ribbon cable If you desire to construct a cable yourself the following chart provides the recommended pin con nections The cable requires two 37 pin D type female connectors Use caution and ensure that in the positi...

Page 68: ...JLF JURXQG XQXVHG KDQQHO QDORJ QSXW XQXVHG KDQQHO QDORJ QSXW XQXVHG KDQQHO QDORJ QSXW XQXVHG KDQQHO QDORJ QSXW XQXVHG KDQQHO QDORJ QSXW XQXVHG KDQQHO QDORJ QSXW 1 QDORJ RPPRQ 1 QDORJ RPPRQ 9 5 1 YROW SRZHU YROW SRZHU ZLWK MXPSHU LQVWDOODWLRQ XQXVHG KDQQHO QDORJ QSXW XQXVHG 1 QDORJ RPPRQ XQXVHG KDQQHO 2XWSXW XQXVHG KDQQHO 5HIHUHQFH QSXW XQXVHG LJLWDO QSXW 7 ULJJHU XQXVHG KDQQHO 5HIHUHQFH QSXW XQXVH...

Page 69: ...7 2 cable adapter which will give you a full 256 chan nels When using all 16 AT16 P s in a system the two CA37 connectors should be attached to a Y cable attached to the I O connector of the ADIO1600 port number C1800Y If you desire to construct a cable yourself the following chart provides the recommended pin con nections The cable requires two 37 pin D type female connectors Use caution and ensu...

Page 70: ...PPRQ ORJLF JURXQG XQXVHG KDQQHO QDORJ QSXW XQXVHG KDQQHO QDORJ QSXW XQXVHG KDQQHO QDORJ QSXW XQXVHG KDQQHO QDORJ QSXW XQXVHG KDQQHO QDORJ QSXW XQXVHG KDQQHO QDORJ QSXW 1 QDORJ RPPRQ 1 QDORJ RPPRQ 9 5 1 YROW SRZHU YROW SRZHU ZLWK MXPSHU LQVWDOODWLRQ XQXVHG KDQQHO QDORJ QSXW XQXVHG 1 QDORJ RPPRQ XQXVHG KDQQHO 2XWSXW XQXVHG KDQQHO 5HIHUHQFH QSXW XQXVHG LJLWDO QSXW 7 ULJJHU XQXVHG KDQQHO 5HIHUHQFH QSX...

Page 71: ... 7 2 3 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Note Bit 7 B7 of the high byte is the sign bit 1 negative 0 positive Integer variables are the most compact form of storage for the 12 bit data from the A D converter and the 16 bit data from the interval timer Therefore to conserve memory and disk space and to optimize execution time all data exchange via the CALL is through integer type variables This poses...

Page 72: ...mmunity EN61000 4 3 1995RadiatedRFFieldImmunity EN61000 4 4 1995EFTImmunityforACandI OLines EN 60950 1992 Safety of InformationTechnology Equipment ThetechnicaldocumentationrequiredtodemonstratethisproductmeetstherequirementsoftheEMCDirective and the LowVoltage Directive has been compiled by ICSAdvent and is available for inspection by the relevant enforcement authorities Attention Theattentionoft...

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