Manual Number: 00650-004-5
Page 5-2
ADIO1600 Manual
Register Definitions
Card Status and Clear Interrupt
The Status register provides information about the operation and configuration of the analog input
functions of the card. Reading the Status register clears interrupt requests and provides means of
controlling the ADIO1600 interrupt status.
Base + 0 Read and Write:
Command and Status Register
7
B
6
B
5
B
4
B
3
B
2
B
1
B
0
B
*
2
E
T
A
G
*
1
E
T
A
G
V
H
C
G
H
C
/
Q
R
I
2
T
I
2
C
D
A
1
C
D
A
0
C
D
A
L
E
S
K
L
C
CLKSEL:
Selects Counter 0 clock, high selects internal 1MHz clock, low selects
external clock input to connecter pin 21 (CTR0 IN).
ADC0:
When high, Analog/Digital conversion starts upon Counter #2 timeout.
ADC1:
When high, Start ADC conversion with external trigger (pin 25 TRIG 0).
ADC2:
When high, Generate an IRQ upon ADC end of conversion.
IT2:
When high, Generate an IRQ when Counter #2 times out. (Note: Counter
#2 must be in mode 2 to produce interrupts.)
CHGCHV:
When set high, Enable ADC conversion start upon a read to base+4,
When set low, Enable ADC start upon any write to base+2.
(CHGCHV must be high to enable hardware start conversions)
IRQ:
The returned bit is reserved for future use.
GATE1:
Gate input to Counter #1 to enable counting, set high to enable gate.
GATE2:
Gate input to Counter #2 to enable counting, set high to enable gate.
*Enable GATE1 and GATE2 together when counters are cascaded.
Base + 2 Read and Write:
ADC Command and Status Register
7
B
6
B
5
B
4
B
3
B
2
B
1
B
0
B
Y
S
U
B
L
A
B
/
E
S
1
N
I
A
G
0
N
I
A
G
3
A
M
2
A
M
1
A
M
0
A
M
MA0:
Least Significant Bit (LSB) of ADC Analog Channel Select multiplexer.
MA1:
Second Significant Bit of ADC Analog Channel Select multiplexer.
MA2:
Third Significant Bit of ADC Analog Channel Select multiplexer.
MA3:
Most Significant Bit (MSB) of ADC Analog Channel Select multiplexer.