5. Appendix
UART Register Mapping
This section describes the UART register mapping for VXC cards. For more
information, please refer to the TI 16C550 datasheet.
wBase+0xC0: Port 0 Receiver Buffer Register (RBR)
wBase+0xE0: Port 1 Receiver Buffer Register (RBR)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Data 7
Data 6
Data 5
Data 4
Data 3
Data 2
Data 1
Data 0
wBase+0xC0: Port 0 Transmitter Holding Register (THR)
wBase+0xE0: Port 1 Transmitter Holding Register (THR)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Data 7
Data 6
Data 5
Data 4
Data 3
Data 2
Data 1
Data 0
wBase+0xC4: Port 0 Interrupt Enable Register (IER)
wBase+0xE4: Port 1 Interrupt Enable Register (IER)
Bit 7 Bit 6 Bit 5 Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0 0 0 0 Enable
Modem
Status
Interrupt
Enable
Receiver
Line Status
Interrupt
Enable
Transmitter
Holding
Register
Empty
Interrupt
Enable
Received
Data
Available
Interrupt
wBase+0xC8: Port 0 FIFO Control Register (FCR)
wBase+0xE8: Port 1 FIFO Control Register (FCR)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Receiver
Trigger
(MSB)
Receiver
Trigger
(LSB)
Reserved
Reserved
DMA
Mode
Select
Transmitter
FIFO
Reset
Receiver
FIFO
Reset
FIFO
Enable
VXC Cards User’s Manual (Ver. 1.1, 06/09.2005, pmh-012-01) -----41