PIO-D64/PIO-
D64U User’s Manual ( Ver.1.
6, Mar. 2015, PMH-007-16 ) ----- 32
3.3.4 INT Mask Control Register
(Read/Write): wBase+5
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0
0
0
0
EN3
EN2
EN1
EN0
Note. Refer to Sec. 3.1 for more information about wBase.
EN0=0
disable INT_CHAN_0 as a interrupt signal (default)
EN0=1
enable INT_CHAN_0 as a interrupt signal
EN1=0
disable INT_CHAN_1 as a interrupt signal (default)
EN1=1
enable INT_CHAN_1 as a interrupt signal
EN2=0
disable INT_CHAN_2 as a interrupt signal (default)
EN2=1
enable INT_CHAN_2 as a interrupt signal
EN3=0
disable INT_CHAN_3 as a interrupt signal (default)
EN3=1
enable INT_CHAN_3 as a interrupt signal
outportb(wBase+5,0); /* disable all interrupts */
outportb(wBase+5,1); /* enable interrupt of INT_CHAN_0 */
outportb(wBase+5,2); /* enable interrupt of INT_CHAN_1 */
outportb(wBase+5,4); /* enable interrupt of INT_CHAN_2 */
outportb(wBase+5,7); /* enable all four channels of interrupt */
Refer to the following demo program for more information:
DEMO3.C of DOS
for INT_CHAN_0 only
DEMO4.C of DOS
for INT_CHAN_1 only
DEMO5.C of DOS
for INT_CHAN_2 only
DEMO6.C of DOS
for INT_CHAN_1 and INT_CHAN_2
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