5.2 Parallel Bus
5.2.1
Timing Diagram
Address
Data
Data
Address
Phase
Data
Phase
t1
t2
t3
t4
CLKOUTA
A12-A0
/CS
/RD
D7-D0
(Read)
/WR
D7-D0
(Write)
Address
Phase
Data
Phase
t1
t2
t3
t4
CLKOUTA
ARDY (Normally
Not-Ready System)
ARDY (Normally
Ready System)
Case 2
Case 4
Case 1
Case 3
t4
tw
t3
t2
t4
tw
tw
tw
t4
tw
tw
t3
I/O Expansion Bus for 7188X/7188E User’s Manual, Jan/2005 v1.5, 7PH-000-15---25