Evaluation Board Manual
Preliminary
PPC750FX Evaluation Board
750FXebm_ch1.fm
June 10, 2003
Overview
Page 17 of 115
• Reliability and Serviceability
- Parity checking on 60x busses.
- ECC checking on L2 cache.
- Parity on the L1 arrays.
- Parity on the L1 and L2 tags.
• Testability
- Level-sensitive scan design (LSSD).
- Powerful diagnostic and test interface through Common On-Chip Processor (COP) and IEEE 1149.1
(JTAG) interface.
1.2 Board Features
The features of the PPC750FX evaluation board are summarized briefly below. More detail may be found in
Section 2 Board Design on page 19.
• PCI adapter form factor
• Two IBM PowerPC 750FX processors
• Marvell
MV64360 System Controller
• 256 MB DDR SDRAM with ECC
• 1MB 8-bit wide socketed Flash (2 - 512KB devices)
• 1MB 8-bit wide SRAM
• 32MB 32-bit wide Flash
• 32KB Ferroelectric Nonvolatile RAM (FRAM)
• Two 100BASE-TX Ethernet ports
• Two 16550 compatible serial ports
• Two 64kb IIC Serial EEPROMs
• Single RISCWatch header for both processors
• Powered either externally or from PCI slot
• External system clock input
• External input for programming the on-board CPLD (FPGA)
