Chapter 2. System-Board Features
Chip Set Control
Two components, the Intel 440BX and PIIX4E, make up the chip set that is the interface between the
microprocessor and the following:
Memory subsystem
PCI bus
IDE Bus Master connection
High-performance, PCI-to-ISA bridge
USB ports
SMBus
Enhanced DMA controller
L2 Cache
The Pentium II microprocessor with MMX technology provides 512 KB of L2 cache with ECC. The
Celeron microprocessor provides 128 KB L2 cache. The L2 cache ECC function is automatically enabled
when ECC memory is installed. If nonparity memory is installed, the L2 cache ECC is disabled. (For
information on overriding these settings, refer to Chapter 5, Configuration/Setup Utility Program, in
PC
300GL User Guide.)
System Memory
The system memory interface is controlled by the 440BX chip set. Synchronous dynamic random access
memory (SDRAM) is standard.
The maximum amount of system memory is 384 MB on some models and 256 MB on some models. For
memory expansion, some system board models provide three dual inline memory module (DIMM)
connectors. Other models provide two DIMM connectors. 100 MHz DIMMs in sizes of 16 MB, 32 MB, 64
MB, and 128 MB are supported. The amount of memory preinstalled varies by model.
The following information applies to system memory:
SDRAM (synchronous dynamic random access memory), nonparity memory is standard.
Error correcting code (ECC) is supported in Pentium II models
The maximum height of memory modules is 3.18 cm (1.25 in.).
Only PC 100 industry-standard, gold-lead DIMMs are supported.
A mix of ECC and nonparity types configures as nonparity.
For information on the pin assignments for the memory module connectors, see “Memory Connectors” on
page 28.
Chapter 2. System Board Features
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