6.2.4.8 Host Terminating Write DMA
HSTROBE
DDMARDY-
DMACK-
DMARQ
STOP
tMLI
tLI
DD(15:00)
Host drives DD
tCH
tCS
CRC
tSS
tACK
tACK
tLI
tIORDYZ
xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
xxxxxxxxxx
tLI
Figure 41. Ultra DMA cycle timing chart (Host Terminating Write)
20
–
20
–
20
–
20
–
20
–
20
–
Maximum time before releasing
IORDY
tIORDYZ
–
20
–
20
–
20
–
20
–
20
–
20
Hold time for DMACK–
tACK
–
5
–
5
–
5
–
5
–
5
–
5
CRC word hold time (at device
side)
tCH
–
5
–
5
–
7
–
7
–
10
–
15
CRC word setup time (at device
side)
tCS
–
20
–
20
–
20
–
20
–
20
–
20
Interlock time with minimum
tMLI
75
0
100
0
100
0
150
0
150
0
150
0
Limited interlock time
tLI
–
50
–
50
–
50
–
50
–
50
–
50
Time from HSTROBE to edge
assertion of STOP
tSS
MAX
MIN
MAX
MIN
MAX
MIN
MAX
MIN
MAX
MIN
MAX
MIN
MODE5
MODE4
MODE3
MODE2
MODE1
MODE0
PARAMETER DESCRIPTION
(all values in ns)
Figure 42. Ultra DMA cycle timings (Host Terminating Write)
Deskstar 120GXP hard disk drive specifications
37
Summary of Contents for IC35L040AVVN07-0 - 40GB IDE Deskstar 120GXP 7200RPM UATA-100...
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