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EM78P221/2N

8-Bit Microcontroller with OTP ROM

46

•

Product Specification (V1.0) 10.19.2007

(This specification is subject to change without further notice)

6.9.2

Residual Voltage Protection

When the battery is replaced, device power Vdd is removed but residual voltage
remains. The residual voltage may trip below Vdd minimum, but not to zero. This
condition may cause a poor power-on reset. Fig. 6-16 and Fig. 6-17 show how to
create a protection circuit against residual voltage.

/RESET

VDD

100K

Q1

1N4684

10K

33K

VDD

Fig. 6-16 Residual Voltage Protection Circuit 1

/RESET

VDD

Q1

VDD

R3

R2

R1

Fig. 6-17 Residual Voltage Protection Circuit 2

6.10 Low Voltage Reset

Low voltage reset (LVR) is designed for unstable power situation, such as external
power noise interference or in EMS test condition.

When LVR is enabled, the system supply voltage (Vdd) drops below Vdd reset level
(V

RESET

) and remains at 10

μ

s, system reset will occur and the system will remain at

reset status. The system will remain at reset status until Vdd voltage rises above Vdd
release level. Refer to Fig 6-18.

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Summary of Contents for EM78P221/2N

Page 1: ...EM78P221 2N 8 Bit Microcontroller with OTP ROM Product Specification DOC VERSION 1 0 ELAN MICROELECTRONICS CORP October 2007 ...

Page 2: ...ation is furnished under a license or nondisclosure agreement and may be used or copied only in accordance with the terms of such agreement ELAN Microelectronics products are not intended for use in life support appliances devices or systems Use of ELAN Microelectronics product in such applications is not supported and is prohibited NO PART OF THIS SPECIFICATION MAY BE REPRODUCED OR TRANSMITTED IN...

Page 3: ... 8 Bank 0 R5 Port 5 11 6 2 9 Bank 0 R6 Port 6 11 6 2 10 Bank 0 R7 Port 7 11 6 2 11 Bank 0 R8 Port 8 11 6 2 12 Bank 0 R9 RD Reserve 11 6 2 13 Bank 0 RE WUCR Wake up Control Register 12 6 2 14 Bank 0 RF Interrupt Status Register 12 6 2 15 Bank 1 R5 R7 I O Port Control Register 13 6 2 16 Bank 1 R8 I O Port Control Register 13 6 2 17 Bank 1 R9 Reserve 14 6 2 18 Bank 1 RA CMPCON Comparator Control Regi...

Page 4: ...ler Reset Block Diagram 34 6 5 2 The T and P Status under Status Register 35 6 6 Interrupt 36 6 7 Comparator 38 6 7 1 External Reference Signal 38 6 7 2 Comparator Outputs 38 6 7 3 Using a Comparator as an Operation Amplifier 39 6 7 3 1 Bank 0 RE WUCR Wake up Control Register 39 6 7 3 2 Bank 1 RA CMPCON Comparator Control Register 40 6 7 3 3 Bank 1 RE WDT Control Register 40 6 7 4 Comparator Inter...

Page 5: ... Diagrams 56 APPENDIX A Package Type 57 B Packaging Configuration 58 B 1 24 Lead Plastic Skinny Dual in line SDIP 300 mil 58 B 2 24 Lead Plastic Small Outline SOP 300 mil 59 B 3 24 Lead Plastic Shrink Small Outline SSOP 209 mil 60 B 4 28 Lead Plastic Skinny Dual in line SDIP 300 mil 61 B 5 28 Lead Plastic Small Outline SOP 300 mil 62 B 6 28 Lead Plastic Shrink Small Outline SSOP 209 mil 63 C Quali...

Page 6: ...cation V1 0 10 19 2007 This specification is subject to change without further notice Specification Revision History Doc Version Revision Description Date 0 9 Preliminary version 2007 03 20 1 0 Initial released version 2007 10 19 ...

Page 7: ...ave been modified to favorably meet users requirements The following table is provided for quick comparison between the two package version and for user convenience in the choice of the most suitable product for their application EM78P221 222N V EM78P221 222N U Crystal mode Operating frequency range at 0 C 70 C DC 12MHz 4 0V DC 8MHz 3 0V DC 4MHz 2 1V DC 16MHz 4 5V DC 8MHz 3 0V DC 4MHz 2 1V IRC mod...

Page 8: ...e range 2 3V 5 5V industrial Operating temperature range Operating temperature range 0 C 70 C commercial Operating temperature range 40 C 85 C industrial Operating frequency range Crystal mode DC 16MHz 2 clks 4 5V DC 125ns inst cycle 4 5V DC 8MHz 2 clks 3V DC 250ns inst Cycle 3V ERC mode DC 16MHz 2 clks 4 5V DC 125ns inst cycle 5V DC 8MHz 2 clks 3V DC 250ns inst Cycle 3V IRC mode Oscillation mode ...

Page 9: ...73 CIN P71 CO INT1 P64 P65 P66 P55 P54 P50 P77 INT0 EM78P222N 1 2 3 4 5 6 7 8 9 10 28 27 26 25 24 23 22 21 12 11 18 17 20 19 P61 P62 P63 P60 P51 P74 P75 P80 14 13 16 15 P76 Fig 3 1 EM78P222NK AK M AM 2 24 Pin DIP SOP SSOP P70 VSS P67 P57 P56 TCC P53 OSCI P52 OSCO VDD P81 RESET P72 CIN P73 CIN P71 CO INT1 P64 P65 P66 P55 P54 P50 P77 INT0 EM78P221N 1 2 3 4 5 6 7 8 9 10 24 23 22 21 20 19 18 17 12 11 ...

Page 10: ...80 P81 13 28 I O 2 bit General purpose input or output pin Default value at power on reset P81 is define as General purpose input or output open drain pin CIN CIN CO 22 23 24 I I O input pin of Vin of the comparator input pin of Vin of the comparator Pin CO is the comparator output Defined by CMPCON Bank 1 RA 3 4 OSCI 27 I Crystal type Crystal input terminal RC type RC oscillator input pin OSCO 26...

Page 11: ... ICE220N simulator P81 24 I O 1 bit General purpose input or output open drain pin Default value at power on reset CIN CIN CO 18 19 20 I I O input pin of Vin of the comparator input pin of Vin of the comparator Pin CO is the comparator output Defined by CMPCON Bank 1 RA 3 4 OSCI 23 I Crystal type Crystal input terminal RC type RC oscillator input pin OSCO 22 O Crystal type Output terminal for crys...

Page 12: ...ction Decoder Instruction Register ALU PC Interrupt Circuit 8 level stack 13 bit Interrupt Control Register Oscillation Generation RAM Mux Ext OSC R4 Ext RC Int RC Comparator LVR Cin Cin CO P5 P50 P57 P56 P55 P54 P53 P52 P51 Ext INT Reset P6 P60 P67 P66 P65 P64 P63 P62 P61 P7 P70 P74 P73 P72 P71 P8 P81 WDT TCC Port change TCC Port 6 P77 P75 P76 P80 Fig 5 1 EM78P221 2N Functional Block Diagram ...

Page 13: ...gh Sink Control Register for Port 6 Reserve 08 R8 Port 8 R8 I O Port Control Register Reserve Reserve 09 Reserve Reserve Reserve Reserve 0A Reserve RA Comparator Control Register Reserve Reserve 0B Reserve RB Pull down Control Register Reserve Reserve 0C Reserve RC Open drain Control Register Reserve Reserve 0D Reserve RD Pull high Control Register Reserve Reserve 0E RE Wake up Control Register RE...

Page 14: ...T1 pin Bit 6 INT Interrupt enable flag 0 masked by DISI or hardware interrupt 1 enabled by the ENI RETI instructions This bit is readable only Bit 5 TS TCC signal source 0 internal instruction cycle clock If P56 is used as I O pin TS must be 0 1 transition on the TCC pin Bit 4 TE TCC signal edge 0 increment if the transition from low to high takes place on the TCC pin 1 increment if the transition...

Page 15: ... 3 for the control register See the table under Section 6 2 Registers Description for the data memory configuration 6 2 5 R2 Program Counter and Stack On chip Program Memory 000H FFFH 008H Interrupt Vector User Memory Space Reset Vector A11 A10 Stack Level 1 Stack Level 3 Stack Level 2 Stack Level 4 Stack Level 5 CALL 00 PAGE0 0000 03FF 01 PAGE1 0400 07FF 10 PAGE2 0800 0BFF 11 PAGE3 0C00 0FFF RET ...

Page 16: ... relative address to be added to the current PC and the ninth and above bits of the PC will increase progressively MOV R2 A allows loading of an address from the A register to the lower 8 bits of the PC and the ninth and above bits of the PC will remain unchanged Any instruction except ADD R2 A that is written to R2 e g MOV R2 A BC R2 6 etc will cause the ninth bit and above bits of the PC to rema...

Page 17: ...64 P63 P62 P61 P60 Bits 7 0 P67 P60 I O data bits 6 2 10 Bank 0 R7 Port 7 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 P77 P76 P75 P74 P73 P72 P71 P70 Bits 7 0 P77 P70 I O data bits With Simulator P73 P72 are input or open drain output pins With EM78P221 2N P73 P72 are general input or output pins 6 2 11 Bank 0 R8 Port 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0 0 NREN 0 0 0 P81 P80 Bit...

Page 18: ...ep the ICWE bit must be set to Enable Bit 2 CMPWE Comparator wake up enable bit 0 Disable Comparator wake up 1 Enable Comparator wake up When the Comparator output status change is used to enter interrupt vector or to wake up from sleep the CMPWE bit must be set to Enable Bit 0 CMPIF Comparator interrupt flag Set when a change occurs in the output of Comparator Reset by software 0 no interrupt occ...

Page 19: ...interrupt mask register Interrupt results from logic AND of Bank 0 RF 2 1 0 and Bank 1 RF 2 1 0 with instruction ENI 6 2 15 Bank 1 R5 R7 I O Port Control Register Bits 7 0 0 defines the relative I O pin as output 1 puts the relative I O pin into high impedance Bank 1 R5 R6 and R7 registers are all readable and writable 6 2 16 Bank 1 R8 I O Port Control Register Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 ...

Page 20: ...ontrol bit of P77 Bit 7 of Bank 1 R7 must be set to 1 NOTE When EIS is 0 the path of INT is masked When EIS is 1 the status of INT pin can also be read by way of reading Port 7 Bank 0 R7 Refer to Fig 6 4 I O Port and I O Control Register Circuit for P77 INT0 and P71 INT1 under Section 6 4 I O Ports EIS0 and EIS1 are both readable and writable The highest priority of P71 INT1 CO2 is INT1 When EIS1 ...

Page 21: ...e the pull down function of the P62 pin Bit 1 PD1 Control bit used to enable the pull down function of the P61 pin Bit 0 PD0 Control bit used to enable the pull down function of the P60 pin 6 2 20 Bank 1 RC Open Drain Control Register Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 OD7 OD6 OD3 OD2 OD5 OD4 OD1 OD0 Bank 1 RC register is both readable and writable Bit 7 OD7 Control bit used to enable...

Page 22: ...pin Bit 2 PH2 Control bit used to enable the pull high function of the P52 pin Bit 1 PH1 Control bit used to enable the pull high function of the P51 pin Bit 0 PH0 Control bit used to enable the pull high function of the P50 pin 6 2 22 Bank 1 RE WDT Control Register Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 WDTE 0 PSWE PSW2 PSW1 PSW0 0 CMPIE NOTE Bank 1 RE 0 register is both readable and wri...

Page 23: ...output status change 6 2 23 Bank 1 RF Interrupt Mask Register Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0 0 0 0 0 EXIE ICIE TCIE NOTE RF register is both readable and writable Individual interrupt is enabled by setting its associated control bit in the RF to 1 Global interrupt is enabled by the ENI instruction and is disabled by the DISI instruction Refer to Fig 6 8 Interrupt Input Circuit u...

Page 24: ...nt Select for P62 Bit 1 HD61 Output High Drive Current Select for P61 Bit 0 HD60 Output High Drive Current Select for P60 HDxx VDD 5V Drive Current 0 9mA in 0 9VDD 1 27mA in 0 7VDD 6 2 25 Bank 2 R6 HSCR1 High Sink Control Register for Port 5 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 HS57 HS56 HS55 HS54 HS53 HS52 HS51 HS50 With Simulator function nonexistent With EM78P221 2N General I O pins ...

Page 25: ... High Sink Current Select for P61 Bit 0 HS60 Output High Sink Current Select for P60 HDxx VDD 5V Sink Current 0 18 mA in 0 1VDD 1 75 mA in 0 3VDD 6 2 27 Bank 2 R8 Operating Mode Control Register Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0 1 1 0 0 0 0 0 Bits 7 4 0 not used fixed to 0 all the time Bits 6 5 not used fixed to 1 all the time NOTE If user wants the MCU to work normally user must s...

Page 26: ... Calibrator of internal RC mode C3 C2 C1 C0 Frequency MHz 0 0 0 0 1 36 F 0 0 0 1 1 31 5 F 0 0 1 0 1 27 F 0 0 1 1 1 22 5 F 0 1 0 0 1 18 F 0 1 0 1 1 13 5 F 0 1 1 0 1 9 F 0 1 1 1 1 4 5 F 1 1 1 1 F default 1 1 1 0 1 4 5 F 1 1 0 1 1 9 F 1 1 0 0 1 135 F 1 0 1 1 1 18 F 1 0 1 0 1 22 5 F 1 0 0 1 1 27 F 1 0 0 0 1 31 5 F 1 Frequency values shown are theoretical and taken at an instance of a high frequency mo...

Page 27: ... to 32 fc s are regarded as signal default NOTE The noise rejection function is turned off in the LXT2 and sleep mode Bit 2 NRE Noise rejection enable 0 disable noise rejection 1 enable noise rejection default However in Low Crystal oscillator LXT mode the noise rejection circuit is always disabled Bits 1 0 LVR1 LVR0 Low Voltage Reset enable bits If Vdd has crossover at Vdd reset level as Vdd chan...

Page 28: ...nal signal input edge selectable from the TCC pin If the TCC signal source is from an external clock input TCC will be incremented by 1 at every falling edge or rising edge of the TCC pin The TCC pin input time length kept at High or Low level must be greater than 1CLK 1 CLK is always Fosc 2 Refer to Fig 6 2 NOTE The internal TCC will stop running when in sleep mode The watchdog timer is a free ru...

Page 29: ...s an input status change interrupt or wake up function Most I O pin can be defined as input or output pin by the I O control registers P52 P53 are only used as output pins The I O registers and I O control registers are both readable and writable However the initial states of these I O ports Port 5 Port 6 Port 7 and Port 8 are unknown input high impedance Then if the I O pin is pulled to a level a...

Page 30: ...C L PDWR D Q Q _ CLK P R C L P R C L CLK D Q Q _ PORT Note CO2 Pull high and Open drain are not shown in the figure Fig 6 4 I O Port and I O Control Register Circuit for P77 INT0 and P71 INT1 PCRD M U X IOD 0 1 PDRD P60 P67 PCW R D Q Q _ CLK P R C L PDW R D Q Q _ CLK P R C L P R C L CLK D Q Q _ TI n PORT Note Pull high down and Open drain are not shown in the figure Fig 6 5 I O Port and I O Contro...

Page 31: ...Wake up Interrupt 1 Wake up 2 Wake up and Interrupt a Before Sleep a Before Sleep 1 Disable WDT 1 Disable WDT 2 Read I O Port 6 MOV R6 R6 2 Read I O Port 6 MOV R6 R6 3 Execute ENI or DISI 3 Execute ENI or DISI 4 Enable wake up bit Set Bank 0 RE ICWE 1 4 Enable wake up bit Set Bank 0 RE ICWE 1 5 Execute SLEP instruction 5 Enable interrupt Set BANK1 RF ICIE 1 b After wake up 6 Execute SLEP instructi...

Page 32: ... state The Watchdog Timer and prescaler are cleared When power is switched On the Memory switch register R1 is set to 0 The CONT register bits are set to all 0 except for Bit 6 INT flag The Bank 0 RF register bits are set to all 0 The Bank 1 RB register bits are set to all 1 The Bank 1 RC register bits are set to all 1 The Bank 1 RD register bits are set to all 1 The Bank 1 RE register bits are se...

Page 33: ...eep mode That is Case a If WDT is enabled before SLEP all of the RE bit is disabled Hence the EM78P221 2N can be awakened only with Case 1 or Case 2 Refer to the section on Interrupt Section 6 6 for further details Case b If Port 6 Input Status Change is used to wake up EM78P221 2N and ICWE bit of Bank 0 RE register is enabled before SLEP WDT must be disabled Hence the EM78P221 2N can be awakened ...

Page 34: ...Disable WDT MOV RE A WDTC Clear WDT and prescaler ENI or DISI Enable or disable global interrupt MOV A 00000100b Enable comparator output status change wake up bit BANK 0 MOV RE A BANK 1 MOV A 0x00000001b Enable Comparator 1 output status change interrupt MOV RE A SLEP Sleep 6 5 1 1 Wake up and Interrupt Modes Operation Summary All categories under Reset Wake up and Interrupt modes are summarized ...

Page 35: ...1 Port 6 Input Status Change Wake up Interrupt Vector 0x08 Set Bank 0 RF ICIF 1 Oscillator TCC and TIMERX are stopped Interrupt Vector 0x08 Set Bank 0 RF ICIF 1 DISI Bank 1 RF TCIE Bit 0 1 Next Instruction Set Bank 0 RF TCIF 1 ENI Bank 1 RF TCIE Bit 0 1 TCC Overflow N A Interrupt Vector 0x08 Set Bank 0 RF TCIF 1 Bank 0 RE CMPWE Bit 2 0 Bank 1 RE CMPIE Bit 0 0 Bank 1 RE CMPIE Bit 0 0 Comparator out...

Page 36: ...e BS1 BS Power on 0 0 0 0 0 0 0 0 RESET WDT 0 0 0 0 0 0 0 0 0x01 R1 MSR Wake up from Pin Change P P P P P P P P Bit Name Power on 0 0 0 0 0 0 0 0 RESET WDT 0 0 0 0 0 0 0 0 0x02 R2 PC Wake up from Pin Change Jump to Address 0x08 or continue to execute next instruction Bit Name T P Z DC C Power on 0 0 0 1 1 U U U RESET WDT 0 0 0 t t P P P 0x03 R3 SR Wake up from Pin Change P P P t t P P P Bit Name P...

Page 37: ...0 R9 RD Reserve Wake up from Pin Change P P P P P P P P Bit Name EX1IF ICWE CMPWE CMPIF Power on 0 0 0 0 0 0 0 0 RESET WDT 0 0 0 0 0 0 0 0 0xE Bank 0 RE WUCR Wake up from Pin Change P P P P P P P P Bit Name EX0IF ICIF TCIF Power on 0 0 0 0 0 0 0 0 RESET WDT 0 0 0 0 0 0 0 0 0xF Bank 0 RF ISR Wake up from Pin Change P P P P P P P P Bit Name C57 C56 C55 C54 C53 C52 C51 C50 Power on 1 1 1 1 1 1 1 1 RE...

Page 38: ...P Bit Name EIS1 EIS0 CMP OUT CMP COS1 CMP COS0 Power on 0 0 0 0 0 0 0 0 RESET WDT 0 0 0 0 0 0 0 0 0xA Bank 1 RA CMPCON Wake up from Pin Change P P P P P P P P Bit Name PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0 Power on 1 1 1 1 1 1 1 1 RESET WDT 1 1 1 1 1 1 1 1 0xB Bank 1 RB Wake up from Pin Change P P P P P P P P Bit Name OD7 OD6 OD5 OD4 OD3 OD2 OD1 OD0 Power on 1 1 1 1 1 1 1 1 RESET WDT 1 1 1 1 1 1 1 1 0xC...

Page 39: ...WDT 0 0 0 0 0 0 0 0 0x06 Bank 2 R6 HSCR1 Wake up from Pin Change P P P P P P P P Bit Name HS67 HS66 HS65 HS64 HS63 HS62 HS61 HS60 Power on 0 0 0 0 0 0 0 0 RESET WDT 0 0 0 0 0 0 0 0 0x07 Bank 2 R7 HSCR2 Wake up from Pin Change P P P P P P P P Bit Name Power on U 1 1 1 U U U U RESET WDT P 1 1 1 P P P P 0x8 Bank 2 R8 OMCR Wake up from Pin Change P P P P P P P P Bit Name Power on 0 0 0 0 0 0 0 0 RESET...

Page 40: ...P P P P P P P P Bit Name Power on U U U U U U U U RESET WDT P P P P P P P P 0x10 0x1F R10 R1F Wake up from Pin Change P P P P P P P P Bit Name Power on U U U U U U U U RESET WDT P P P P P P P P 0x20 0x3F Bank 0 3 R20 R3F Wake up from Pin Change P P P P P P P P Legend not used P previous value before reset u unknown or don t care t check Reset Type Table in Section 6 5 2 6 5 1 3 Controller Reset Bl...

Page 41: ...low are used to check how the processor wakes up Reset Type T P Power on 1 1 RESET during Operating mode P P RESET wake up during Sleep mode 1 0 LVR during Operating mode P P LVR wake up during SLEEP mode 1 0 WDT during Operating mode 0 P WDT wake up during Sleep mode 0 0 Wake up on pin change during Sleep mode 1 0 P Previous status before reset The following shows the events that may affect the s...

Page 42: ...the power to vibrate fiercely While Vdd is still unsettled the supply voltage may be below working voltage When the system supply voltage Vdd is below the working voltage the IC kernel must automatically keep all register status Bank 0 RE and Bank 0 RF are the interrupt status register that records the interrupt requests in the relative flags bits Bank 1 RE and Bank 1 RF are interrupt mask registe...

Page 43: ...on is subject to change without further notice BANK0 RE RF BANK0 RE RF RD BANK0 RE RF WR BANK1 RE RF RD BANK1 RE RF WR BANK1 RE RF Fig 6 8 Interrupt Input Circuit Interrupt Sources Interrupt occurs ENI DISI Stack ACC Stack R3 RETI ACC R3 2 0 R4 Stack R4 R1 5 4 1 0 Stack R1 Fig 6 9 Interrupt Backup Diagram ...

Page 44: ...rence Signal The analog signal presented at Cin compares to the signal at Cin and the digital output CO of the comparator is adjusted accordingly by taking the following notes into considerations NOTE The reference signal must be between Vss and Vdd The reference voltage can be applied to either pin of the comparator Threshold detector applications may be of the same reference The comparator can o...

Page 45: ...UT CMRD CMRD From other comparator RESET From OP I O Fig 6 11 Comparator Output Configuration 6 7 3 Using a Comparator as an Operation Amplifier 6 7 3 1 Bank 0 RE WUCR Wake up Control Register Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 EX1IF 0 0 ICWE 0 CMPWE 0 CMPIF Bit 2 CMPWE Comparator wake up enable bit 0 Disable Comparator wake up 1 Enable Comparator wake up When the Comparator output st...

Page 46: ...errupt 1 Enable CMPIF interrupt When the Comparator output status change is used to enter an interrupt vector or to enter the next instruction the CMPIE bit must be set to Enable But actually the comparator output must be read to latch the status at first Then the comparator output is compared to this latch to produce the information of output status change 6 7 4 Comparator Interrupt CMPIE must be...

Page 47: ... 0 1 0 IRC 2 Internal RC oscillator mode P52 OSCO act as OSCO 0 1 1 LXT1 3 Frequency range of XT mode is 1MHz 100kHz 1 0 0 HXT1 3 Frequency range of XT mode is 16MHz 6MHz 1 0 1 LXT2 3 Frequency range of XT mode is 32kHz 1 1 0 HXT2 3 Frequency range of XT mode is 6MHz 1MHz Default 1 1 1 1 In ERC mode OSCI is used as oscillator pin OSCO P52 is defined by code option Word 0 Bit 6 Bit 4 2 In IRC mode ...

Page 48: ... C2 RS a serial resistor may be required for AT strip cut crystal or low frequency mode Fig 6 13 1 is a recommended PCB layout When the system works in Crystal mode 16MHz a 10KΩ is connected between OSCI and OSCO Capacitor selection guide for crystal oscillator or ceramic resonators Oscillator Type Frequency Mode Frequency C1 pF C2 pF 100kHz 67pF 67pF 200kHz 30pF 30pF 455kHz 30pF 30pF LXT 100K 1MH...

Page 49: ...P221 2N 8 Bit Microcontroller with OTP ROM Product Specification V1 0 10 19 2007 43 This specification is subject to change without further notice Fig 6 13 1 Parallel Mode Crystal Resonator Circuit Diagram ...

Page 50: ... than 1MΩ If the frequency cannot be kept within this range the frequency can be easily affected by noise humidity and leakage The smaller the Rext in the RC oscillator the faster its frequency will be On the contrary for very low Rext values for instance 1 KΩ the oscillator will become unstable because the NMOS cannot discharge the capacitance current correctly Based on the above reasons it must ...

Page 51: ...stabilizes to a steady state EM78P221 2N has a built in Power on Voltage Detector POVD with detection level range of 1 7V to 1 9V The circuitry eliminates the extra external reset circuit It will work well if Vdd rises quickly enough 50 ms or less However under critical applications extra devices are still required to assist in solving power on problems 6 9 1 External Power on Reset Circuit The ci...

Page 52: ...otection circuit against residual voltage RESET VDD 100K Q1 1N4684 10K 33K VDD Fig 6 16 Residual Voltage Protection Circuit 1 RESET VDD Q1 VDD R3 R2 R1 Fig 6 17 Residual Voltage Protection Circuit 2 6 10 Low Voltage Reset Low voltage reset LVR is designed for unstable power situation such as external power noise interference or in EMS test condition When LVR is enabled the system supply voltage Vd...

Page 53: ...dd changes the system will reset LVR1 LVR0 VDD Reset Level VDD Release Level 11 NA Power on Reset default 10 2 5V 2 7V 01 3 0V 3 2V 00 4 0V 4 2V Vdd Internal Reset VRESET Vdd Vreset not longer than 10us thesystem still keepson operating LVR Voltagedrop 18ms System occur reset LVR Voltagedrop Fig 6 18 LVR Waveform Situation 6 11 Code Option EM78P221 2N has two Code Option Words and one Customer ID ...

Page 54: ...tor Modes OSC2 OSC1 OSC0 ERC 1 External RC oscillator mode P52 OSCO act as P52 0 0 0 ERC 1 External RC oscillator mode P52 OSCO act as OSCO 0 0 1 IRC 2 Internal RC oscillator mode P52 OSCO act as P52 0 1 0 IRC 2 Internal RC oscillator mode P52 OSCO act as OSCO 0 1 1 LXT1 3 Frequency range of XT mode is 1MHz 100kHz 1 0 0 HXT1 3 Frequency range of XT mode is 16MHz 6MHz 1 0 1 LXT2 3 Frequency range o...

Page 55: ...n IRC or ERC mode 0 OSCO pin is open drain 1 OSCO output instruction clock Default Bit 8 NRHL Noise rejection high low pulse define bit INT pin has a falling edge trigger 0 Pulses equal to 8 fc are regarded as signal 1 Pulses equal to 32 fc are regarded as signal Default NOTE NRHL and NRE are at Bank 3 R7 when using ICE Bit 7 NRE Noise rejection enable 0 disable noise rejection 1 enable noise reje...

Page 56: ...13 bit word divided into an OP code and one or more operands Normally all instructions are executed within one single instruction cycle one instruction consists of 2 oscillator time periods Note the program counter is changed by instructions MOV R2 A ADD R2 A or by instructions of arithmetic or logic operation on R2 e g SUB R2 A BS C R2 6 CLR R2 etc In this case these instructions only need one in...

Page 57: ...Enable Interrupt None 0 0000 0001 0100 0014 CONTR CONT A None 0 0000 01rr rrrr 00rr MOV R A A R None 0 0000 1000 0000 0080 CLRA 0 A Z 0 0000 11rr rrrr 00rr CLR R 0 R Z 0 0001 00rr rrrr 01rr SUB A R R A A Z C DC 0 0001 01rr rrrr 01rr SUB R A R A R Z C DC 0 0001 10rr rrrr 01rr DECA R R 1 A Z 0 0001 11rr rrrr 01rr DEC R R 1 R Z 0 0010 00rr rrrr 02rr OR A R A VR A Z 0 0010 01rr rrrr 02rr OR R A A VR R...

Page 58: ...1 R skip if zero None 0 100b bbrr rrrr 0xxx BC R b 0 R b None1 0 101b bbrr rrrr 0xxx BS R b 1 R b None 2 0 110b bbrr rrrr 0xxx JBC R b if R b 0 skip None 0 111b bbrr rrrr 0xxx JBS R b if R b 1 skip None 1 00kk kkkk kkkk 1kkk CALL k PC 1 SP lower 10 bits of k PC None 1 01kk kkkk kkkk 1kkk JMP k lower 10 bits of k PC None 1 1000 kkkk kkkk 18kk MOV A k k A None 1 1001 kkkk kkkk 19kk OR A k A k A Z 1 ...

Page 59: ...C mode 3 75 V VILRC Input Low Threshold Voltage Schmitt Trigger OSCI in RC mode 1 25 V IIL Input Leakage Current for input pins VIN VDD VSS 1 0 0 1 0 μA VIH1 Input High Voltage Schmitt Trigger Ports 5 6 7 8 3 75 V VIL1 Input Low Voltage Schmitt Trigger Ports 5 6 7 8 1 25 V VIHT1 Input High Threshold Voltage Schmitt Trigger RESET 1 9 V VILT1 Input Low Threshold Voltage Schmitt Trigger RESET 1 2 V V...

Page 60: ...A ICC2 Operating supply current at two clocks VDD 3V RESET High Fosc 32kHz Crystal type CLKS 0 Output pin floating WDT enabled LVR disabled 15 25 μA ICC3 Operating supply current at two clocks VDD 5V RESET High Fosc 4MHz Crystal type CLKS 0 Output pin floating WDT enabled LVR disabled 1 5 1 7 mA ICC4 Operating supply current at two clocks VDD 5V RESET High Fosc 10MHz Crystal type CLKS 0 Output pin...

Page 61: ...1 The output voltage is in the unit gain circuitry and over the full input common mode range 2 The input common mode voltage or either input signal voltage should not be allowed to go negative by more than 0 3V The upper end of the common mode voltage range is VDD 1 3 The response time specified is a 100mV input step with 5mV overdrive 9 AC Electrical Characteristic Ta 25 C VDD 5V 5 VSS 0V Symbol ...

Page 62: ...ing Diagrams RESET Timing CLK 0 CLK RESET NOP Instruction 1 Executed Tdrh TCC Input Timing CLKS 0 CLK TCC Ttcc Tins AC Testing Input is driven at VDD 0 5V for logic 1 and GND 0 5V for logic 0 Timing measurements are made at 0 75VDD for logic 1 and 0 25VDD for logic 0 AC Test Input Output Waveform VDD 0 5V GND 0 5V 0 75VDD 0 25VDD TEST POINTS 0 75VDD 0 25VDD ...

Page 63: ... 300mil EM78P221NAMS NAMJ SSOP 24 pins 209mil EM78P222NKS NKJ Skinny DIP 28 pins 300mil EM78P222NMS NMJ SOP 28 pins 300mil EM78P222NAMS NAMJ SSOP 28 pins 209mil Green products do not contain hazardous substances The third edition of Sony SS 00259 standard Pb contents should be less than 100ppm Pb contents comply with Sony specs Part No EM78P221 222 NxS xJ Electroplate Type Pure Tin Ingredient Sn 1...

Page 64: ...Dual in line SDIP 300 mil TITLE PDIP 24L SKINNY 300MIL PACKAGE OUTLINE DIMENSION Unit mm Scale Free File K24 Material Edtion A Sheet 1 of 1 A2 A1 e 1 12 13 24 Min Normal Max 5 334 0 381 3 175 3 302 3 429 0 203 0 254 0 356 31 750 31 801 31 852 6 426 6 628 6 830 7 370 7 620 7 870 8 380 8 950 9 520 0 356 0 457 0 559 1 470 1 520 1 630 3 048 3 302 3 556 2 540 TYP 0 15 Symbal A A1 A2 c D E1 E eB B B1 L ...

Page 65: ...t further notice B 2 24 Lead Plastic Small Outline SOP 300 mil TITLE SOP 24L 300MIL PACKAGE OUTLINE DIMENSION Unit mm Scale Free File SO24 Material Edtion A Sheet 1 of 1 b e Symbal A A1 b c E H D L e θ c Min Normal Max 2 350 2 650 0 102 0 300 0 406 TYP 0 230 0 320 7 400 7 600 10 000 10 650 15 200 15 600 0 630 0 838 1 100 1 27 TYP 0 8 ...

Page 66: ...e B 3 24 Lead Plastic Shrink Small Outline SSOP 209 mil TITLE SSOP 24L 209MIL PACKAGE OUTLINE DIMENSION Unit mm Scale Free File SSO24 Material Edtion A Sheet 1 of 1 A2 1 12 13 24 D Symbal Min Normal Max A 2 00 A1 0 05 A2 1 65 1 75 1 85 b 0 22 0 38 c 0 09 0 25 D 7 90 8 20 8 50 E 7 400 7 80 8 200 E1 5 00 5 30 5 60 e 0 65 L 0 55 0 75 0 95 L1 1 25 θ 0 8 ...

Page 67: ...l in line SDIP 300 mil TITLE PDIP 28L SKINNY 300MIL PACKAGE OUTLINE DIMENSION Unit mm Scale Free File K28 Material Edtion A Sheet 1 of 1 Symbal A A1 A2 c D E1 E eB B B1 L e θ Min Normal Max 5 334 0 381 3 175 3 302 3 429 0 152 0 254 0 356 35 204 35 255 35 306 7 213 7 315 7 417 7 620 7 874 8 128 8 382 8 890 9 398 0 356 0 457 0 559 1 422 1 524 1 626 3 251 3 302 3 353 2 540 TYP 0 10 A ...

Page 68: ...Lead Plastic Small Outline SOP 300 mil TITLE SOP 28L 300MIL PACKAGE OUTLINE DIMENSION Unit mm Scale Free File SO28 Material Edtion A Sheet 1 of 1 Symbal A A1 b c E E1 D L L1 e θ Min Normal Max 2 370 2 500 2 630 0 102 0 300 0 350 0 406 0 500 0 254 TYP 7 410 7 500 7 590 10 000 10 325 10 650 17 700 17 900 18 100 0 678 0 881 1 084 1 194 1 397 1 600 1 27 TYP 0 8 ...

Page 69: ...ic Shrink Small Outline SSOP 209 mil TITLE SSOP 28L 209MIL OUTLINE PACKAGE PACKA OUTLINE DIMENSION Unit mm Scale Free File SSO28 Material Edtion A Sheet 1 of 1 b e c Min Normal Max 2 130 0 050 0 250 1 620 1 750 1 880 0 220 0 380 0 090 0 200 7 400 7 800 8 200 5 000 5 300 5 600 9 900 10 200 10 500 0 630 0 900 1 030 0 650 TYP 0 4 8 Symbal A A1 A2 b c E E1 D L e θ E E1 A2 ...

Page 70: ...C RH 100 pressure 2 atm TD endurance 96 hrs High temperature High humidity test TA 85 C RH 85 TD endurance 168 500 hrs High temperature storage life TA 150 C TD endurance 500 1000 hrs High temperature operating life TA 125 C VCC Max Operating Voltage TD endurance 168 500 1000 hrs Latch up TA 25 C VCC Max operating voltage 150mA 20V ESD HBM TA 25 C 3KV ESD MM TA 25 C 300V IP_ND OP_ND IO_ND IP_NS OP...

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