3-26
Processor Interface
3.16.2 ERRDET1 - Error Detection 1
Address Offset: x04
Width:
32
Reset Value: x0000_0000
Access: Read/Write
Note: Individual bits may be cleared by writing a "1" to the corresponding bit position.
6
WR_INT_EN
0
PLB Slave write region interrupt enable.
0 - Disable
1 - Enable
Enables use of PLBSWRINT region. When the PLB address
falls within the 16KB region as programmed into the PLB-
SWRINT register, an interrupt will be generated to the CPC700
interrupt controller. System software may separately program
the interrupt controller to generate an interrupt to the processor
based on this condition or not.
See Section 3.16.17, “PLBSWRINT - PLB Slave Write Interrupt”
for information programming the PLB Slave Write Interrupt re-
gion.
7:31
0s
Reserved
Bit
Name
Reset
Value
Description
0
CPU_TT_ER
0
CPU Transfer Type/Size Error
0 - No Error Detected
1 - Error Detected
1
MEM_SEL_ER
0
Memory Select Error
(Error indicating access to non-existent memory)
0 - No Error Detected
1 - Error Detected
2
PLB_MSTR_ER
0
PLB Master Error
0 - No Error Detected
1 - Error Detected
3
PLB_SLV_ER
0
PLB Slave Error
0 - No Error Detected
1 - Error Detected
4
FL_WR_ER
0
Flash Write Error
0 - No Error Detected
1 - Error Detected
5
CPU_APE_ER
0
60x Address Parity Error
0 - No Error Detected
1 - Error Detected
Summary of Contents for CPC700
Page 10: ...Table of Contents x Table of Contents...
Page 16: ...Tables xvi List of Tables...
Page 28: ...1 12 CPC700 User s Manual Preliminary...
Page 72: ...3 36 Processor Interface...
Page 132: ...4 60 Memory Controller...
Page 184: ...5 52 PCI Interface...
Page 194: ...6 10 Clock Power Management and Reset...
Page 224: ...8 18 IIC...
Page 244: ...10 10 Interrupt Controller...
Page 246: ...I 11 2 JTAG...
Page 250: ...12 4 Processor Local Bus PLB...
Page 262: ...14 10 Register Summary...
Page 267: ...CPC700 User s Manual Preliminary...