IBM CPC700, User Manual

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CPC700 User’s Manual—Preliminary 3-15
3.11.2 PCI to Memory Byte Swapping
Two modes are available for transfers from the PCI bus to local memory. The default method preserves
byte lanes and the alternate method swaps byte lanes. A bit in the PLBMIFOPT register controls which
mode is in effect for all PCI to memory transfers. See Section 3.16.6, “PLBMIFOPT - PLB Master Interface
Options” for information.
3.11.2.1 Byte Lane Preservation
Preserving byte lanes is the default method for handling memory access from the PCI bus. In this method
PCI_BYTE0 corresponds to CPU/MEM_BYTE0 and is true for all PCI to local memory transfers regardless
of the number of bytes transferred. No address manipulation occurs, so addresses correspond directly to
PCI addresses. Bit ordering within bytes is preserved such that:
PCI_BYTE0[7:0] corresponds to CPU/MEM_BYTE0[0:7].
For example, if PCI_BYTE0[7:0] = 22 then CPU/MEM_BYTE0[0:7] = 22.
The following figure illustrates the byte preservation method of PCI to local memory accesses.
3.11.2.2 Byte Lane Swapping - Value Preservation
In the alternative method of memory access from PCI, the byte lanes are swapped such that PCI_BYTE0
corresponds to CPU/MEM_BYTE3, PCI_BYTE1 corresponds to CPU/MEM_BYTE2, etc. Byte lane swap-
ping is intended to preserve the value of 32-bit data as seen from both the PowerPC processor and the PCI
bus.
As in the default method, bit ordering within bytes is preserved:
PCI_BYTE3[31:24] corresponds to CPU/MEM_BYTE0[0:7] and PCI[31:0] = CPU/MEM[0:31]
Processor
PLB Byte Lanes
PCI
0 1 2 3 4 5 7 6
1 2 3 4 5 6 7 0
0 1 2 3
[0:7] [8:15] [16:23] [24:31]
[32:39] [40:47] [48:55] [56:63]
[7:0] [15:8] [23:16] [31:24]
(Big-Endian;
msb is bit 0)
(Little-Endian;
msb is bit 31)
Figure 6. Default Byte Preservation Method