IBM CPC700, User Manual

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CPC700 User’s Manual—Preliminary 3-3
Detailed information regarding the processor interface registers can be found in Section 3.16, “Processor
Interface Register Description”.
3.4 Processor Interface to Memory, PCI, and Peripherals
The CPC700 supports 1 full level of addressing pipelining on the processor bus and decodes the target of
processor accesses based on the address range of the transfer. All of the processor accesses are decoded
as one of the following:
•
System memory read (SDRAM/ROM)
•
System memory write (SDRAM/ROM)
•
DCR configuration read
•
DCR configuration write
•
PLB read (PCI or internal peripherals)
•
PLB write (PCI or internal peripherals)
The range of addresses that define the above accesses are defined by the address map detailed in the fol-
lowing tables.
PLBMTLEA1 24 R/W Processor-PLB Master Byte Swap Region 1 Ending Address
PLBMTLSA2 28 R/W Processor-PLB Master Byte Swap Region 2 Starting Address
PLBMTLEA2 2C R/W Processor-PLB Master Byte Swap Region 2 Ending Address
PLBMTLSA3 30 R/W Processor-PLB Master Byte Swap Region 3 Starting Address
PLBMTLEA3 34 R/W Processor-PLB Master Byte Swap Region 3 Ending Address
PLBSNSSA0 38 R/W PLB Slave No Snoop Region Starting Address
PLBSNSEA0 3C R/W PLB Slave No Snoop Region Ending Address
BESR 40 R/W PLB Bus Error Syndrome Register
BESRSET 44 W PLB Bus Error Syndrome Register Set (for test/verification
use)
Reserved 48
BEAR 4C R/W PLB Bus Master Error Address Register
Reserved 50
Reserved 54
PLBSWRINT 80 R/W Write Interrupt Region Base Address
Table 5. CPC700 Address Map - Processor View
Processor Address Range Description
PLB
Address
0 to
2G-1 h00000000
h7FFFFFFF System Memory
Typically reserved for local memory
2G to
4G-11M-1 h80000000
hFF4FFFFF PCI Interface* h80000000
hFF4FFFFF
Table 4. Offsets for Processor Interface Registers (Continued)
Register Offset R/W Description