IBM CPC700, User Manual

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CPC700 User’s Manual—Preliminary 7-9
7.2.1.5 Interrupt Enable Register
Three types of UART interrupts are enabled via the interrupt enable register (IER). Any of the three
interrupt types can be used to surface a UART interrupt to the CPC700 interrupt controller. Each interrupt
type can be enabled by setting its appropriate bit. Resetting bits 4 through 7 of the IER totally disables the
UART interrupt system. Disabling an interrupt prevents it from being shown as active in the IIR and
prevents it from signalling a UART interrupt to the CPC700 interrupt controller.
4, 5 and
6
Bit
4
Bit
5
Bit
6
Bits 5 and 6 are used to indicate the interrupt priority as shown below. Bit 4 is always 0 in
16450 mode. In FIFO mode, when a timeout interrupt is pending, bits 4 and 5 are set to
logic 1.
Priority
Level Interrupt Type Interrupt Source Interrupt Reset
Control
0 1 1
1st Receiver Line
Status Overrun, Parity or Framing
Error, or Break Interrupt Read LSR
0 1 0
2nd Received Data
Available Receiver data available or
trigger level reached. Read RBR, or FIFO
drops below trigger
level.
1 1 0
2nd Character timeout
Indication No characters have been
removed from or input to the
receiver FIFO during the last
four char. times and it
contains at least one char.
during this time. Read RBR
0 0 1
3rd Transmitter Holding
Register Empty Transmitter Holding Register
Empty Read IIR (if source
of interrupt) or write
THR
0 0 0
reserved
7
0
Interrupt is pending. IIR contents may be used as a pointer to the appropriate interrupt
service routine.
1
No interrupt is pending.
Table 76. Interrupt Enable Register Description
IER Bits
Bit # Value Description
0 0
Always 0
1 0
Always 0
2 0
Always 0
3 0
Always 0
4
reserved
Table 75. Interrupt Identification Register Description (Continued)
IIR Bits
Bit # Value Description