IBM CPC700, User Manual

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CPC700 User’s Manual—Preliminary 1-1
Chapter 1. Introduction
1.1 Overview
The CPC700 Memory Controller and PCI Bridge (CPC700) contains a bridge from the PowerPC processor
to the PCI bus, as well as a high-speed memory controller, internal peripherals, and control for external
ROM and external peripherals. The CPC700 is meant to be a general purpose solution to the problem of
interfacing a high performance, superscalar, PowerPC 603e, 740, and 750 microprocessors to any PCI
bus. These microprocessors feature multiple, independent execution units and large onboard instruction
and data caches.
The CPC700 adds the following features:
• PowerPC 60x/7xx bus with operation to 66 MHz (CPC700-66) or to 83 MHz (CPC700-83).
• Synchronous DRAM interface operating at the processor bus speed.
- 64-bit interface for non-ECC applications.
- 72-bit interface (64 bits of data plus 8 checkbits) for ECC applications.
- ECC protection applied to address as well as data.
• ROM/SRAM/External Peripheral Controller.
- Flash ROM/Boot ROM interface.
- Direct support for 8-, 16-, 32-, or 64-bit SRAM or external peripherals.
• PCI Revision 2.1 Compliant Interface (32-bit, 25 to 66 MHz).
- PCI Bus Interface may be configured to operate synchronously or asynchronously to the processor
bus (synchronous clock is limited to 33 MHz PCI bus operation).
- Internal PCI Bus Arbiter for up to six external devices at PCI bus speeds up to 33 MHz.
• Interrupt Controller supports interrupts from a variety of sources.
- Internal Peripherals (UARTs, IICs, Timers).
- External Peripherals.
- ECC correctable error.
- PCI writes to PCI Command Register.
- PCI writes to a specific memory address range.
• Programmable Timers.
• Two 2-wire 8-bit Serial Ports (16550 compatible UART).
• Two IIC interfaces.
• Supports JTAG for board level testing.
• Byte swapping supported for bi-endian operation.
With versions that support processor bus speeds up to 66 MHz and 83 MHz, the CPC700 allows the Pow-
erPC to realize its full potential. To complement this operation, the CPC700 memory subsystem keeps up
with the processor by providing an optimized memory controller. The memory architecture focuses on per-
formance, cost, and board space. Support is provided for 16-bit wide SDRAMs, reducing the number of
memory devices that are needed to support the 64-bit PowerPC bus size. The device will support four
banks of SDRAM, with up to 512 Mbytes per bank.