IBM CPC700, User Manual

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5-4 PCI Interface
5.5 PCI Interface Address Maps
The PCI interface supports a flexible, programmable address map.
5.5.1 PLB Address Map
The PCI interface responds as a target on the PLB bus in several address ranges. These ranges allow the
processor (a PLB master) to configure the PCI interface, and to cause the PCI interface to generate Mem-
ory, I/O, Config, Interrupt Acknowledge, and Special cycles on the PCI bus. Table 41. shows the address
map from the view of the PLB (i.e., as decoded by the PCI interface as a PLB slave).
PCICACHELS 0C R Cache Line Size
PCILATTIM 0D R/W Latency Timer
PCIHDTYPE 0E R Header Type
PCIBIST 0F R Built In Self Test Control
PCIBAR0 10 R Unused BAR 0
PCIPTM1BAR 14 R/W PTM 1 BAR
PCIPTM2BAR 18 R/W PTM 2 BAR
Reserved 1C - 27 Unused BARs
Reserved 28 - 2B Unused Cardbus
PCISUBSYSID 2C R/W PCI Subsystem ID
PCISUBSYSVENDID 2E R/W PCI Subsystem Vendor ID
Reserved 30 - 3B Unused or Reserved
PCIINTLN 3C R/W Interrupt Line
PCIINTPN 3D R Interrupt Pin
PCIMINGNT 3E R Minimum Grant
PCIMAXLTNCY 3F R Maximum Latency
PCIBUSNUM 40 R Bus Number
PCISUBBUSNUM 41 R Subordinate Bus Number
PCIDSCCNT 42 R Disconnect Counter
PCIARBCNTL 47 - 44 R/W PCI Arbiter Control
PCIERREN 48 R/W Error Enable
PCIERRSTS 49 R/W Error Status
PCIBRDGOPT1 4B - 4A R/W Bridge Options 1
SESR 4F - 4C R/W PLB Slave Error Syndrome Register
SEAR0 53 - 50 R PLB Slave Error Address Register 0
SEAR1 57 - 54 R PLB Slave Error Address Register 1
Reserved 5B - 58
Reserved 5F - 5C
PCIBRDGOPT2 61 - 60 R/W Bridge Options 2
Table 40.PCI Interface Configuration Register Offsets (Continued)
PCI Config Register Offset R/W Description