HUAWEI MC509 Series CDMA LGA Module
Hardware Guide
Description of the Application Interfaces
Issue 02 (2013-05-06)
Huawei Proprietary and Confidential
Copyright © Huawei Technologies Co., Ltd.
42
Table 3-10
Signals on the digital audio interface
Pin
No.
Pin Name
I/O
Description
DC Characteristics (V)
Min.
Typ.
Max.
5
PCM_SYNC
O
PCM interface sync
–0.3
2.6
2.9
6
PCM_DIN
I
PCM I/F data in
–0.3
2.6
2.9
7
PCM_DOUT
O
PCM I/F data out
–0.3
2.6
2.9
8
PCM_CLK
O
PCM interface clock
–0.3
2.6
2.9
The MC509 PCM interface enables communication with an external codec to support
linear and
μ-law format. The PCM_SYNC runs at 8 kHz with a 50% duty cycle.
Figure 3-20
Circuit diagram of the interface of the PCM (MC509 is used as PCM master)
PCM_SYNC: Output when PCM master
PCM_CLK: Output when PCM master
It is recommended that a TVS be used on the related interface, to prevent electrostatic
discharge and protect integrated circuit (IC) components.
Data only edition does not support the voice function.
When the MC509 module works on master mode, PCM_CLK and PCM_SYNC pins are in
the output status.
Primary Mode
On Primary mode MC509 provides a 16-bit linear o
r μ-law, with short-sync and 2.048
MHz clock (on the PCM_CLOCK pin).
Module
(DC
PCM_SYNC
PCM_SYNC
PCM_DIN
PCM_DIN
PCM_DOUT
PCM_DOUT
CODEC
PCM_CLK
PCM_CLK
E)
