Page 1: ...HP Computer Systems HP 98640A 7 Channel Analog Input Interface Hardware Installation and Reference Manual FIIOW HEWLETT PACKARD ...
Page 2: ...HP Computer Systems HP 98640A 7 Channel Analog Input Interface Hardware Installation and Reference Manual r J HEWLETT a 1 II PACKARD ...
Page 3: ...eight prepaid Repairs necessitated by misuse of the equipment or by hardware software or interfacing not provided by Hewlett Packard are not covered by this warranty HP warrants that its software and firmware designated by HP for use with a CPU will execute its programming instructions when properly installed on that CPU HP does not warrant that the operation of the CPU software or firmware will b...
Page 4: ...r other card if the cards are in adjacent slots Since the HP 98640A must be installed in the lower of paired slots this occurance is likely There are two possible solutions The recommended solution is to apply an insulating material such as electricial tape to the upper surface of the RFI shield on the processor or other card The second while more difficult is equally effective Always place the AD...
Page 5: ...ARDWARE INSTALLATION AND REFERENCE MANUAL Fliii HEWLETT PACKARD Card Assembly 98640 66501 Date Codes A 2 419 B 2 420 HEWLETT PACKARD COMPANY Roseville Networks Division ManuaIPartN 98640 90001 E0784 Printed in U S A July 1984 8000 Foothills Boulevard Roseville Callifornia 95678 ...
Page 6: ...anual will contain new information as well as updates FIRST EDITION July 1984 NOTICE The information contained in this document is subject to change without notice HEWLETT PACKARD MAKES NO WARRANTY OF ANY KIND WITH REGARD TO THIS MATERIAL INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE Hewlett Packard shall not be liable for errors contai...
Page 7: ...use Calculating power requirement5 Component installation Boot up ID number Switch Set in9s Factory Settings Interrupt Level Inserting the card Where How Removal Checking a new A to D card Attaching the wire termination aS5embly Cabl i nB Wi re Connection Removal Operational Con5iderations Return Shipment THEORY OF OPERATION Power and Timing Powelr Supply System Clock iii vi i 1 1 1 1 1 2 1 2 1 2 ...
Page 8: ...uitry 3 13 Generating Control Signals 3 13 Stopping the Counter 3 14 Conversion Cycle Timing 3 17 The BUSY eyeIe 3 18 The Internal Pacing Timer 3 19 External Pacing 3 20 Digi tal Backplane Circui try 3 20 Select Code 3 20 The Backplane Handshake 3 21 Addressing 3 21 Reset 3 22 Backplane Data Bus 3 22 Reading From the Card 3 22 Wri ting to the Card 3 22 Interrupt5 3 23 Sequence of Operations 3 23 T...
Page 9: ... Sequ1ence 5 3 Test 5 Performed 5 4 Prograrn run 5 4 Insti lIed ADCs 5 4 Set I epet i t ions 5 4 Pace Timer Test 5 4 Select Readings to Display 5 4 Run Error Reporting 5 5 Succes 5ful Verification 5 5 On Failure 5 5 Error Codes 5 6 PARTS LISTS Organization 6 1 Ava i labi 1 i t y 6 1 A to D card 6 2 wire tl rmination assembly 6 5 test a 5sembly 6 6 DIAGRAMS Resistor network 7 2 Component Location A...
Page 10: ...follow on products you may have a future need for One product that is already available is the HP 98645A Measurement Library The library s set of subroutines that you can call from high level languages may save considerable development time The following languages can call routines from the library BASIC 3 0 and 2 0 with 2 1 extensions Pascal 3 0 2 1 and 2 0 Contact your Hewlett Packard sales repr...
Page 11: ...ting points MOS structures are also susceptible to dielectric damage due to high fields The resulting damage can range from complete destruction to latent degrada tion Small geometry semiconductor devices are espe cially susceptible to damage by static discharge The basic concept of static protection for electronic components is the prevention of static build up where possible and the quick remova...
Page 12: ... erif that the product is onfiJ rurt d to match thl a ailahll main power source per tht input powt r confj urati n in tructions provided in this manual If this product is til hI l lll rl ll l d 1 an auto transf rmer tfor oltClgt n duct ion I milk sun tIll wmmon tl rminal is connected til tht l II1h t rminal of tht Illalll powt r SCHliTt SERVICING viii Any servicing adjustment maintenance or re pai...
Page 13: ...face s four input voltage ranges will accommodate signal sources ranging from control cir cuits to thermocouples The voltage ranges are determined by the amplification of the input voltage by the card Y ou can select any of 4 gains for any channel The four gain factors are 1 8 64 and 512 This allows the ADC integrated circuit IC on the card to always see a voltage between 0 and 10 volts The rest o...
Page 14: ...t equipment you received When you unpack the cards you may want to refer to the following lists Options Standard Product A to D card part number 98640 66501 Wire termination assembly WTA part number 98640 66502 Test assembly part number 98640 67950 This installation manual part number 98640 90001 Verification option only one may be selected VERIFICATION OPTIONS 001 Deletes test assembly 630 Adds v...
Page 15: ...ur nearest Hewlett Packard Sales and Service office listed at the back of this manual for manual update information SPECIFI ATIONS ElectricaJ Power Requiirements 672W 12V 228W 12V 2 570W 5V 3 5 Watts total Input overvolltage protection Transorbs redirect voltage in excess of 15 volts to ground Input resistance each channel 1OOmegohms power on WARNING Each input is routed through a 1k one thousand ...
Page 16: ...el s inputs should not equal or exeed full scale see below 1 1 GAIN 1 INPUT VOLTAGE RANGE 1 1 1 1 1 1 1 to 10V 1 1 1 8 1 to 1 25V 1 1 1 64 1 to 156mV 1 1 1 512 1 to 19 5mv 1 Other sampling characteristics are listed in table 1 1 Control Minimum external trigger pulse width 2 3 microseconds Trigger voltage 2 to 50volts trigger voltage must not go below ground 1 4 ...
Page 17: ... 305uV 38 1UV 4 77uV 5mV 600uv lOOUV 18uv 7 3mV 915uV 152UV 24uv 18mV 3mV 250uV 75uV 400mV usec 50mV usec 4mV usec 40uV usec 20k sec 20k sec 14k sec lk sec 55k sec 55k sec 55k sec 55k sec By averaging readings noise can be reduced to less than one least significant bit Isb These figures are based on an HP 98640A whose data were processed and controlled by routines from the HP 98645A Measurement Li...
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Page 19: ... edges or the plastic levers extractors in the corners next to the right angle posts Do not touch the gold plated contacts at the end of the card opposite the right angle posts If you do get a fingerprint on the gold plated contacts or the right angle posts clean them with a lintless tissue moistened with a small amount of isopropyl alcohol CAUTION Never clean the contacts or the right angle posts...
Page 20: ... are used by the operating system to associate the card with an application program SWITCH SETTINGS The A to D card has a DIP dual in line package block of switches SWl located as shown in figure 2 1 Switch numbers are on the switch block These switches control the card s address and the priority level of any interrupt the card transmits You must select part of the address for the card The portion...
Page 21: ...2 1 Standard device assignments STANDARD SELECT CODE ASSIGNMENTS SELECT ASSIGNED SELECT ASSIGNED CODE DEVICE CODE DEVICE 8 98624 19 9 98626 20 98628 10 21 98629 11 98623 22 12 98622 23 13 24 14 98625 25 15 CUSTOM 26 I O 1 27 16 CUSTOM 28 98627 COLOR I O 2 29 color cont 17 30 18 98640 31 2 3 ...
Page 22: ...W1 Switches I SELECT msb 12345 Isb I CODE 01000 01001 01010 01011 01100 01101 01110 01111 10000 10001 10010 10011 8 9 10 11 12 13 14 15 16 17 18 19 HARDWARE INTERRUPI LEVELS SWl Switches 76 INTERRUPl LEVEL 10100 10101 10110 10111 11000 11001 11010 11011 11100 11101 11110 11111 00 3 01 4 10 5 11 6 Table 2 2 SWI switch settings 20 21 22 23 24 25 26 27 28 29 30 31 Choose a select code for the A to D ...
Page 23: ...Series 200 computers a cover plate is not attached to the A to D card so you can actually seat the card in the wrong slot How To install the A to D card pickup the card by the corners where the extractors plastic levers are at tached Be sure the component side of the card is up Check for any fingerprints on the contacts of the top c01nponent side and bottom of the card Clean the contacts as necess...
Page 24: ...rectly installed the card s extractors will be folded flat against the card with one edge of each extractor touching or almost touching the card cage Removal ICAUTION I The following instructions for removing the A to D card assume you have properly powered down the com puter and removed the wire termination assembly as ex plained in Section 5 under the heading DISCONNECTING THE WTAII If you have ...
Page 25: ...e holes in the card cage Tighten both screws simultaneously or they may bind Tighten until the cover plate is seated against the card cage s outside edges Tighten only finger tight over tightening may strip the threads of a thumbscrew or the card cage ICAUTION I The right angle posts must properly engage the mating connectors on the wire termination assembly There is a connector for every post and...
Page 26: ...in relief for the wires attached to the wire termination assembly The wire termination as sembly is not designed to support the weight of a large cable or long lengths of individual conductors WARNING THIS INPUT INTERFACE WILL APPEAR TO BE A LOW RESISTANCE PATH TO GROUND FOR ANY VOLTAGE MORE THAN I 5 VOLTS ABOVE OR BELOW GROUND WHEN POWER TO THE COMPUTER IS TURNED OFF EACH INPUT IS SHORTED TO GROU...
Page 27: ...CHANNEL3 12 INPUT D 13 GROUND COMPONENT D I SIDE D 14 INPUT CHANNEL4 15 INPUT II D I D D 16 GROUND 17 INPUT 18 INPUT CHANNEL5 D 19 GROUND D D 20 INPUT CHANNEl 6 21 INPUT D 22 GROUND D D 23 INPUT CHANNEL 7 24 INPUT D 25 GROUND D 26 NOT CONNECTED D 27 NOT CONNECTED D 28 5V 50ma D 29 EXTERNAL PACE INPUT EPCON D 30 INTERNAL PACE DISABLE lPACDA i I m Figure 2 3 Wire termination assembly inputs 2 9 ...
Page 28: ...e ground loops or overvoltage on an input A ground loop will contribute unwanted noise to the input voltage Also if the difference in potential between chassis grour d and the voltage source s ground is high enough the current limiting resistor on the wire ter mination assembly may be damaged Once you have finished adding the wires to the wire t ermination assembly and the voltage sources you may ...
Page 29: ...6I J __ _ lJ 1 C CHANNEL 7 Q GND TERMINAL l7 Removal Figure 2 5 Wiring a channel s inputs WARNING THESE INSTRUCTIONS FOR REMOVING THE WIRE TERMINATION ASSEMBLY ASSUME THE COMPUTER AND THE VOLTAGE SOURCES BEING SAMPLED ARE TURNED OFF IF THEY ARE NOT READ APPENDIX A BEFORE TURNING THE POWER OFF 2 11 ...
Page 30: ...the right angle posts on the A to D card Do not use the wire termination assembly to hang up your wire bundle The weight of the wire may cause damage to the assembly or the wires might slip out of the receptacles OPERATIONAL CONSIDERATIONS The bottom of the wire termination assembly is exposed do not allow conductors to come in contact with the bottom of the assembly when it is installed If the co...
Page 31: ...ded Pack the product in the original packing material Please observe the anti static electrical procedures described at the front of this manual under the heading Safety Considerations If the original pack ing material is missing you may use an equivalent commercially available anti static packing material You may a lso have a reliable commercial packing company repack the item Be sure to advise t...
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Page 33: ...al sections essentially an annotated timing diagram Analog ipeline summary of the interrelationships of successive analog readings Note that in this section we use the term analog read to refer to a read from one of the eight analog input channels on the A to D card as contrasted with a read or write from or to the status ID or pace timing register In our discussion we will frequently refer to int...
Page 34: ...IAL I __ 1 TO t SINGLE ENDED SAMPLE AND HOLD I I v3 CONVERTER ADDRESS LATCH 2 PACE TIMING REGISTER ADDR ADDR L ____ r w a o o ID 16 BIT DATA BUS STATUS REGISTER REGISTER A t DATA FLlP FLOP v BACKPLANE 1 ABSOLUTE VALUE CIRCUIT I v1 ANALOG T DIGITAL CONVERTER 12 Figure 3 1 A to O card functional block diagram 3 2 ...
Page 35: ...available for internal pacing Note that the clock on the card is not synchronized with the host computer s clock REGISTERS To make an analog read from the A to D card you must specify a register address in your read request The register address encodes the channel you want to read and the gain at which you want to read it in the following way Address for Address for Address for Address for ChannE ...
Page 36: ...e D data These twelve bits give a binary value for the magnItude of the voltage Bit 11 is the most significant bit MSB bit 0 is the least significant bit LSB This is the raw value provided by the ADC on the card it has not been adjusted for gain The meanings of these bits are covered in greater detail in the remainder of this section Pace Timing Register The pace timing register controls the pace ...
Page 37: ...e card and indicate which interrupt line is ac tivated when an interrupt occurs The meanings of the bits are Bit Bit Interrupt Interrupt 5 4 Level Line 0 0 3 IR3 0 1 4 IR4 1 0 5 IR5 1 1 6 IR6 ANALOG CIRCUITRY The analog circuitry on the A to D card takes a differential input voltage from one of the eight analog input channels amplifies it if you tell it to and prepares it for conversion to a digit...
Page 38: ...n the breakdown state In the case of an overvoltage condition the input voltage will exceed the zener value plus 0 7 volts This will forward bias the appropriate diode in one of the arrays and allow current to flow through the zener diode At this time the voltage at the diode array will not exceed approximately 10 7 volts and the rest of the voltage will be dropped across the lOaD ohm resistor Thi...
Page 39: ... its input at the same voltage as its input When an op amp s output voltage is fed back into one of its inputs the op amp can approach its goal equal voltages at the inputs by varying its output in some suitable manner In the case of the PGA the differential in put voltages are brought into the inputs of the two op amps The output of each op amp is fed back into its input GAIN OF 1 For a gain of 1...
Page 40: ...alog Input Interface INPUT INPUT 3 7 2 V 4_2 4 55 5K 31 5K 28K _1 v _2 u Q 3 4 AA4 4 1K ADDRESS 8K 1 K AA5 4 1 3 2 1 X1 X8 X64 X512 4 28K 431 5K 4 255 5K 2 7 L 3 V VOUT Figure 3 3 Programmable gain amplifier 3 8 ...
Page 41: ...at their respective and in puts When the circuit has reached equilibrium the difference between the op amp output voltages will have been amplified by the appropriate gain factor Let s look at an example Example Assume that your A to D card is connected to a device that is supplying 3 01 volts to the input of a channel and 3 00 volts to the input Assume also tha t you are measuring that voltage at...
Page 42: ...oltage coming from the positive op amp of the PGA Vin due to the resistive divider network in U24 Similarly the voltage at the negative input of op amp U32 is half way between the output voltage of U32 Vout and the voltage coming from the negative op amp of the PGA Vin Op amp U32 drives its output pin 7 so that the voltages at its negative input pin 2 and positive input pin 3 are equal the resulti...
Page 43: ...R3 CR4 and CR6 a capacitor C43 and 4 resistors R7 R15 and two resistors in U24 The circuit is shown schematically in figure 3 6 The output of the absolute value circuit is driven by the more positive of the two op amps One of the op amps U22 is a unity gain buffer and the other U23 is a unity gain inverter Thus one of the outputs will always be positive Diodes CR3 and CR4 separate the negative and...
Page 44: ...f the polarity signal from going much below ground The 270 pf capacitor C43 in the feedback loop of the inverting op amp is used as a low pass filter to reduce high frequency noise in the circuit 5 POLARITY OUTPUT 10K 270 pf 10K I S H OUT I Figure 3 6 Absolute value circuit Analog to Digital Converter ADC The ADC U65 receives its analog input from the absolute value circuit and converts it to a di...
Page 45: ...clock cycles Since the digital conversion circuitry of the A to D card runs on the same clock signals that the A to D chip uses the digital circuitry simply waits an ap propriatl number of clock cycles before requesting the results of the the conversion from the chip First J tuead The ADC chip doesn t have enough data lines to output all of the data bits at once so two reads are needed to get the ...
Page 46: ...alf a clock cycle later Since the PROM outputs are unstable only on the positive clock edge the control signals clocked into the flip flop are always clean and the outputs of the flip flop are always free of glitches The A to D card makes use of both buffered and unbuffered control signals To differentiate be tween them the names of the buffered signals have IIBUII added to the front of the unbuff...
Page 47: ...17 18192021222324252627282930 I I _____________________ u u ________________________rl______________________ r j BUSY CYCLE IA6 SI___________ CONVERSION STATE MACHINE MAY BE HALTED AT EITHER OF THESE POINTS DTACK I I ADDRESSG ADDRESSG ___ BUSY L BUSY I LACH ALSO I SEE ABOVE Figure 3 7 Control signal timing PROM U68 and BUSY state machine 3 15 ...
Page 48: ...1121314151617 18192021222324252627282930 1 u u _______________________rl _____________________ r J BUSY CYCLE IA6 Slo ________ CONVERSION STATE MACHINE MAY BE HALTED AT EITHER OF THESE POINTS DTACK I I ADDRESSG ADDRESSG L ____ BUSY L BUSY I LACH ALSO I SEE ABOVE Figure 3 7 Control signal timing PROM U68 and BUSY state machine 3 16 ...
Page 49: ...nd the inverted EXTPAC input into U92 stops the counter un til the external pacing circuit lets the external pacing input go low again b The internal pacing timer uses the ENDCT signal to stop the counter In this way the pacing timer can stop the conversion cycle to let the programmed pace interval elapse between read ings The pacing timer holds ENDCT high until the timer counts up to FFFF hex at ...
Page 50: ...l continue On the next cycle BUC D will go low followed by BUWR BULACH and BUSAMP one cycle later As a result conversion begins on the voltage held by the sample and hold circuit in addition the polarity and overrange signals POLAR and OVD are clocked into the flip flops in U96 After allowing time for the conversion to complete the START signal goes high This resets the counter to 0 causing the PR...
Page 51: ...oes low again to reload the timer The carry bit of the most significant counter U47 drives the ENDCT signal This signal is used to restart the Conversion state machine counter after the programmed pace interval has elapsed ENDCT remains high while the pacing timer counts up toward FFFF When the timer reaches FFFF ENDCT is driven low A typical conversion cycle starts off with BUSY set high by an an...
Page 52: ...PACEN control signal to stop or start the Conversion state machine at the times that are appropriate for external pacing Ifa voltage is applied at the external pace input it sends EXTPAC high With f XTPAC high PACEN will stop the counter when it goes high at clock cycle 15 of the conversion cycle see figure 3 7 Once stopped the counter will not continue until the voltage at the external pace input...
Page 53: ...l drive flip flop U46A high and its Q output will go low This low output is designated the TACH signal and it drives the DTACK signal on the backplane low When the CPU removes the card address from the backplane the ININT signal goes low This clears both flip flops in U46 and leaves the circuit ready for another I O operation Addressing The several different operations that can be done on the A to...
Page 54: ...the Conversion state machine to cycle 0 the WAIT state In the second path CLR2 clears the BUSY and ADDRESSGRAB flip flops U83 The soft reset does not affect the interrupt control Backplane Data Bus Two hi directional buffers U38 and U29 drive the backplane data bus Backplane signal BR W controls the direction of the data flow The data buffers are enabled by BUDS BLDS and IIMA lIMA must be valid fo...
Page 55: ... writing to bit 7 of the status register as discussed above the interrupt enable flip flop U93B activates one of the two enable pins of U79 When the BUSY signal goes low activating the other enable pin of U79 the appropriate backplane interrupt line IR3 IR4 IRS or IR6 goes high generating an interrupt to the CPU SEQUENCE OF OPERATIONS What follows is a summary of the operation of the A to D card I...
Page 56: ... as soon as BUSY goes high again You can determine when that happens by checking bit 6 of the status register or by repeatedly checking bit 15 of the returned analog data word 1 0 WAIT goes low 1 5 BURD goes low This enables the transfer of the 4 most significant bits from the ADC 2 5 BUSAMP goes high This has three effects The sample and hold circuit starts sampling The polarity bit the overrange...
Page 57: ...o s high 30 0 As a result the counter resets to O This puts WAIT high and starts the conversion cycle over agaIn THE ANALOG PIPELINE The analog pipeline is implicit in the foregoing theory of operation now we will make it explicit If you follow the sequence of operations of the A to D card closely you will see that the result you get back when you make an analog read does not come from the address...
Page 58: ...plane for the full 18 microseconds and the backplane simply doesn t allow that two microseconds is about all that is available at a time By breaking the analog read process down into a three stage pipeline the card can always be able to release a reading and take in a new address in that 2 microsecond window Once you understand that the pipeline exists the effect it has on the way you take reading...
Page 59: ... Pascal If you ve determined that assembly language is the right language for your application read on We assume that you have a solid working knowledge of MC6 8000 assembly language and the Pascal operating system Refer to the Pascal 2 0 System Designer s Guide part number 09826 90074 for more information We also assume that you have absorbed the information in Section 3 of this manual particular...
Page 60: ...the minus signs indicate negative true For example if your read request specified a register address of 86 the A to D card would break down that address as follows A6 1 analog read A5 A4 o 1 gain 8 A3 A2 A1 011 channel 3 AO o not used The value returned by an analog read is the voltage for the channel and gain specified tWQ ana og r adurevicm Thus you must take n 2 readings to get the n values tha...
Page 61: ... the major factors affecting accuracy is noise Later in this section we will devote several para graphs to dealing with noise Another major factor affecting accuracy is input offset voltages We will deal with input offset voltages here CALIBRAT ON Most of the A to O card s input offset voltage is caused by operational amplifiers op amps on the card You ca n correct for most of these offsets by cal...
Page 62: ...nary not two s compli ment form and that zero may have positive or negative sign polarity The polarity of zero is caused by offsets which are too small to measure but not too small to detect For the mathematical operations described in the calibration procedures normalize zero by removing the sign NOTE Most high level languages do not permit signed zero O in a numeric variable You will have decide...
Page 63: ...truncate the product to an in teger This corrected product is the Derived_PGA_Correction E Subtract Derived_PGA_Correction from Partly _ Corrected_Reading The difference is Calibrated_Reading Since this was a subtraction of signed numbers not absolute values the sign polarity will be correct NOTE Calibrated_Reading may be less than equal to or greater than Uncalibrated_Input_Reading With the corre...
Page 64: ...rude_Offset and Uncalibrated_Input_Reading are real numbers Roughly_Corrected _Reading may be less than equal to or greater than Uncalibrated _Input_Reading GAIN UNCALIBRATED QUICK CALIBRATION WORST CASE DETAILED CALIBRATION WORST CASE MEASUREMENT LIBRARY CALIBRATION WORST CASE Table 4 1 Comparison of offset ranges 1 OFFSET RANGE 1 1 I 1 1 8 64 512 1 I PERCENT OF FULL SCALE 1 1 O 32 O 39 O 96 5 6 ...
Page 65: ...re closely See tables 4 1 and 4 2 To convert to a voltage multiply Roughly_Corrected_Reading by the Isb value for the gain used to read the input channel The sign indicates the polarity of the voltage OVERRANGES Normal modle If all 12 data bits bit 0 to bit 11 are set to 1 a normal mode overrange has occurred You may be able to avoid this problem by taking subsequent readings at a lower gain Commo...
Page 66: ...src gain gain index src VAR value raw_data src src src END def adcfastread adcfastread def adcfastread read adc module initialization routine adcfastread adcfastread rts If called from Pascal with normal checking enabled no range checking required on parameters Stack Frame At Entry 16 a6 select code 14 a6 chan 12 a6 gain 8 a6 pointer to value 4 a6 return address a6 stack frame SP register utilizat...
Page 67: ...ent add in reading register offset get the base address add in the register offset get 3 1 counter to clear pipeline read the card repeat until busy bit 15 is clear do this 3 times to clear the pipeline get the address of value stuff the value return to main program get the return address clear the stack return This routine ignores all readings taken when the busy bit is high See the instruction l...
Page 68: ...etect this by comparing readings taken from the same channel at high and low sample rates over equal amounts of time If your high speed samples found voltages that are higher or lower than you found with your low speed samples you may have a problem with an alias Increase the number of samples of the channel The paragraphs above are not a complete discussion of measurement techniques They are inte...
Page 69: ...lly paced readings and bursts of externally triggered internally paced readings Sil J read llg The idea behind taking single externally paced readings is that you keep EPCON high until you want to take a reading set it low only long enough to take the reading and then set it high again The steps in taking a single reading are 1 Set IPACDA high IPACDA will remain high for the duration of externally...
Page 70: ...Iowan appropriate amount of time after EPCON goes low This circuit uses the 5 volt power supply from terminal 28 of the wire termination assembly WIRE TERMINATION ASSEMBLY RECPTICALES t29 EXTERNAL PACE INPUT EPCON 1N 914 J TYPICAL 0 OPEN TO START 7 30 READING INTERNAL PACE DISABLE lPACDA 100 PF I 28 5V Figure 4 1 IPACDA timing circuit for externally paced burst readings Combinations You can combin...
Page 71: ... to use READIO and WRITEIO statements as the system 10 handlers such as STATUS CONTROL OUTPUT ENTER do not recognize this interface Remember that the pace and analog data registers on this card are 16 bit registers To transfer 16 bits of data to from the card simply specify a negative select code in the READIO WRITEIO statement The following program segment writes a 16 bit value to the pace regist...
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Page 73: ...ces for the peripherals and software for your computer a Keyboard b Video display c Disk Drive d Diagnostic Diskette to fit your disk drive 3 5 inch disk part number 98640 13301 or 5 25 inch disk part number 98640 13601 e Test Assembly part number 98640 67950 Installin J test assembly DISCONNECTING THE WTA If you have a lready installed the wire termination assembly WTA you will have to power down...
Page 74: ...t of your way Do not allow long lengths of wire to dangle from the termina tion blocks on wire termination assembly as the wires may be pulled free INSTALL PERIPHERALS Attach any peripherals required to run this test The instructions for installing a peripheral in your system are included in the peripheral s documentation or your computer s manual The peripherals required to run the verification p...
Page 75: ...ishes loading it will transfer control to the verification program liSTARTA There is no command interpreter so if the verification program ever terminates the computer must be re booted to restart the verification program Also there is no sub routine to permit scrolling the screen back SEQUENCE The verification program will ask you a few questions Once the questions have been answered the verifica...
Page 76: ... with the select code If all responses are negative the verification program branches to the repeat program question SET REPETITIONS If any card tests are to be done the verification program then asks Specify Repetitions 0 Repeats Forever Number of Times to Repeat default 1 The tests are repeated the specified number of times looping forever if 0 or a negative number is specified If the verificati...
Page 77: ... NOTE Always repeat the test if the error code reported is 860 Offset out of range Transient noise can cause such an error Successful Verification When an A to D card passes the test all you will have to do is On Failure 1 Remove the verification program disk 2 Power down your system 3 Remove the test assembly by pulling it straight back away from the card cage to avoid bending the mating post on ...
Page 78: ...elect code 838 Illegal name 850 Unsupported gain 851 Pace out of range 852 Repeat specification error 853 Illegal channel number Message Number 854 855 856 857 858 859 860 Meaning Not allowed in inter rupt mode Common mode overrange Normal ADC overrange Pace timing error Unsupported units Max number of names exceeded Offsets out of range card deffective or calibration channel not shorted Table 5 1...
Page 79: ...CPU word access to odd address 12 CPU bus error 13 Illegal CPU instruction 14 CPU privilege violation Message Number 15 16 17 18 19 20 21 22 23 24 25 25 27 98640A Analog Input Interface Meaning Bad argument SIN COS Bad argument Natural Log Bad argument SQRT Bad argument real BCD conversion Bad argument BCD real conversion Stopped by user Unassigned CPU trap Reserved Reserved Macro parameter not o ...
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Page 81: ...rence designation of the part The Hewlett Packard part number Part check digit CD Total quantity QTY Description of the part Code number identifying a manufacturer of a part The manufacturer s part number A VAILABILITV Contact your local HP Sales and Service office if you need to order parts They can also explain to you how doing your own repairs may affect your warranty When you order please give...
Page 82: ...CITOR FXD 0IUF 10X 100VDC CER 8480 CAPACITOR FXD 0IUF IOX 100VDC CER 2f 1480 CAPACITOR FXD olur IOX 100VDC CER 28480 CAPACITOR FXD 0IUF 10X 100VDC CER 28400 CAPACITOR rXD OIUF IOX 100VDC cr R 29400 CAPACITOR FXD 01UF 10X 100VDC CER 20400 CAPACITOR FXD 01UF IOX 100VDC CER 280480 CAPACITOR FXD 0IUF 10X 100VDC CER 28400 CAPACITOR rXD 15UF lOX 20VDC TA 562B CAPAC ITOR FXD l 5UF l0X 20VDC TA 5 289 CAPA...
Page 83: ...R I G 01295 IC CNTR nL LS BIN SYNCHRO POS EDGETR IG 01295 IC CNTR TTL LS BIN SYNCIiRO POS EDGE TR I G 01295 IC FF TTL LS D TYPE POS EDGE TRIG PRL IN 01295 2 IC FF TTL LS D TYPE POS EDGE TR I G COM 012 5 NOT ASSIGNED IC OP AMP PRCN O DIP P PKG 28480 NOT ASSIGNED 2 NETWORK RES 16 DIPI OK OHM X 0 11236 2 DIODE ARRAY 50V 400MA 28480 NOT ASSIGNED IC MULTIPLXR 8 C IAN ANLG DUAL 28 DIP P 20480 IC 6112 AD...
Page 84: ...062 X 0 25 IH Table 6 2 Manufacturers MANUFACTURER CODE LIST MFR NO l1ANUFACTURER NAME ADDRESS 01121 ALLEN BRADLEY CO MILWAUKEE WI 01295 TEXAS INSTR INC SEMICOND COMPNT DIV DALLAS TX 11236 CTS OF BERNE BERNE IN 19701 MEPCO ELECTRA CORP MINERAL WELLS TX 24546 CORNING GLASS WORKS BRADFORD BRADFORD 27014 NATIONAL SEMICONDUCTOR CORP SANTA CLARA 28480 HEWLETT PACKARD CO CORPORATE HQ PALO ALTO 56289 SPR...
Page 85: ...ODE ZNR 14 SV PD 5W TC OBB IR 5lJA 204BO DIODE ZNR 14 5V PD 5W TC OB8 IR 5UA 28480 DIODE ZNR 14 5V PD 5W TC OBB IR 5lJA 20400 DIODE ZNR 14 5V PD 5W TC OBB IR 5UA 28480 DIODE ZNR 14 5V PD 5W TC 08B IR 5UA 204BO DIODEZNR 14 5V PD 5W TC OBB IR 5UA 2B4BO DIODE ZNR 14 5V PD 5W TC OBB IR 5UA 20400 DIODE ZNR 14 5V PD 5W TC OB8 IR 5UA 204BO DIODE ZNR 14 5V PD 5W TC OBB IR 5UA 204BO DIODE ZNR 14 5V PD 5W T...
Page 86: ... tOO 24546 RESISTOR 10 IX 12SW F TC O tOO 24546 RESISTOR to IX t25W F TC O t 00 24546 RESISTOR 75 IX 125101 r TC 0 100 24546 RESISTOR b 19K IX 12SW F TC 0 100 t9701 8 RCSISTOR ZERO OHMS 22 AWG LEAD OIA 20480 RESISTOR ZERO OHMS 22 Awe LEAD DIA 28480 RESISTOR ZERO OHMS 22 AWG LEAD OIA 28480 RESISTOR ZERO OHMS 22 Awe LEAD DIA 28480 RESISTOR ZERO O IMS 22 Awe LEAO DIA 28480 RESISTOR ZERO OUMS 22 Awe L...
Page 87: ... resistor network U24 7 2 A component location diagram for the A to D card and the wire ter mination assembly 7 3 A component location diagram for the test assembly 7 4 Schematic diagrams of the A to D card circuit Three sheets 7 5 A schematic diagram of the wire termination assembly 7 6 A schematic diagram of the test assembly 7 7 PROM output codes 7 1 ...
Page 88: ...og Input Interface 1 2 3 4 5 6 7 8 9 10 11 12 2 S SK 1K 2SS sK 31 5K 1K 31 SK 10K 10K eo o D TOP U24 281 81 281 10K 10K 10K 10K eo Figure 7 1 Custom resistor network 7 2 24 23 22 21 20 19 18 17 16 15 14 13 ...
Page 89: ...a _ _ _ F3 U82 9 un 5I U62 5 EBB U32 qU229 U12 5 r lID L _ _ _U_83_ J em J I U33 9 U23 L _ _ _U84_ t U64 l U54 qU44 im IDI _ J U 5 ______ U24 1 _ _ 1 _ _ _ 1_ cmr 0 I U36 9 U26 5 tiID I12fr mn fm ID U97 I U77 9 U67 9 U47 g U37 9 U27 5 U92 U93 9 U94 9 U78 q U68 q U48 9 U38 9 U28 I USO U70 9 1 L J 1 C39 4 _ _ J DDDDDODO OOOOOO D O OO OO OOOO OOOODD A to D CARD Figure 7 2 Component locations 7 3 ...
Page 90: ...ut Interface 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 o m W2 33E R6 t jt ill R8 98640 66503 A XXXX Figure 7 3 Component locations on the test assembly 7 4 ...
Page 91: ... 186 1 5 C38 95 GN0 96T GNO 15 C7 lIMA IMA 4 1 ___1 3 1 4 ________ U99 DTACH 3 4 ___1 1 1 2 ____________ D21 TACH U99 5 13 1 16 C33 f U79 3 8 P4 NC L L NC 9 NC T 12 END T U82 BUSY 821 PACDA C18 AT3 INTl l QQ INT 1 AT3 INT2 LQQ INT2 IR3 1 6 ________________________________________________________ 10 p2 NC 11 14 Ail INTEN EN 12 EN 15 IR4 1 5 __ __ IR5 1 8 IR6 1w7 __ A1 BUSY 17 5 4 12 13 5 U92 3 1 2 ...
Page 92: ...V 4 L C16 15 24 l_ 1 5 12 12 13 14 NRL DD T vi 12 tC43 t 1 2 L 4 6el iC2 7 CR4 1 f I_ _ _C 15 C 7 NC 2 1 U65 20 RB C26 _ SYCLK 04 NC 1 rf BU WR C1 12 WR W 20 L 5 1 3 Io13 0V0 PRL C16 i l_1_1 U33 R16 _ BU C D D 1 5 jC i5 ANINlll 9 l 7 6 100 100 18 BU RO C1 r 1461 o DO 1 8 i 1 9 IO O 1 1NTERNALI I c oO l l 2 C 8 r n U77 i g DATA g _ 1 2 5 18 19 ID4 BUS ID4 9 4 4 5 ID5 VV I 0 5_ 7 3 3 2 ID6 ID6 5 07 ...
Page 93: ...90 14 5 ID1 v ID12 B 9 6 ENT 10 91 15 6 ID 11_ ID11 13 11 2 ENP 7 92 16 7 101o_ V IDl0 14 15 LD C 15 93 17 8 109 _ IDJi 17 16 11 94 18 Ji 108 _ V ID8 18 19 U48 T2NC rrNC EN p1JL V I NC 1 EN t NC 18 16 A15 0 lIMA QD B 16 10 3 ENT 7 43 1 ININT 4 ENP 3 5 U47 r4 NC 6 NC 44 1 2 NC 11 l5 LD NC 1 CLR Cci2 jCLRl 6 5 37 5 U97 U94 6 B4 RESET 4 5 14 READ 12 lA6 B7 il U94 TIME C5 5 5 14 5 2 45 f 5 14 5 6 2 6 ...
Page 94: ...______ C R 9 ______ 15C C R 1 0 16 GNO 17 ________ C R 1 1 __________ 18 3H 19Q NO 20G3L 21G3H 22U NO 23C7L 24ClH 25Q NO CR12 CH13 CH14 CR15 26C 27C 28C __________ C R 17 __________________ 29 __________ C R 18 __________________ 30 __________ C R 19 ____________________ GROUND CONNECTED THROUGH BACKPLATE DOG BOLTS 10 11 12 13 14 15 16 17 GND 18 19 20 21 22 23 24 PINS RO CARD EDGE NOTE ALI CR 14 5...
Page 95: ...1 I W5 1 W6 1 W7 CW8 R2 3 83K r Rl 9 09K R3 1K R4f 100 R51 10 R61 1O R7t 75 CR21 4 02V R8 6 18K 1 OL OH 1L lH 2L 2H 3L 3H 4L 4H 5L 5H 8B GO 7H 12 12 5 PACEN 2 3 5 6 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 PINS FROM CARD EDGE Figure 7 6 Test assembly schematic diagram 7 12 ...
Page 96: ...c o RP 1 __ u u WAIT 1 _______________________________________________________ PACEN _______________ nL ______________ STABT 1 PROM CODE LOCATION 3C 14 15 II 13 IB IF OF IF IF IF IF IF IF IF 5F 1B 08 18 IC IC IC IC IC IC IC IC IC IC 9C o 1 2 3 4 5 6 7 8 9 ABC 0 E F 10 11 12 13 14 15 16 17 18 19 IA IB IC 10 Figure 7 7 PROM code 7 13 ...
Page 97: ...thousand ohms when the computer is turned off or IF POWER TO THE COMPUTER FAILS If the resistor R is not sig nificantly smaller than 1000 ohms then the ADC will become a major secondary path to ground The resulting change in the voltage drop across R will affect other devices attached across R In cer tain cases the effect could cause dangerous situations to develop because people or control device...
Page 98: ...t set to one at the time of the read busy bit 16th bit 01 5 of data returned when an Analog read of the card is made If this bit is set to one the remainder of data should be regarded as invalid Further more the address data will not be retained by the card This bit provides immediate information about the status of the card card Refers to the main printed circuit assembly of the HP 98640A center ...
Page 99: ... voltage is equal to or greater than the full scale voltage Normal mode overrange at the time that a sample of a particular channel was made is indicated when the 12 least significant bits D11 to DO of the data from that sample are all set to one peA see printed circuit assembly printed drcuit assembly The finished product made up of the printed circuit board plus any per manently attached compone...
Page 100: ... analog read 3 1 3 3 3 17 3 18 3 25 4 2 address line A6 3 21 addressing 3 3 data returned 3 3 busy bit 3 4 common mode overrange bit 3 4 data bits 3 4 sign bit 3 4 wait bit 3 4 98640A Analog Input Interface analog to digital converter see also ADC 1 1 3 11 A to O card 1 1 check 2 7 removal 2 6 B boot up 10 2 2 buffered control NOT data BUC D see also signals 3 13 buffered sample signal BUSAMP see ...
Page 101: ...l OVD see signals controllines voltage source for 4 12 conversion cycle 3 17 3 18 Conversion state machine 3 1 3 13 control 3 17 clock cycles 0 to 4 5 3 1 9 reset 3 22 restart counter 3 19 stuck at cycle 16 3 20 converting to a voltage 4 5 counter release 3 17 cover plate 1 1 2 5 2 7 CPC 1 2 2 12 CPC 2 12 custom resistor network 3 7 D data buffer 3 18 data register 3 3 data word availability BUSY ...
Page 102: ...dings 4 11 extractors 2 5 G gain 1 1 gross offset value 4 3 H hold capacitor 3 10 HP 98645A 1 5 ID register see registers 3 4 input ground 2 8 offset voltage 1 1 protection analog multiplexer 3 6 input resistors 3 6 rail voltages 3 6 rolloff 4 10 voltage alias 4 1 0 installation 2 5 seating A to D card 2 5 wire termination assembly 2 7 manual 1 2 internal data bus data buffer selection 3 22 I am a...
Page 103: ..._Offset_X_512 4 4 Roughly_Corrected_Reading 4 6 Uncalibrated_Input_Reading 4 5 noise 1 5 2 10 4 3 4 10 NOT buffered write BUWR see signals 3 13 NOT buffered read BURD see signals 3 13 o offset range 4 6 offset voltage 4 3 op amps 3 7 overranges p common mode 4 7 normal mode 4 7 PACDA and external pacing 3 17 pace interval determining 3 19 Pace register see also registers 3 4 writes to 4 9 pace tim...
Page 104: ... 1 sample PascaI 4 8 PROM 3 13 R control 3 14 stopping the PROM 3 17 counter controlled 3 13 output stabalizing 3 14 period of signal sequence 3 1 4 raw reading 4 3 read 16 bit 4 1 4 13 reading 3 22 alias 4 10 averaging 4 10 reference channel 1 1 4 3 hook up 2 9 registers Data 3 3 ID 3 4 Pace 3 4 4 9 address 3 4 contents 3 4 timing a write to 4 9 Status 3 4 3 19 not busy bit 3 5 interrupt level 3 ...
Page 105: ...ackplane 3 21 BLDS backplane 3 21 3 22 4 2 BR W backplane 3 22 BUC D 3 13 3 18 3 19 BUDS backplane 3 21 3 22 4 2 BULACH 3 18 BURD 3 13 3 18 BUSAMP 3 10 3 18 3 19 BUSY 3 1 7 3 18 3 19 BUSY 3 1 7 3 19 BUWR 3 13 3 18 DTACK backplane 3 1 8 3 21 ENDCT 3 17 3 19 EPCON 3 20 EXTPAC 3 17 3 20 EXTPAC 3 20 IA6 3 18 3 21 IDEN internal data buffer select 3 22 lIMA 3 21 3 22 ININT backplane 3 18 3 21 ININT 3 21...
Page 106: ... logical state 2 2 Pascal 2 4 select code 2 2 3 20 SYCLK system clock 3 3 system clock see SYCLK 3 3 system designers guide 3 1 T test assembly 1 2 2 7 5 2 testing see verifying operation Theory of Operation conventions 3 1 thumbscrews 1 1 2 7 transorbs 1 3 3 5 u unpacking 2 1 v verification software 1 2 verifying operation 5 1 display errors 5 4 minimum equipment 5 1 test assembly 5 2 run time er...
Page 107: ...put Interface w wire termination assembly WTA 1 1 3 5 part number 1 2 removal 2 11 support 2 12 termination receptacles 2 8 window backplane 3 26 writes 3 21 3 22 4 9 4 13 WTA see wire termination assembly 1 1 INDEX 8 ...
Page 108: ...allation and Reference Manual Manual Part NO 98640 90001 July 1984 Update No _____ If Applicable We wellcome your evaluation of this manual Your comments and suggestions help us improve our publications Please use additional pages if necessary FROM Nnme Address C mpany ...
Page 109: ...PERMIT NO 256 ROSEVILLE CA POSTAGE WILL BE PAID BY Hewlett Packard Company Roseville Division 8000 Foothills Blvd Roseville California 95678 ATTN Technical Marketing Dept 1IIII1 FOLD r NO POSTAGE NECESSARY j IF MAILED IN THE UNITED STATES FOLD ...
Page 110: ...MANUAL PART NO 98640 90001 E0784 Printed in U S A July 1984 FIJ HEW ETT I II PACKARD HEWLETT PACKARD COMPANY Roseville Networks Division 8000 Foothills Boulevard Roseville California 95678 ...
