HP 8560E, Service Manual

Page: 394 / 665

Chapter 7 393
ADC/Interface Section
A16 Assembly Fast ADC Control Circuits (8560E with Option 007)
A16 Assembly Fast ADC Control Circuits
(8560E with Option 007)
The fast ADC control circuits consist of the CPU interface and control
registers, the reference clock, a clock and sample rate generator, a
trigger circuit, a 16-bit post-trigger counter, a 15-bit circular address
counter, a video trigger comparator, and the reference and power supply
circuits.
CPU Interface and Control Registers
Refer to function block A of the A16 fast ADC assembly schematic
diagram in the HP 8560 E-Series Component Level Information.
The A16 assembly digital interface to the A2 controller assembly
consists of an 8-bit bi-directional data bus, one address line, a
most-significant byte strobe, and a least-significant byte strobe.
The A16 fast ADC assembly can be accessed by firmware (on the A2
controller assembly) at two logical addresses. When the address line
(ADDR3) is low, the primary address is selected. When the ADDR3 is
high, the secondary address is selected. The data transfers between the
A16 fast ADC assembly and the A2 controller assembly are clocked by
the two strobe lines, MSB_STRB and LSB_STRB. 16-bit word transfers
occur as two sequential byte transfers; the most-significant byte first,
followed by the least-significant byte.
The primary address (ADDR3 low) contains the 16-bit control word
written by the firmware on the A2 controller assembly. The secondary
address (ADDR3 high) supports both 8-bit byte and 16-bit word reads
and writes. There is no read/write line on the A16 fast ADC assembly to
control the direction of data transfer. The fast ADC is preconfigured to
read or write by setting the appropriate bits in the 16-bit control word.
Refer to
Table 7-13 on page 394 . If the control word is not correct, it
may result in a bus conflict.