HP 64100A Service Manual Download Page 1

Page: 1 / 392

Summary of Contents for 64100A

Page 1: ...HP64000 Logic Development System Model 64100A Mainframe Service Manual r i HEWLETT a PACKARD ...

Page 2: ...he product to Buyer However Buyer shall pay all shipping charges duties and taxes for products returned to HP from another country HP warrants that its software and firmware designated by HP for use with an instrument will execute its programming instructions when properly installed on that instrument HP does not warrant that the operation of the instrument or software or firmware will be uninterr...

Page 3: ...pplies directly to MAINFRAMES with serial numbers prefixed 2336A COPYRIGHT HEWLETT PACKARD COMPANY 1981 1982 1983 LOGIC SYSTEMS DIVISION COLORADO SPRINGS COLORADO U S A Manual Part No 64100 90910 Microfiche Part No 64100 90810 All Rights Reserved PRINTED DECEMBER 1983 ...

Page 4: ...ponent replacement and internal adjustments must be made by qualified maintenance personnel Do not replace components with power cable connected Under certain conditions dangerous voltages may exist even with the power cable removed To avoid injuries always disconnect power and discharge circuits before touching them DO NOT SERVICE OR ADJUST ALONE Do not attempt internal service or adjustment unle...

Page 5: ...erification 4 1 4 1 Introduction 4 1 4 4 Boot Up Modes 4 1 4 6 Power Up Sequence 4 2 4 9 Power Up ROM Test 4 3 4 10 Power Up RAM Test 4 4 4 11 Performance Verification Boot Procedure 4 6 4 12 Performance Verification Procedure 4 8 4 15 ROM Test Procedure 4 11 4 16 RAM Test Procedure 4 12 4 17 I O Write Test Procedure 4 13 4 18 I O Read Test Procedure 4 14 4 19 Time Interrupt Test Procedure 4 15 4 ...

Page 6: ... 1 VI Replaceable Parts 6 1 6 1 Introduction 6 1 6 3 Abbreviations 6 1 6 5 Major Components 6 1 6 7 Ordering Information 6 3 6 10 Direct Mail Order System 6 3 6 13 Parts List 6 3 VI I Manual Backdating 7 1 7 1 Introduct ion 7 1 7 3 Manual Changes 7 1 VIII Service 8 1 8 1 Block Diagram Description 8 1 MF iv ...

Page 7: ...Block Diagram 8 6 8 2 A2 Motherboard Component Locator 8 7 List of Tables Table Title Page 1 1 Basic Power Current Drain 1 2 1 2 Power and Environmental Requirements 1 3 4 1 PV Boot Keys 4 8 4 2 Performance Verification Soft Keys 4 10 4 3 Failure Conditions and Routing 4 21 6 1 List of Manufacturers Codes 6 2 6 2 Reference Designators and Abbreviations 6 5 6 3 Replaceable Parts 6 6 6 4 Attach Scre...

Page 8: ...Model 64100A General Information r j 1 1 Figure 1 1 64100A Mainframe MF 1 0 ...

Page 9: ...heory of operation to the block diagram level and is intended to support the troubleshooting procedures 1 4 CHAPTER INTRODUCTION 1 5 This chapter contains technical information concerning the installation maintenance troubleshooting and theory of operation of the 64100A Mainframe The information contained in the Mainframe Chapter describes the overall system and how the various components relate t...

Page 10: ...splay Control PC Board slot C CPU PC Board 1 12 For convenience board identifier labels for the first three boards are located just above the cardcage on the left hand side The remaining ten option slots are numbered 0 9 1 13 The PC boards interface to the system through the motherboard on the bottom of the card cage A cable from the Rear Panel PC board on the rear panel makes connection to the to...

Page 11: ...he serial number is in the form OOOOA 00000 It is in two parts the first four digits and the letter are the serial prefix and the last five digits are the suffix The prefix is the same for all identical instruments it changes only when a change is made to the instrument However the suffix is assigned sequentially and is different for each instrument The contents of this manual apply to instruments...

Page 12: ...isted on the title page or in the Manual Changes supplement contact your nearest Hewlett Packard Sales Service Office 1 22 RELATED DOCUMENTS 1 23 The following documents provide addition information pertaining to the use of the HP 64000 system It is recommended that the System Overview Manual be referenced first System Overview Manual System Software Reference Manual Installation and Configuration...

Page 13: ... KEYBOARD A4 00000000000000 DDDDDDDDDDDDDD DDDDDDDDDDD DDDDDDDDDDD I I ASCII KEYBOARD MICROPROCESSOR BOARD A3 DISPLAY CONTROL BOARD AS I O CONTROL BOARD AS MOTHERBOARD A2 FLOPPY DISC DRIVE OR TAPE TRANSPORT OPTION c Jc Jc Jc J SYSTEM CONTROL KEYS DD ID IPROM I PROGRAMMER DDD SOCKET DO OPTION DDD DISPLAY KEYS Figure 1 3 Mainframe Configuration MF 1 5 1 6 blank ...

Page 14: ......

Page 15: ...g materials if a claim is made c Check the mainframe mechanically and electrically The electrical performance verification is given in Section IV For initial inspection the CYCLE softkey selection should be used d If the contents are not complete there is mechanical damage or defect or it does not pass the performance verification test then notify the carrier as well as the Hewlett Packard Sales S...

Page 16: ...ng f In any correspondence refer to the instrument by model number and full serial number 2 9 INSTALLATION AND REMOVAL OF THE MAINFRAME COMPONENTS 2 10 This section contains the installation and removal instructions for the Mainframe components excluding the Power Supply CPU PC board I O PC board Display Controller PC board and the Display Driver PC board The installation and removal instructions ...

Page 17: ...Model 64100A Operation SECTION III OPERATION 3 1 GENERAL 3 2 Refer to paragraph 1 20 related documents for information on operating instructions for the Mainframe MF 3 1 3 2 blank ...

Page 18: ......

Page 19: ...tion see section IV under System Chapter 4 4 BOOY UP MODES 4 5 The mainframe Boot Up mode is determined by the position of the control source switches on the Rear Panel The display at completion with no errors is determined by the boot source The four control source options are described in this section BIT 1 BIT 0 CONTROL SOURCE 1 1 PERFORMANCE VERIFICATION 1 0 LOCAL MASS STORAGE ADDRESSABLE o 1 ...

Page 20: ...nly Does not happen when the SHIFT and RESET keys are pressed together or the END TESTS softkey is pressed b BEEP software initiated After initialization sequence the display is also enabled c BEEP BEEP BEEP ROM test completed approximately a 7 second delay before the next beep sequence d BEEP BEEP successful completion of RAM test NOTE The 64100A now boots up according to boot switch configuratio...

Page 21: ...d timing the demultiplexed Address data bus to from ROM the and address control a This test executes a checksum on each of the OMs as long as the kernal of ROM needed to run the test is operational b If an error is detected then a bit is set in an error mask c The error mask is then used to output an error message to the screen stating a ROM failure the address range of the failure and the byte 0 ...

Page 22: ...he multiplexed memory Address Data Bus from the CPU motherboard connections between the CPU and Display Controller board the demultiplexed Address Data bus to from RAM and the timing and control circuitry Operation a The Power Up Test is a different test than the one performed during PV b The RAM test takes approximately 1 seconds c All upper 32K RAM locations are toggled to insure READ WRITE oper...

Page 23: ...he system will beep twice But if an error exists then the following error sequence occurs 1 Reset the delta timer to prevent auto restart 2 Set the SA latch 3 Write to and read from all of the upper 32K of RAM 4 Provide stimulus to CRT controller 5 Output RAM error display header information including refresh error message if refresh error flag set 6 Reset SA latch 7 Output individual failing unit...

Page 24: ...E a Place the control source switches in the Performance verification position shown on the control source label on the rear panel See Figure 4 1 for the switch locations b Turn power off and then back on The display test pattern figure 4 2 should be on screen after the boot tests However there are several steps that occur before the display test pattern is shown MF 4 6 1 Suspend operation of the ...

Page 25: ...nds 26 Clear SA interval 27 Read and write from RAM 28 Read keyboard 29 Issue an I O write 30 Begin SA interval again c After the test pattern is displayed refer to table 4 2 and make the desired softkey selection Table 4 1 PV Boot Keys PV TESTS Performance Verification Test on the left Press this softkey performance verification procedures First softkey to display the DIAG Diagnostic Third softke...

Page 26: ...itry is faulty 4 12 PERFORMANCE VERIFICATION PROCEDURE 4 13 The steps given below will enable the operator to gain access to any of the mainframe performance verification tests MF 4 8 a Perform the PV Boot procedure descibed in the previous paragraph b The performance verification menu figure 4 2 should be displayed at the bottom of the display test pattern Press the PV TESTS softkey c Press NEXT ...

Page 27: ...TROL SOURCE __ BS232 C _______ TO MODEM SElECT INS1Df O 0 80M I TO TERMINAL Jo rr V r ri W t I k s tSlOIlMlf r f t ss STOIlAGE SYS1 I IUS CURRENT LOOP r FROM TTYlrfO nVl snc RrN I SRe RTI I Figure 4 1 Rear Panel Switch Locations Figure 4 2 Display Test Pattern MF 4 9 ...

Page 28: ...his soft key to cycle through all tests except the keyboard test This is recommended as an initial test DISPLAY fourth softkey from the left Press this soft key to return to the display test pattern If pressed during the running of a test the system returns to the test pattern after completion of that test END TESTS fifth softkey from the left Press this key to reboot If pressed during a test the ...

Page 29: ... All ROMs the latches data circuitry and Operation multiplexed memory Address Data bus to ROM the buffers the CPU and its associated timing and the demultiplexed Address data bus to from ROM address control a This test is simialar to the ROM test which is performed during power up Although there is a different error message b Each test takes approximately 1 2 second c A routine reads the ROM conte...

Page 30: ...2K x 16 locations of RAM address 8002 HEX thru FFFF HEX located on the Display Controller board Note that this test occurs only on power up The lower 32K x 16 locations of RAM memory mapped address 4000 HEX thru 7FFF HEX are tested under option test The option test is initiated by pressing the opt test softkey The upper and lower 32K of RAM have their own PV and display different error messages Ar...

Page 31: ...go to error sequence see step f 10 If there is no previous error wait one second 11 Read RAM and compare with count 12 Check for an error If error occurs go to error sequence f If there are not any errors in either RAM error mask then the system will beep twice But if an error exists then the following error sequence occurs for steps a thru e 1 Reset the delta timer to prevent auto restart 2 Set t...

Page 32: ...esponds to the Uf of the failing RAM Depending on which RAM is failing the display could be affected Evidence of this is a random pattern on the CRT or incorrect spelling of messages For this reason the accuracy of a RAM test failure is always suspect Because each RAM is 1 bit wide all 16 RAMs are used to store display information Thus if any of these 16 RAMs is failing the display will be unintel...

Page 33: ... of the screen NOTE Since the display uses a portion of all 16 RAMs a failure may affect the ability to display the failed RAM IC number Example of PV ERROR MESSAGE RAM TEST BIT ERROR MASK UPPER BANK XXXX LOWER BANK XXXX The XXXX is the hexidecimal representation of the 16 bit error mask Since there are 64K x 16 locations of RAM each RAM IC is one data bit for the entire upper 32K address range Th...

Page 34: ...EDURE Purpose This test provides audible feedback that the test is executing by beeping and provides the following SA stimulus The I O WRITE TEST cycles the PHI chip register addresses cycles the interrupt masks cycles the slot select lines and stimulates the four rear panel BNC connectors Area Tested This test is not a pass fail test It provides stimulus for signature analysis for the following c...

Page 35: ...menu displays the following in inverse video I O READ TEST ADDR XX BOOT XX M X RS232 XXXXXXXX HC XX XXXXX N A ADDR XX BOOT XX is the HPIB address O lF as set by the rear panel switches is the boot source set by the rear panel switches as follows Bit 1 Bit 0 Control Source 0 0 System Bus 0 1 Local Mass Storage Talk only 1 0 Local Mass Storage Addressable 1 1 Performance Verification M X X l for CON...

Page 36: ...ime interrupt circuitry Area Tested LINE SYNC a 50 to 60 Hz signal from the power supply the delta time interrupt circuitry on the I O board and interrupts to the CPU Operation a Upon initiation the PV test counts and displays line sync interrupts to the CPU b If a failure occurs refer to I O section IV for more information 4 22 KEYBOARD TEST PROCEDURE Purpose The KEYBOARD TEST indicates proper ke...

Page 37: ...ow in figure 4 4 f Note the KEYBOARD TEST is skipped while PV is in the cycle mode START 1 6 Figure 4 4 Keyboard PV Test Sequence 4 23 SYSTEM BUS TEST PROCEDURE CAUTION THIS TEST SHOULD NOT BE RUN IF THE MAINFRAME IS CONNECTED TO A SYSTEM BUS AND IS THE MASTER CONTROLLER Purpose During the System Bus Test the PHI U20 I O board chip is taken off line and the CPU writes to and reads from its interna...

Page 38: ...ine drivers the interface to the CPU and the rear panel cable Operation a Energizes the loop back relays to loop transmit data and handshake lines back on receive data b Sends a character stream c compares receive character stream to the transmit character stream d Notes 1 The voltage translators cannot be signaturized on the higher voltage side 2 This test may take up to two minutes for a failure...

Page 39: ...he controller board mechanics and the CPU floppy controller board electronics the cable from to the drives drive READ WRITE electronics and I O and interface circuitry Operation a Response from floppy controller chip is tested by writting a pattern to the track register and reading it back b When initiated each floppy drive is cycled through the following series of tests 1 The drive is selected 2 ...

Page 40: ...ed with a cassette with data stored on it During PV read write functions are done which will result in loss of existing data on the tape Refer to the tape control and drive manual for more information Purpose The TAPE TEST will test every function of the tape system Area Tested The hole detectors high speed reverse high speed forward search the record capabilities read write circuitry and servo fa...

Page 41: ... the loss of high voltage render the CRT display useless However the B key may be pressed to determine if the CPU is serv1c1ng interrupts The beeper will sound indicating proper operation of the CPU 4 31 TROUBLESHOOTING 4 32 The purpose of the information in this section is to guide you as quickly as possible to the functional area that is failing in the Mainframe NOTE If an error is detected whil...

Page 42: ...ST softkey doesn t work 4 ROM TEST fails 5 RAM TEST fails 6 I O WRITE TEST a READ TEST b TIME INTERVAL TEST c KEYBOARD TEST d SYS BUS TEST e RS 232 BUS TEST 7 TAPE TEST 8 FLOPPY TEST MF 4 24 Failure Conditions and Routing ROUTING GO TO CPU Chapter Section IV Check 12 and 5 Vdc and then go to table 4 3 I O Chapter Section IV CPU Chapter Section IV Display Chapter Section IV I O Chapter Section IV T...

Page 43: ...CHECK THE TIMING LOGIC USE THE RESET TEST SWITCH TO CYCLE THE INITIATION PROCESS MAINFRAME TAB SECTION IV PERFORMANCE TESTS NO NO DISPLAY CONTROL TAB SECTION IV 1 IF A FAILURE OCCURS DURING THE RAM TEST USE THE FOLLOWING TABLES TO IDENTIFY THE FAILED RAM A 1 IN ANY OF THE BITS SIGNIFIES A BAD RAM EXAMPLE UPPER BYTE 0201 HEX 2 IF A RAM FAILURE IS NOT FIXED BY REPLACING THE RAM CHIP INDICATED BY THE...

Page 44: ...V ADJUSTMENTS 5 1 GENERAL 5 2 There are no adjustments that apply strictly to the Mainframe structure Refer to the Display Driver CPU and Power Supply Chapter for adjustments that pertain to these PC boards and the CRT MF 5 1 5 2 blank ...

Page 45: ......

Page 46: ...iation forms may be used with both lowercase and uppercase letters 6 5 MAJOR COMPONENTS 6 6 The major components compr1s1ng the Model 64100A Mainframe are listed below Figure 6 1 shows the location of the Mainframe components excluding the mounting attach screws The attach screws are shown in figure 6 2 Figure 6 2 is to be used in conjunction with the instructions presented in Section II Installat...

Page 47: ...Dallas Tx 75234 19701 Mepco Electra Corp Mineral Wells Tx 76067 20940 Micro Ohm Corp El Monte Ca 91731 24546 Corning Glass Wks Bradford Pa 16701 26654 Varadyne Inc Santa Monica Ca 90404 27014 National Semicond Corp Santa Clara Ca 95051 27777 Varo Semicond Inc Garland Tx 75040 28480 Hewlett Packard Hq Palo Alto Ca 94304 30983 Mepco Electra Corp San Diego Ca 92121 32997 Bourns Trimpot Div Riverside ...

Page 48: ...ect mail order system Advantages of using this system are 1 Direct ordering and shipment from the HP Parts Center in Mountain View California 2 No maximum or minimum on any mail order there is a minimum order amount for parts ordered through a local HP office when the orders require billing and invoicing 3 Prepaid transportation there is a small handling charge for each order 4 No invoices to prov...

Page 49: ...ewlett Packard part number and check digit for HP internal use 2 Total quantity Qty 3 Description of the part 4 Typical manufacturer of the part in a five digit code 5 Manufacturer s number for the part NOTE The total quantity for each part is given only at the first appearance of the part number in the list ...

Page 50: ...ter clockwise INCL includels SIL silver CER ceramic INS insulationled OBD order by description SL slide CMO cabinet mount only INT internal OH oval head SPG spring COEF coeficient OX oxide SPL special COM common K kilo 1000 SST stainless steel COMP composition SR split ring COMPL complete LH left hand P peak STL steel CONN connector LIN linear taper PC printed circuit CP cadmium plate LK WASH lock...

Page 51: ...0 ORDER BY DESCRIPTION H14 2680 0103 8 4 SCREW MACH 10 32 5 IN LG PAN HD POZI 00000 ORDER BY DESCRIPTION H15 2950 0054 1 4 NUT HEX DBL CHAM 1 2 28 THD 125 IN THK 00000 ORDER BY DESCRIPTION H16 3050 0002 2 4 WASHER FL MTLC NO 10 203 IN ID 28480 3050 0002 H17 3050 0010 2 17 WASHER FL MTLC NO 6 147 IN ID 28480 3050 0010 H18 3050 0066 8 6 WASHER FL MTLC NO 6 147 IN ID 28480 3050 0066 H19 3050 0235 3 1...

Page 52: ...Model 64100A Replaceable Parts 1 W2 MP15 MP12 MP24 MP25 M 11 M 9 MP20 Figure 6 1 Mainframe Component Locator Left View MF 6 7 ...

Page 53: ...Model 64l00A Replaceable Parts MP27 83 81 MP25 MP2 MP3 1 f4rn wAr mf lS IP MP9 1 MP1 J2 J4 J3 MP4 F1 BOTTOM COVER RECP Figure 6 1 Mainframe Component Locator Rear View MF 6 8 ...

Page 54: ...I Model 64100A Replaceable Parts MOTHERBOARD III I III I till MP5 Figure 6 1 Mainframe Component Locator Bottom View KEYBOARD MODULE PROM PROGRAMMER OPTION MF 6 9 ...

Page 55: ...Model 64100A Replaceable Parts 4 Figure 6 2 Mainframe Attach Screw Locator Sheet 1 of 7 MF 6 10 ...

Page 56: ...Model 64100A Replaceable Parts 19 19 19 19 _ _ _ 8V 1 tlO l _ _ _ _ 00 11 8 18 Figure 6 2 Mainframe Attach Screw Locator Sheet 2 of 7 MF 6 11 ...

Page 57: ...Model 64100A Replaceable Parts 1 III Illl J Figure 6 2 Mainframe Attach Screw Locator Sheet 3 of 7 MF 6 12 ...

Page 58: ...Model 64100A Replaceable Parts 2 Figure 6 2 Mainframe Attach Screw Locator Sheet 4 of 7 MF 6 13 ...

Page 59: ...Model 64100A Replaceable Parts 9 9 7 7 F F 8 Figure 6 2 Mainframe Attach Screw Locator Sheet 5 of 7 MF 6 14 ...

Page 60: ...12 12 5 Model 64100A Replaceable Parts Figure 6 2 Mainframe Attach Screw Locator Sheet 6 of 7 MF 6 15 ...

Page 61: ...Model 64100A Replaceable Parts 3 3 3 Ht 18T 3 _ 18J 3 3 h 3 18 1 3 18 J1i t 3 J 3 18 UUUJ 11m 3 3 14 3 SYMBOL KEY Screw 16 Screw 17 Screw 2 Figure 6 2 Mainframe Attach Screw Locator Sheet 7 of 7 MF 6 16 ...

Page 62: ... attach screws 8 6 Card cage attach screws 6 7 CRT mounting screws 4 8 Fan mounting screws 3 9 Tape Transport and Floppy Drive mounting screws 4 10 Power supply access port 2 11 Rear panel pC board mounting screws 4 12 Fan Shroud attach screws 7 13 Support Spring attach screws 4 14 Keyboard mounting screws 6 15 Beeper Speaker mounting screws 3 16 Motherboard mounting screws 21 17 Motherboard Top P...

Page 63: ......

Page 64: ... are listed for that serial prefix When making changes listed in table 7 1 make the change with the highest number first Example if backdating changes 1 2 and 3 are required for your serial prefix do change 3 first then change 2 and finally change 1 If the serial prefix of the instrument is not listed either in the title page or in table 7 1 refer to an enclosed MANUAL CHANGES sheet for updating i...

Page 65: ......

Page 66: ...the second list options are shown on the right side of figure 8 1 A brief functional description of each of these items and how they interrelate is presented in the following paragraphs 8 5 CENTRAL PROCESSOR UNIT CPU The CPU PC board contains a 16 bit microprocessor that controls the execution of software firmware instructions and also 1 services interrupt requests from the various external periph...

Page 67: ...RS 232 interface connectors one for when the Mainframe is serving as a modem and one for when it is serving as a terminal 3 two sets of RS 232 current loop i e teletype input output terminals 4 a HP IB interface connector and 5 a loop back circuit for testing the RS 232 circuits 8 9 KEYBOARD The 64100A Mainframe uses a keyboard that provides the operator with three basic means of communicating wit...

Page 68: ...ata signals that are distributed to the cardcage are also in most cases routed to the same pin location number in each of the 13 card slots see Table 8 5 Of course not all signals are used by each cardtype Thus if a particular PC board does not use a certain signal that is tied to pin number 20 for example this is handled by simply creating a dead end at pin 20 i e there is no conductive path on t...

Page 69: ... the neck of the CRT The signal vs pin number is shown in table 8 3 Table 8 3 Keyboard Connector J15 Signals Pin No Signal Pin No Signal 1 LPST 9 Gnd 2 Ne 10 NC 3 HKA2 11 LKA3 4 HKA6 12 LKBCLK 5 HKA5 13 HKA3 6 HKA4 14 HKDN 7 HKAl 15 HKAO 8 GND 16 No Name 8 17 CONNECTOR J16 Four test signals from cardcage connector pins 73 75 77 and 78 are routed through J16 at rear of Motherboard to the four BNC c...

Page 70: ...00A Service Table 8 4 BNC Connector J16 Signals J16 Pin No Cardcage Pin No Destination Signal 1 78 BNC 1 LTP 2 1 2 GND 3 77 BNC 2 LMC 4 1 2 GND 5 75 BNC 3 Not Used 6 1 2 GND 7 73 BNC 4 Not Used 8 1 2 GND MF 8 5 ...

Page 71: ... PROM PROGRAMMER MODULE MEMORY BUS Jl Jl Jlr PROM PROGRAMMER EMULATOR EMULATOR CONTROL MEMORY MEMORY PCB PCB PCB Pl I j Pl 1 1 Pl I I 1 IIDDRESS DIITII NTRDL CIIRD SLOT SELECT liND ID ENIIBLE J If 5V 5V j 12V t 5V _ t 5V 12V HOV INTERFACE CONNECTOR FOR USER SYSTEM T EMULATION EMULATOR BUS PROBE h PCB Jk DJ r Jf tS EMULATOR LOGIC EMULATOR MEMORY ANALYZER CONTROL CONTROL PCB PCB PCB Pl I 1 _ 1 I Pl ...

Page 72: ...X X X X x X X X X X X X X x x J6 J7 J8 J9 JI0 X X X X X x x x X X X X X X X X X X X X X X X X X X X X X X X X X X X x X X X X X X X x x x X X X X X X X X X x X X X X X X X X X X X X X X x X X X X X x x x x x X X X X x X X X X x X X X X X x x x x x X X X X X X X X X X X X X X X PINS 23 24 PIN5 19 20 PINS 15 16 PINS 11 12 x x x x x x x x x x J6 I J7 J8 J9 JI0 X X X x x x x x x x x x x x x X X X X X ...

Page 73: ...ENTRAL PROCESSING UNIT CPU COPYRIGHT HEWLETT PACKARD COMPANY 1981 1982 1983 LOGIC SYSTEMS DIVISION COLORADO SPRINGS COLORADO U S A All Rights Reserved Manual Part No Part of Mainframe Manual Microfiche Part No See Mainframe Manual ...

Page 74: ......

Page 75: ...erformance Verification and Troubleshooting 4 1 4 1 Introduction 4 1 4 7 CPU ROM Test 4 1 4 9 Power Up ROM Test 4 1 4 10 ROM Test During PV 4 2 4 11 Troubleshooting 4 3 4 13 Loop A Signatures 4 3 4 16 Counting Mode 4 4 v Adjustments 5 1 5 1 Introduction 5 1 5 3 Safety Requirements 5 1 5 5 Equipment Required 5 1 5 7 7V Adjustment 5 1 VI Replaceable Parts 6 1 6 1 Introduction 6 1 6 3 Abbreviations 6...

Page 76: ...ation 8 4 8 6 General 8 4 8 8 CPU Power Supplies 8 4 8 10 Clock Generator 8 4 8 12 Low Power On Pulse Generator 8 5 8 14 Low Byte Sync 8 5 8 16 Memory Timing Cycles 8 5 8 18 CPU Address Bus 8 5 8 20 Address Buffers 8 5 8 22 Chip Select 8 5 8 24 ROMs 8 5 8 26 CPU Data Bus 8 7 8 28 Test Reset 8 8 8 30 Input Output Bus 8 8 8 32 SA Latch 8 8 8 34 Mnemonics 8 9 CPU iv ...

Page 77: ...te Memory Cycle 8 6 8 4 Typical Read Memory Cycle 8 7 8 5 Typical I O Read and Write Cycle 8 8 8 6 CPU Component Locator 8 14 8 7 CPU Schematic 1 8 15 8 7 CPU Schematic 2 8 17 List of Tables Table Title Page 4 1 Loop A Signatures 4 5 4 2 Signature Analys is 4 6 6 1 Abbreviations 6 2 6 2 Replaceable Parts 6 4 6 3 Manufactures Codes 6 6 7 1 Manual Changes 7 1 8 1 CPU Mnemonics 8 9 CPU v ...

Page 78: ......

Page 79: ...mber of the Logic Development Station Mainframe to change The history of serial number prefix changes is recorded in Section VII of the Mainframe Chapter The details of a change for a given assembly can be found in Section VII of the appropriate Tab i e Mainframe CPU Display Control and Driver Input Output or Power Supply 1 5 RELATED DOCUMENTS 1 6 The following documents provide additional informa...

Page 80: ...PU Board contains the CPU Bus consisting of a 16 bit bi directional data bus a 16 bit address bus and several control lines The CPU Board contains the I O bus consisting of a 16 bit bi directional data bus a 4 bit address bus and several control lines The CPU bus and I O bus are controlled independently by the Microprocessor The Microprocessor is located on the CPU Board The microprocessor is a 16...

Page 81: ...placement part and installation is described in the following paragraph 2 3 CARD CAGE LOCATION 2 4 When the CPU Board is removed from the Mainframe it must always be reinstalled in the third position from the front of the Card Cage identified by the blue board extractors and blue CPU label on the Card Cage WARNING When removing or installing the CPU Board the Mainframe A C line power must be turne...

Page 82: ......

Page 83: ...ION III OPERATION 3 1 GENERAL 3 2 The CPU has no operator functions The CPU is both physically and operationally part of the Mainframe For the operation of the Mainframe see section III of the Mainframe Chapter CPU 3 1 3 2 blank ...

Page 84: ......

Page 85: ... correct the problem then the SA ROM loop counting sequence must be used to troubleshoot the CPU board 4 6 If a count sequence can not be produced then the Microprocessor or its control circuits are not operating correctly They must be repaired by using an Oscilloscope and or Logic Probe 4 7 CPU ROM TESTS 4 8 The ROM test sequence used during power up and performance verification is the same Howev...

Page 86: ...e power up test is good SELF TEST FAILURE blinking ROM TEST FAILING ADDRESS RANGE BYTE S xxxx xxxx xx f Use the table below to determine which ROM unit number is failing Note that the error message might give an address range that includes more than one ROM SA loop A might be necessary to isolate the fault see Table 4 2 Failed Failed Addresses Byte ROM II 0020 1FFF 0 U9 Lower 8K ROM 0020 1FFF 1 U1...

Page 87: ...n one ROM SA loop A might be necessary to isolate the fault see Table 4 2 4 11 TROUBLESHOOTING 4 12 In the event that a critical component has failed and the performance Verification is not able to run at all the Microprocessor will most likely be runnin g in some unknown loop or will be executing random code lost If this should happen the Microprocessor can be forced into a counting loop by chang...

Page 88: ...a trigger for an Oscilloscope you should be able to observe Ul s outputs changing state These are the ROM chip selects Using Low Data Buffer LDBUF as a trigger you can observe the outputs of the ROMs and the outputs of the Data Bus Buffers U21 and U28 If the Microprocessor is not outputing a count sequence then check the Timing Control and Clock Circuits using an oscilloscope The Clock is two nono...

Page 89: ... 16 15C8 U1 11 15C8 U26 2 8638 U33 19 15C8 Ul 12 0001 U26 4 1P06 Ul 13 0001 U26 6 4168 U34 5 2633 Ul 14 0000 U26 8 F753 U34 9 8AOH Ul 15 0000 U26 1O 3PU7 U2 5 15C8 U32 2 3981 U32 5 UA19 U32 6 449U U32 9 P6HO U32 12 52H3 U32 15 2F9U U32 16 9380 U32 19 OCCP ALL ROMs U8 9 10 11 U9 11 18 20 INSTALLED REMOVED REMOVED U27 2 FH75 U27 2 9PlC U27 2 46H6 U27 4 H7CH U27 4 A9UA U27 4 6CUU U27 6 HC41 U27 6 H7A...

Page 90: ...U8 9 18 19 DO NOTE 1 SA ON U27 GOOD POSSIBLY U8 9 DO NOTE 2 l ALL ROMS INSTALLED TAKE SA ALL SA GOOD STOP SA ON U28 BAD POSSIBLY U20 21 DO NOTE 2 SA ON U27 BAD SA ON U27 GOOD SA ON U27 BAD SA ON U27 GOOD SA ON U28 BAD SA ON U28 BAD POSSIBLY U10 11 20 21 DO NOTE 1 SA ON U28 GOOD POSSIBLY U10 11 DO NOTE 2 1 l SA ON U28 GOOD SA ON U28 BAD I SA ON U28 GOOD REPLACE U19 REPLACE U18 REPLACE U8 REPLACE U9...

Page 91: ...is manual Mainframe or with specific warnings given throughout the manual could result in serious injury or death Service adjustments should be performed only by qualified service personnel 5 5 EQUIPMENT REQUIRED 5 6 A Voltmeter capable of 01 Volt accuracy is required for this Adjustment Procedure 5 7 7V ADJUSTMENTS 5 8 There is only one Adjustment on the Central Processing Unit Board for the Regu...

Page 92: ......

Page 93: ...apitals However in the schematics and other parts of the manual other abbreviation forms are used with both lowercase and uppercase letters 6 5 REPLACEABLE PARTS LIST 6 6 Table 6 2 is the list of replaceable parts and is organized as follows a Chassis mounted parts in alphanumerical order by reference designation b Electrical assemblies and their components in alphanumerical order by reference des...

Page 94: ... INCL includels SIL silver CER ceramic INS insulation edl OBD order by description SL slide CMO cabinet mount only INT internal OH oval head SPG spring COEF coeficient OX oxide SPL special COM common K kilo 1000 SST stainless steel COMP composition SR split ring COMPL complete LH left hand P peak STL steel CONN connector UN linear taper PC printed circuit CP cadmium plate LK WASH lock washer PF pi...

Page 95: ...U30 MP2 O I MP1 I I I I H1 e I Model 64100A Replaceable Parts I H1 6 e I I J2 Figure 6 1 Illustrated Parts Breakdown CPU 6 3 ...

Page 96: ... H3 0360 0679 3 6 TERMINAL STUD SPCL STDF PRESS MTG 28480 0360 0679 J2 1251 4388 9 1 CONNECTOR 3 PIN M POST TYPE 28480 1251 4388 Ll 9140 0112 2 1 COIL MLO 4 7UH 10 Q 33 155DX 375 LG NOM 28480 9140 0112 MPl 5040 6069 4 2 EXTRACTOR BLUE 28480 5040 6069 MP2 1480 0116 8 2 PIN GRV 062 IN DIA 25 IN LG STL 28480 1480 0116 MP3 09825 67908 8 1 GASKET MICROPROCESSOR 28480 09825 67908 MP4 1205 0338 4 1 HEAD ...

Page 97: ...95 74LS2O U30 5061 3011 4 1 MICROPROCESSOR W HEAT SINK 28480 5080 3011 U31 1820 1288 9 1 IC DRVR TTL CLOCK DRVR TTL TO MOS HNP 04713 MMH0026CL U32 1820 2102 8 2 IC LCH TTL LS D TYPE OCTL 01295 74LS373 U33 182G 2102 8 IC LCH TTL LS 0 TYPE OCTL 01295 74LS373 U34 182G 1917 1 1 IC BFR TTL LS LINE DRVR OCTL 01295 74LS240 U35 182G 1198 0 1 IC GATE TTL LS NAND QUAD 2 INP 01295 74LS03 U36 1820 0539 1 1 IC...

Page 98: ...ICOND CMPNT DIV DALLAS TX 75222 03888 KDI PYROFILM CORP WHIPPANY NJ 07981 04713 MOTOROLA SEMICONDUCTOR PRODUCTS PHOENIX AZ 85062 24546 CORNING GLASS WORKS BRADFORD BRADFORD PA 16701 27014 NATIONAL SEMICONDUCTOR CORP SANTA CLARA CA 95051 28480 HEWLETT PACKARD CO CORPORATE HO PALO ALTO CA 94304 56289 SPRAGUE ELECTRIC CO NORTH ADAMS MA 01247 72136 ELECTRO MOTIVE CORP SUB IEC WILLIMANTIC CT 06226 CPU ...

Page 99: ...Model 64100A Manual Changes SECTION VII MANUAL CHANGES 7 1 INTRODUCTION 7 2 This manual has no backdating information for the CPU manual at the pUblication date of this manual CPU 7 1 7 2 blank ...

Page 100: ......

Page 101: ...the device being addressed if the information on the Data Bus is either the upper or lower byte of a word e Low Byte part of U34 and U14B indicates to the device being addressed the length of the word on the Data Bus eight or 16 bits f Timing Circuits U4A U12C U13 U14A U15 U16D part of U34 U36B C D and U37C develop the signals necessary for the Microprocessor to communicate with the devices connec...

Page 102: ...tputs and the CPU Data Bus 1 Test Reset Circuit Ul6c and U35 will cause the Microprocessor to count from 0020 Hex to 3COO Hex when the Test Mode jumpers E4 and E5 are in the TEST position and U27 and u28 are removed m SA latch U2 is used as an aid in taking signature analysis n Input Output Bus U3A u4B U5 and u6 is the path the Microprocessor uses to communicate with the I O Board which in turn co...

Page 103: ...TIMING LCLK1 Y LPOP SYNC 0 w Z III III UJ J III UJ UJ FROM FROM DISPLAY 1 0 CONTROL CPU BUS CONTROL PS MOTHERBOARD I SCHEMATIC 1 I SCHEMATIC 2 I I I I I I I I I I I 7 I I ADDR ADDR LATCH AO 15 BUFFERS I I I I y U26 I I I N l l l I I CHIP SELECT I CSO 1 I I HADL I I lRADDR I I I I I I 5 7 CPU DATA CPU ADDRESS BUS BUS HAO ROMO f ROM1 v DATA BUFFERS r LDBUF 8 1 8 Model 64100A Service Figure 8 l CPU B...

Page 104: ...Output Processor The I O Processor has a 16 bit bi directional data bus with a 4 bit address bus Along with the 4 bit address bus there are two other control lines that can be used to expand the I O Address Bus In addition there are control lines that are independent of the CPU Control Lines The I O Data Bus Address Bus and I O Control Lines form the I O Bus 8 8 CPU POWER SUPPLIES 8 9 The CPU oper...

Page 105: ...e developed from LCLK1 LCLK2 and five signals from the Microprocessor HRAL LSTM LPDR HSYNC and HRD The timing relationship of the signals needed for the Microprocessor to communicate are shown in figure 8 3 and 8 4 These signals are listed in table 8 1 8 18 CPU ADDRESS BUS 8 19 Latches U32 and U33 capture the address from the Low Instruc tion Data Address Bus LIDA when High Address Latch HADL goes...

Page 106: ... HIGH START EXTERNAL MEMORY HIGH ADDRESS LATCH LOW START MEMORY LOW PROCESSOR BUFFER OUT 2 LOW PROCESSOR DRIVE 1 I LOW MEMORY SYNC ff ff ff ff W 41 1 I LOW STROBE 3 LOW UNSYNCHRONIZED MEMORY COMPLETE I I 4 4 6 W 4 I I LOW DATA BUFFER rl 1 I__ ______ ____ Figure 8 3 Typical Write Memory Cycle CPU 8 6 ...

Page 107: ...vice 4 I I I I 0 AD D RE SS W m __ DA_TA ___ W ff I I I 4 l n07 ____________ ____ ____ J 0 0 ff ffij I I w MYff 4 I I I I I I I I I I I I I Figure 8 4 Typical Read Memory Cycle 8 26 DATA BUS 8 27 Buffers U27 and U28 provide buffering between the ROM outputs and the CPU Data Bus Because the Data Bus has addresses multiplexed on it the data can only be on the Data Bus at certain times Therefore the ...

Page 108: ...ble Timing Diagrams for both Read and Write Cycles are shown in figure 8 5 8 32 SA LATCH 8 33 The SA latch U2 is used while taking signature analysis for setting up the intervals required to get valid signatures See CPU section IV for information on the use of SA on the CPU board LOW DATA OUT LOW DATA OUT DELAYED ____________________ LOW PERIPHERAL h V 777 7 7 77 7 7 T7 1 7 ADDRESS BUS ADDRESS A L...

Page 109: ...sed peripheral device the read data from it When low indicates Microprocessor will High External Bus Grant when high indicates to the re questing device that it may use the ID Address Bus IDA High Processor Clock 1 and 2 two complementary nonover lapping clocks required by the Microprocessor Chip High Register Access Line when an address on the ID Address Bus is within the range reserved for regis...

Page 110: ...present on the bus Low Data Buffered when low enables two 8 bit buffers to transfer data from the ROMs to the Data Bus Low Direct Memory Access Request a peripheral device forces this line low when it wants direct access to memory Low Data Out when low indicates to the addressed periph eral device that the Microprocessor will write to it LIOSB must also be low Low Data Out Delayed normally low Whe...

Page 111: ...n to the I O bus low the CPU is writing Low Interrupt Request High an external device requests an interrupt by forcing this line low LIRN has a higher pri ority than Low Interrupt Request Low LIRL and can preempt the lower priority even while it is in process LPOP can preempt LIRH Low Interrupt Request Low an external device requests an interrupt by pulling this line low LIRL is the lowest pri ori...

Page 112: ... data bus has valid information on it When low and in the read mode indicates the Microprocessor is not driving the bus and the device addressed can now drive it Low Start Memory low indicates valid used to initiate that the information a memory cycle When on the Address Bus is Low Status can be tested by software Used as a Flag by any peripheral device connected to the Microprocessor The peripher...

Page 113: ...Model 64100A Service CPU 8 13 ...

Page 114: ... E1 IA Ie IA I I r I I I I e E2 IA I I E3 I I I I I I IA L __ _ J I C 3 U24 P1 TPGND r f Ii EJ J R3 R1 QD 811 I C2 RS J R6 ca cw C2D 1 C21 e22 rl I Figure 8 6 CPU Component Locator CPU 8 14 0 0 0 0 z r C9 ell 1l E5 IT I I 85 J1 TP GND N 0 U 0 0 II ADJ OUT IN M c 49 641 OO 66532 CPU ROM BOARD o 0 1 I 1 5 I C29 ...

Page 115: ...__ 3 5 I L 0 1 1__ S4 lI35B I 4 1 1 r __ _ L RA O O R 4 N P70 on NO CONNECTION FACTORY USE on L014 11 I R W 1 I U350 I 12 RIO R7 I I l 1r 26 1 26 1 4 V1I i S r r NC 5 FlO R9 RS fW l U17 NC L 8 C U146 DC FF 5 R 11 LCLKZ 5 P O 5 1 U7 5 r __ R6 3 1SK 10 U7 1 5 RI4 I K 3 16K r 6_____ ___ ONLY j J zi 11 J I f j _ 11r JW t 1 0_ I TES T RESET 5 P O 3COO HEX I T I X Y DE4 t r 14 t 0 0 P t 11 t t L WIRO IM...

Page 116: ...IA Ic IA I I r I I I I IC E2 IA I I I E3 I I I I I I IA L ___ J I C t3 O U24 TPGND P1 if Ii R6 J 0 0 R3 R1 Q2 J 11 B I C2 RS C8 C9 ell C11 U30 C2 C21 1l C22 1 l U I I I CPU Component Locator c 0 z L E5 IT Y 85 J1 TP GND U a a II L 9 I I I I ch a _a I Y I 49 64100 66532 CPU ROM BOARD B B1J If B ADJ OUT VRl IN C29 ...

Page 117: ......

Page 118: ...ISPLAY CONTROLLER AND DRIVER COPYRIGHT HEWLETT PACKARD COMPANY 1981 1982 1983 LOGIC SYSTEM DIVISION COLORADO SPRINGS COLORADO U S A All Rights Reserved Manual Part No Part of Mainframe Manual Microfiche Part No See Mainframe Manual ...

Page 119: ......

Page 120: ...RAM Tests 4 1 4 4 Power up RAM Test 4 1 4 5 Upper 32K RAM PV Test 4 3 4 6 Lower 32K RAM PV Test 4 5 4 7 Performance Verification Tests 4 5 4 9 Performance Verification Commands 4 7 4 11 Total PV Test 4 8 4 16 Operation Test 4 9 4 20 Data Test 4 10 4 23 Address Test 4 11 4 26 Byte Operation Test 4 12 4 29 Pattern Test 4 12 4 32 Refresh Test 4 12 4 36 Delay Test 4 13 4 39 Timing Test 4 14 4 42 Signa...

Page 121: ...Direct Mail Order System 6 2 MANUAL CHANGES 7 1 7 1 Introduction 7 1 7 3 Manual Backdating 7 1 SERVICE 8 1 8 1 Block Diagram Theory 8 1 8 3 The Display Controller Board 8 1 8 8 Address and Data Latches 8 1 8 9 Refresh Mode 8 2 8 12 RAM Write Function 8 2 8 13 RAM Read Function 8 2 8 14 Display Setup 8 2 8 15 Display Operation 8 2 8 22 Display Driver Board 8 3 8 25 Theory of Operation 8 4 8 26 Disp...

Page 122: ...4 24 4 10 SA Loop A 4 25 4 11 SA Loop B 4 25 4 12 SA Loop C 4 26 4 13 SA Loop D 4 27 4 14 SA Loop E 4 28 4 15 SA Loop G 4 29 4 16 SA Loop H 4 30 4 17 SA Loop I 4 31 4 18 SA Loop K 4 32 4 19 SA Loop L 4 33 4 20 SA Loop M 4 34 4 21 SA Loop N 4 36 4 22 SA Loop 0 4 37 4 23 SA Loop P 4 38 4 24 SA Loop R 4 39 4 25 SA Loop S 4 40 4 26 SA Loop T 4 41 4 27 SA Loop U 4 43 VI 6 1 Reference Designator Abbrevi...

Page 123: ...eet 1 of 2 7 3 7 3 Display Controller Schematic Sheet 1 of 4 7 11 7 3 Display Controller Schematic Sheet 2 of 4 7 13 7 3 Display Controller Schematic sheet 3 of 4 7 15 7 3 Display Controller Schematic Sheet 4 of 4 7 17 8 1 Horizontal and Verticle Sync Waveforms 8 10 8 2 Display Controller Block Diagram 8 12 8 3 Display Controller Component Locator 8 13 8 4 Display Controller Schematic Sheet 1 of 4...

Page 124: ...ssembly and the cathode ray tube CRT assembly The display screen format provides for 80 characters and 25 rows The horizontal sweep sync runs at a frequency of 25 KHz the vertical sweep sync runs at 60 Hz The dot matrix size for each character is 7 dots wide by 9 dots high To allow for a border around and between characters each character is allotted a space 9 dots wide by 15 dots high The horizon...

Page 125: ...General Information Model 64100A POST ACCELERATOR LEAD J2 DSP 1 2 Figure 1 2 Location of Display Components CRT GROUND STRAP PROTECTIVE RUBBER CUP J1 DISPLAY DRIVER BOARD ...

Page 126: ...r on the Motherboard before complete insertion To remove the Display Controller board first disconnect any cables that cross over the top of the Display Controller board The board can now be removed by lifting on the two card extractor levers simultaneously 2 3 DISPLAY DRIVER 2 4 REMOVAL WARNING HAZARDOUS POTENTIALS EXIST ON THE DISPLAY DRIVER BOARD AND ON THE CRT TO AVOID ELECTRICIAL SHOCK THE FO...

Page 127: ...harge on the CRT by connecting a jumper lead between the ground strap of the CRT and the shaft of the screwdriver Slip the screwdriver under the protective rubber cup of the Post Accelerator lead and then momentarily touch the screwdriver to the metal clip of the Post Accelerator lead 4 Disconnect the Post Accelerator lead from the CRT 5 Disconnect the cables at Jl and J2 of the display driver see...

Page 128: ... ON THE CRT TO AVOID ELECTRICAL SHOCK THE FOLLOWING PROCEDURE SHOULD BE CLOSELY ADHERED TO SAFETY GLASSES SHOULD BE WORN WHILE WORKING WITH THE INTERIOR OF THE UNIT EXPOSED 2 6 REMOVAL 1 Switch power OFF and disconnect the AC power cord 2 Completely remove the five cover Also remove the two the state and timing ground and remove cover screws that secure the top or four screws that secure clips to ...

Page 129: ... to the metal clip of the Post Accelerator lead NOTE THE CRT MAY CHARGE UP BY ITSELF EVEN WILE DISCONNECTED DISCHARGE THE CRT BY SHORTING THE POST ACCELERATOR TERMINAL OF THE CRT TO THE CRT GROUND STRAP WITH A JUMPER LEAD 4 Disconnect the Post Accelerator lead from the CRT 5 Disconnect the cables at J2 of the Display Driver and the cable at the end of the CRT 6 Completely remove the four CRT mount...

Page 130: ...ION 3 1 GENERAL 3 2 The Performance Verification section of the Mainframe contains the procedure for testing the various functional areas of the processor to help in isolating malfunctions There are no external user controls DSP 3 1 3 2 blank ...

Page 131: ......

Page 132: ...pressing the opt test softkey The upper and lower 32K of RAM have their own PV and display different error messages Area Tested All upper 32K x 16 locations of RAM including refresh ability the multiplexed memory Address Data bus from the CPU Motherboard connections between CPU and Display Controller board the demultiplexed Address Data bus to from RAM and the timing and control circuitry Operatio...

Page 133: ... to prevent auto restart 2 Set the SA latch 3 Write to and read from the upper 32K locations of RAM 4 Provide stimulus to CRT controller 5 Output RN1 error display header information including refresh error message if refresh error flag set 6 Reset SA latch 7 Output individual failing IC number for the upper 32K x 16 memory locations which are contained on all 16 RAM Ies NOTE The Display Controlle...

Page 134: ... to read and write from the upper 32K addressable locations of RAM located on the Display Control board and checks for refresh Note that this test only occurs during PV and is intended to troubleshoot intermittent problems This test can be run in single step or continuous mode It displays the number of tests run versus the number of tests failed If a failure occurs an error message code will be di...

Page 135: ...bit set in the error mask and the failing RAM Table 4 1 PV ERROR CODE A 1 indicates a failure when the HEX error code is converted to BINARY Example error RAM TEST BIT ERROR MASK UPPER BANK 2004 LOWER BANK OOOO 1 2 0 0 1 4 1 1 1 1 1 1 1 u45 u44 u43 U42 1 U41 u40 U39 U38 1 U30 U29 u28 U27 1 u26 U25 u24 U23 1 1 1 1 1 1 I 0 010 100 0 0 1 0 0 0 0 101 0 0 1 I 1 1 1 1 u43 and U25 have failed Example err...

Page 136: ...est about 99 of the circuitry used by the RAM Purpose This RAM test verifies the ability to read and write from the lower 32K x 16 memory locations of RAM located on the Display Controller board and checks for refresh operation Area Tested All lower 32K x 16 memory locations of RAM including refresh ability the multiplexed memory Address Data bus from the CPU Motherboard connections between the CP...

Page 137: ...l 64100A DSP 4 6 STATUS Awaiting COMMand option_ test tJsl1 rid ___ ____ _ ____ _____ _ _ _ _____ __ j 4 1e L L J JL__ dat1 tat if1 q P Ji L L T_ci nQ l_ i g ttP E J ____ __ a Q K b t J C Figure 4 1 System Awaiting Command Display ...

Page 138: ...through option slot 10 with an ID of 0402 HEX ENTER 10 press RETURN c Bank 1 and Bank 2 refer to the upper 16K and lower 16K of the lower 32K locations of memory in RAM under test See figure 4 3 4 9 PERFORMANCE VERIFICATION COMMANDS 4 10 Each PV display provides prompting for the commands that can be executed These commands are selected by softkeys which are defined on the following page NOTE The ...

Page 139: ... exit test softkeys start and stop the PV test 4 11 TOTAL PV TEST 4 12 Display All test categories available are shown in this display When one or more test categories have been executed the results are displayed Use the display to choose the test categories to be performed or to review the overall results of the PV DSP 4 8 Host MeMory PerforM nce Verification 32K MeMory Expander in card slot t10 ...

Page 140: ...xact cause of the error by running the failed test the results in detail Do this by positioning the the failed test category and pressing the disp test the display in the next lower level where the start and the exit test ends the PV test 4 16 OPERATION TEST 4 17 Display test results This display shows the four Operation test categories and the Use the display to view test conditions in detail Hos...

Page 141: ...o only one address in each of the 16 RAMs therefore a successful test indicates that the data paths are functioning correctly but it does not imply that all cells in all RAMs are operating properly See Pattern Test for RAM cell check Note that address bus failures generally do not affect the reliability of this test 4 22 Decoding Data Test Errors All errors found are formatted as a four character ...

Page 142: ...l in error xxxx 0000 0000 0000 0000 None 00 1 LAO 00 1 LA1 NOTE 00 1 LA2 00 1 LA3 When LAl5 False 00 1 LA4 and LA14 True 00 1 LA5 then the Memory Mapped 00 1 LA6 is addressed The lower 00 1 LA7 of RAM is addressed over 00 1 LA8 Memory Mapped I O 00 1 LA9 00 1 LA10 When LMAP1 False then 00 1 LA11 BANK 2 is addressed 00 1 LA12 001 LA13 When LMAP1 True then LA Low Address BANK 1 is addressed b Addres...

Page 143: ...All errors found are formatted as a four character hexidecimal word Each character represents four binary digits each digit corresponding to a single bit To decode an error word convert each character to its binary equivalent and compare it with the chart shown below If necessary see Table 4 2 for hexidecimal to binary conversion For example if the error word is 0060 there are errors on the LD5 an...

Page 144: ...tected during the test Cumulative error codes that differ from Results error codes indicate multiple or intermittent errors When the error codes are the same the errors are systematic Refer to the appropriate test for an explanation of what the test does and how to decode the errors 4 36 DELAY TEST 4 37 Purpose This test figure 4 5 checks for hard failures in the refresh circuitry a HARD FAILURE i...

Page 145: ...lly significant deviations from normal CPU access rates over a timed interval When the access rate is not within the normal range a failure is flagged 4 41 Decoding Timing Errors The errors found in this test are not decoded When the test fails and all other tests pass the failure is probably associated with refresh operation or the multiplexers U49 U50 or U79 U82 4 42 SIGNATURE ANALYSIS TEST 4 43...

Page 146: ...s test Table 4 2 Error Code Conversion Hex Binary Hex Binary Hex Binary Hex Binary 0 4 1 8 1 C 11 1 1 5 1 1 9 1 1 D 11 1 2 1 6 11 A 1 1 E 111 3 11 7 111 B 1 11 F 1111 4 51 TROUBLESHOOTING USING SIGNATURE ANALYSIS 4 52 Signature Analysis SA offers a fast and convenient method of isolating hardware logic failures down to the component level The basic concept is to utilize a known set of start stop a...

Page 147: ...nd LIVD with an oscilloscope and logic probe However if a 5005A Signature Analyzer is used SA can be taken The reason being this circuitry is run by a 25 MHz signal called DOTCLK and the 5004A will not operate at that speed If the signatures in loop S are good and the circuitry from the shift registers U76 and U77 to the video output check good then check the high voltage the horizontal sync and t...

Page 148: ...lTES use signature analysis setup K table CPU RAM writes setup First check the ability of the CPU to write information to the RAM GOOD Vh take signatures BAD SIGS ON RAM TIMING AND CONTROL SIGNALS use signa ture analysis setup U table RAM cycle selector generator setup to troubleshoot If these signals are not correct information may not be written to or read from RAM cor rectly Since these signals...

Page 149: ...ignature analysis setup M table CPU RAM reads setup Before signatures on the output of the RAM can be correct addressing and data from the CPU must be correct You should have already checked these func tions using CPU RAM writes and CPU RAS address check BADVh NO CLOCK SIGNAL go to signature analysis setup U table RAM cycle selector generator setup to troubleshoot NO START STOP SIGNAL go to ROM tr...

Page 150: ...g STEP 1 LEGIBLE DISPLAY YES replace failing RAM IC s DOESN T FIX PROBLEM go to step 2 Since the RAM is used to store display information the failure may be cor rupting the displayed failure information The RAM failure summary SA setup table will give you this information NO go to step 2 Since the RAM is used to store display in formation the failure may be corrupting the displayed failure informa...

Page 151: ...up BADVh NO CLOCK use signature analysis setup U table RAM cycle selector generator setup to troubleshoot NO START STOP go to step 5 VALID Vh ADDRESS TIMING AND CONTROL SIG analysis setup U table RAM setup to troubleshoot OTHER SIG ERRORS troubleshoot ERRORS use signature cycle selector generator STEP 5 CPU PROGRAM OF CRT CONTROLLER use signature analysis setup P table CPU program of CRT controlle...

Page 152: ...eshooting STEP 1 CRT CONTROLLER OUTPUTS DISPLAY TEST use signature analysis setup S table CRT controller outputs display test setup BADVh NO CLOCK troubleshoot with scope NO START STOP go to step 3 VALID Vh CRT CONTROLLER IC PINS 1 5 7 8 SIGNATURE ERRORS go to step 3 The CRT controller is not operating correctly CPU program of the CRT controller will allow you to verify that the CRT controller is ...

Page 153: ... sus pect the RAM or any IC connected to the RAM memory data bus OTHER BAD SIGNATURES troubleshoot NO BAD SIGNATURES check power supplies and clock to CRT controller If outputs are bad and all inputs are good replace the CRT controller STEP 3 CPU PROGRAM OF CRT CONTROLLER use signature analysis setup P table CPU program of CRT controller BADVh DSP 4 22 NO CLOCK signature analysis setup N table RAM...

Page 154: ...ne which of the tests the mainframe is executing All option boards removed All jumpers in the NORMAL position ST SP START pos edge CPU Bd TP10 MEM SA LATCH QUAL STOP neg edge CPU Bd TP10 MEM SA LATCH CLOCK pos edge CPU Bd TPl LSTB Signatures Vh CA27 Vh AH68 Vh AU94 Vh XXXX POWER ON RAM TEST LOOP SIMPLE RAM FAILURE Go to simple RAM failure troubleshooting POWER ON RAM TEST LOOP REFRESH FAILURE Go t...

Page 155: ...e of the signatures and data bit may be decoded to isolate the failing RAM IC numbers Executing power on RAM test or refresh failure loop ST SP START pos edge CPU Bd TP10 MEM SA LATCH QUAL STOP pos edge CPU Bd TP10 MEM SA LATCH CLOCK pos edge CPU Bd TP9 Vh 0007 Signature 0000 0002 0004 0006 Bit Failing RAM on Display Controller Bd LDO no failure U23 U51 U23 U51 LD1 no failure u24 U52 u24 U52 LD2 n...

Page 156: ... 1 1 0 x 1 bUF f J U 0 7 0 J I U 1 l 1 Pi 1 j 4 U 0 q U i I U i 0UU U J 0 i 1 4 H H U 0 t f C6F 1 U 1 0 l B F4 H U i L F J t U t t tf t i l i U I i i C 4 1 U I 1 i iCi j I U T i I 1 H4i Ii J U i 1 1 i U I l t 3GHF U J 1 LJUr i i Table 4 11 Signature Analysis Loop B PC Board Display Controller Board Test failure or circuit Power up RAM failure Data writes to RAM Procedure S A hookup Start Pos edge ...

Page 157: ...Stop Neg edge CPU Bd TPIO S A Interval Clock Pos edge Disp Controller TPll HPRAS Probe Blinking Node Sig 1 1 r j l f D0 0 D ro I I i i h Li j HP of U 41 1 j 6H U 1 I 0 p U r i 1 4 i LiC FI I 1 I HI iCPI i I U F H i I f II j 463H DSP 4 26 Node U L r I tJ i 1 U 1 I J L t U U 6 r J U B U i U L t 1 1 1 1 I 1 6H U rB t i J Sig 2HP S 4 i j j I 1 f 1 1 6H i U iPI t i 1 J 1 i 0P L eF A F C HI lCtl I i FH ...

Page 158: ...er TP6 LPCAS VH 7H 5 Probe Blinking Node Sig U 1 8 0000 U 4 i J nooo U 49 4 scoc U 3aHU U 4 40P u 0 4 DUH U 03 3 U 0 9 7 j 4 5 U O i OU d U 66 2 OUH9 u 66 4 2PP u 66 _ o3 7 J U 66 p 0 0 U J l i 7i43 U 66 1 7 266 u 66 j 4 U l U 67 8coe U 6 7 4 U63r u 67 38HU U 1 7 4 I P U I 3HH l U 6 T i i 40PO Node Sig U 70 or H49f i J LJ 0 S 9S u 70 7 38 1 P U 70 9 PFPD u 0 2 A004 u O i4 1 9 9 LJ 0 16 UF l B U 7 ...

Page 159: ... OAr A LJ i l i BPI ll U 4 l4 P444 U t S P444 U 1 j t2 P444 LJ I 4 9B 5B U j 7 l83B U 1 1 1 3 9B 58 U 6 1 4 4Aa l U t c1 4 i H U 1 14 4A H LJ 1 4 PU 3 U 5i j 2 PUS3 U 7 1 15 PU 3 U i i 4 401 3 U 3 1 14 Jl 1 3 U 1 j 6 40 1 3 U 29 1 4 3AH I J t J t 3PI1 1 5 U 1 1 3 7 Si lH3 U 30 1 4 f 4 7 U 3i i B A 4 l J l j D f 4 DSP 4 28 Node l J 3D 1 4 U O t J 39 i 4 U O S t J 40 14 U 70 U 41 14 U O 9 U 42 j 4 U...

Page 160: ...DRAS Vh P5H2 Probe Blinking Node Sig Node U 1 7 3 CP j 1 U S8 j i U D 1 2 u 1 8 P iH U S8 1 U 8 j 4 U j 2 SFCi U B j l J 4a PSH2 U 6 4 U 6 U 49 4 CPij U 65 9 U 49 7 I U8 U 49 1 4P iP U 68 4 U 6fj U 0 4 6H 2U U 68 9 U 0 A7 7S U 68 1 U 0 i DHOi U O ii i7 54 U S6 j l P IO U i f II l J8 U i6 i 3 4PSP U 1 4 6H U U S J t SU8F NOTE If the signatures of U6S and U68 are unstable use NEG clock edgE for thes...

Page 161: ...nc Stop Neg edge Disp Controller TP3 Vert Sync Clock Neg edge Disp Controller TP13 Vh P5H2 Probe Blinking Node Sig U i l t PSH U t P H U 1 IS OOO Pl U j 8 P H 2 U 4 7 6 e H U 4B S 0000 U 4 i tt 000 0 U 4 00 0 U 4 J fi O OO U 0 4 6CD6 U 0 1 DP 4 U 0 9 U P6 U SO i 2 73P j DSP 4 30 Node U j 1 U j l J S 7 i U 7 j 4 U 66 4 l J 66 U 6 U 66 1 U 6 7 4 U 6 U 7 Sig 6CB6 Dpi ilf LJ p b 73P BPS4 6CBb j 73 4 r...

Page 162: ... A hookup Start Pos edge TP14 Stop Pos edge TP14 Clock Pos edge TP2 Vh UP73 Probe Blinking Node Sig Node Sig Ul 3 55H1 U20 6 UP73 Ul 8 UP51 U20 8 H4C1 U2 11 8135 U22 1 0000 U2 12 86F1 U22 4 0000 U2 14 ACA2 U22 13 669P U5 11 8117 U35 1 0022 U35 4 2275 U9 13 ACA2 U10 6 UP73 U36 8 UP73 UlO 7 55H1 U36 11 HF06 U15 3 7U24 U37 3 7U46 U15 6 UP73 U37 6 UP51 U15 8 UP73 U37 8 7U46 U37 11 7U24 U16 6 UF74 U16 ...

Page 163: ... the multiplexers is also checked The mainframe may be forced to execute the power on RAM failure test by removing RAM IC A5U23 ST SP START pos edge CPU TP10 SA LATCH QUAL STOP neg edge CPU TP10 SA LATCH CLOCK pos edge CPU TP13 LMWRT VH H37A U 16 6 0001 U 70 3 728H U 16 8 0001 U 70 5 UH82 U 70 7 UF05 U 23 3 0001 U 70 9 lUPA U 23 4 0001 U 70 12 9093 U 70 14 P58U U 70 16 84H6 U 37 8 0001 U 70 18 F35...

Page 164: ...4 u68 12 3COA U 65 5 626H u68 14 463H U 18 1 0000 u 65 1 1U5A U 18 11 0000 U 65 9 6A39 U 18 12 0000 U 65 11 110P U 65 12 1266 U 23 3 1H31 U 65 14 OU51 U 23 5 463H U 23 6 HACA U 66 2 40po U 23 1 FH20 U 66 4 3HH1 U 23 9 OU51 U 66 5 OUH9 U 23 10 626H U 66 1 12PP U 23 11 110P U 66 9 1POO U 23 12 96cp U 66 11 0331 U 23 13 2HP3 U 66 12 OF14 U 23 15 7H31 U 66 14 1143 U 38 3 1H31 U 61 2 0000 U 61 4 7H31 U...

Page 165: ...O U 31 5 p444 U 31 6 4013 U 15 4 H555 U 31 7 9838 U 15 5 high U 31 8 PU53 U 15 6 high U 31 9 4A2H U 15 8 high U 31 11 4A2H U 15 10 3555 U 31 12 PU53 U 31 13 9838 U 16 1 high U 31 14 4013 U 16 2 0000 U 31 15 p444 U 16 4 POOO U 31 16 5AH3 U 16 5 0000 U 31 17 8AAA U 16 6 POOO U 31 18 A247 U 16 8 POOO U 31 19 0000 U 18 7 0000 U 35 10 0000 U 18 9 POOO U 37 8 POOO U 21 8 3555 U 37 10 0000 U 21 10 0000 U...

Page 166: ... OAFA U 70 12 CF46 U 65 11 PAFA U 70 13 APH6 U 65 12 HC89 U 70 14 FF7H U 65 14 3C89 U 70 15 C211 U 70 16 F8AA U 66 2 3AP7 U 70 17 AH28 U 66 4 HAP7 U 70 18 cmm U 66 5 U293 U 66 7 1293 U 71 1 POOO U 66 9 HPPO U 71 11 8AAA U 66 11 3PPO U 71 12 p444 U 66 12 2H70 U 71 13 9838 U 66 14 FH70 U 71 14 4A2H U 71 15 PU53 U 67 2 0000 U 71 16 4013 U 67 4 POOO U 71 17 5AH3 U 67 5 955U U 71 18 A247 U 67 7 755U U ...

Page 167: ...re loop by removing RAM ICA5U23 ST SP START pos edge CPU TP10 SA LATCH QUAL STOP neg edge CPU TP10 SA LATCH CLOCK pos edge CPU TP1 LSTB VH CA27 U 1 8 HC2U U 69 1 HC2U U 69 2 HF62 U 5 3 75FC U 69 3 074H U 69 5 HC2U U 7 3 3785 U 69 6 APP5 U 69 8 U869 U 15 11 2347 U 69 10 0000 U 69 11 3785 U 21 3 6645 U 21 4 HF62 U 21 10 U869 U 21 11 424p U 35 10 8HA2 U 47 3 2347 U 64 1 u664 U 64 2 F8FF U 64 3 5FAC U...

Page 168: ...ertical sync circuitry This setup allows checking the horizontal and vertical sync circuitry for proper configuration of the CRT controller IC ST SP START pos edge DSP TP16 HVRTC QUAL STOP pos edge DSP TP16 HVRTC CLOCK pos edge DSP TP4 HCHAR VH HU61 U 3 3 745H U 3 7 BC75 U 3 9 212H U 11 6 5B9H U 11 B 4179 U 11 9 AC3F U 12 9 9AOO U 12 11 Fu65 u 33 1 AC3F U 33 2 5414 u 33 3 63UP u 33 4 UP4F U 33 5 3...

Page 169: ...os edge DSP TP17 LCS VH H7P4 U 5 3 0000 U 69 8 H7P4 U 5 6 AP7C U 69 11 0000 U 69 12 H7P4 U 7 3 0000 U 7 6 H7P4 U 71 1 0000 U 71 2 A391 U 15 11 H7P4 U 71 3 2235 U 71 4 8242 U 17 6 0000 U 71 5 HPU1 U 71 6 A9A4 U 21 3 H7P4 U 71 7 AA06 U 21 4 0000 U 71 8 H2A3 U 71 9 u898 U 31 1 H7P4 U 71 11 U898 U 71 12 H2A3 U 32 1 H7P4 U 71 13 AA06 U 71 14 A9A4 U 33 12 7172 U 71 15 HPUl U 33 13 0547 U 71 16 8242 U 33...

Page 170: ...12 AH4p U 58 13 861H U 7 11 279A U 37 6 high U 58 14 F513 U 7 12 P5H2 U 37 11 279A U 58 15 8447 U 37 12 0000 U 8 6 72P9 U 65 4 C811 U 8 8 0000 U 65 7 12FO U 8 9 279A U 38 3 279A U 65 9 19A8 U 65 12 FCHU U 15 5 high U 48 5 279A U 15 6 high U 66 4 279A U 15 8 high U 49 4 9U8C U 66 7 8P54 U 49 7 355A U 66 9 U424 U 16 2 0000 U 49 9 3P32 U 66 12 4AHP U 16 6 279A U 49 12 PF45 U 16 8 279A U 67 4 279A U 1...

Page 171: ... CLOCK pos edge DSP TP4 HCHAR VH UAl1 U 3 3 676p U 33 1 9H7U U 54 2 0000 U 3 5 5HP8 U 33 2 A903 U 54 6 0000 U 3 7 5312 U 33 3 CP98 U 54 10 0000 U 3 9 c18H U 33 4 4C9F U 54 11 UAl1 U 3 12 676p U 33 7 8554 U 3 14 5312 U 33 8 UAl1 U 60 9 738F U 3 16 4489 U 33 23 A7U9 U 60 10 C67P U 3 18 c18H U 33 24 731A U 60 11 3930 U 33 25 1939 U 60 13 417H U 4 3 U239 U 33 26 58H3 U 60 14 c8pU U 4 5 P328 U 33 27 73...

Page 172: ... VH P5H2 U 19 3 A6FC U 1 8 P5H2 U 19 6 PUC9 U 1 11 5FC1 U 19 8 96uA U 2 11 0000 U 21 2 5FC1 U 5 6 0000 U 23 3 P5H2 U 5 8 0000 U 23 4 P5H2 U 23 5 u2P6 U 7 6 P5H2 U 23 6 6c86 U 7 11 P5H2 U 23 7 8P54 U 23 9 0000 U 8 6 72P9 U 23 10 0000 U 8 8 0000 U 23 11 0000 U 8 9 P5H2 U 23 12 0000 U 23 13 0000 U 9 10 H5AU U 23 15 0000 U 12 5 P5H2 U 32 2 75CF U 12 6 0000 U 32 3 901U U 32 4 CF87 U 13 1 74P7 U 32 5 A4...

Page 173: ... U 46 7 CH8H U 65 12 9635 U 46 8 2522 U 46 9 OA6c U 66 4 P5H2 U 46 12 9135 U 66 7 8P54 U 46 13 FPHC U 66 9 6c86 U 46 14 6U9U U 66 12 1734 U 46 15 84AC U 46 16 A454 U 67 4 P5H2 U 46 17 1315 U 67 7 P5H2 U 46 18 PFUA U 67 9 P5H2 U 46 19 901U U 67 12 P5H2 U 47 3 P5H2 U 68 4 88UH U 47 6 C963 U 68 7 42A7 U 47 8 P5H2 U 68 9 68HO U 68 12 FC90 U 49 4 0000 U 49 7 0000 U 69 5 P5H2 U 49 9 0000 U 69 6 P5H2 U 4...

Page 174: ...P TP2 HRAMCLK VB UP73 U 1 3 ACA2 U 1 8 UP51 U 22 1 U 22 4 U 2 11 8135 U 22 8 U 2 12 86F1 U 22 9 U 2 13 98PH U 22 10 U 2 14 ACA2 U 22 13 U 5 11 8117 U 23 3 U 23 4 U 9 11 ACA2 U 23 15 U 9 12 low U 9 13 55H1 U 35 1 U 15 3 7U24 U 35 4 U 15 5 high U 15 6 high U 36 3 U 15 8 high U 36 6 U 16 6 UF74 U 16 8 UF74 U 37 3 U 37 6 U 18 7 HF06 U 37 8 U 18 9 2275 U 37 11 U 18 12 high U 38 3 U 20 6 high U 20 8 H4c...

Page 175: ......

Page 176: ...2 0cm 8 1 2 in and 23 0cm 9 in e Adjust potentiometer R1 H POS so that the display test pat tern is centered in the bezel as close as possible f Adjust potentiometer R26 V GAIN so that the display test pattern is from 14 0cm 5 1 2 in to 15 0cm 5 3 4 in high NOTE There is no vertical position adjustment and pattern may be offset up to 6cm 1 4 in Magnetic fields from soldering irons transformers and...

Page 177: ...Adjustments Model 64100A R15 R9 FOCUS INTENSITY Ri HPOS 0 J1 DISPLAY DRIVER BD 64100 66527 L3 HGAIN J2 I D R26 VGAIN Figure 5 1 Location of Display Driver Adjustments DSP 5 2 ...

Page 178: ...Adjustments Model 64100A Figure 5 2 Display Test Pattern DSP 5 3 ...

Page 179: ...ER SUPPLY I I I I I I I I I I I I I I DISPLAY DRIVER I I NECK YOKE SCREW I I I I I L0 I FAN CRT DDDDDDDD c Jc Jc Jc J aD OOOOOOOOOODOOO DO 00000000000000 000 00000000000000 DODDDODODODD DD I I ODD Figure 5 3 Location of Yoke Neck Screw DSP 5 4 ...

Page 180: ...he reference designation as used on component locators and schematics 2 The Hewlett Packard part number 3 The check digit CD for HP internal use only 4 The quantity The total quantity for each part is given only once at the first appearance of the part number for each assembly 5 The part description 6 The manufacturer s code a five digit number 7 The manufacturer s part number 6 5 ORDERING INFORMA...

Page 181: ...ain View California 2 No maximum or minimum on any mail order there is a min imum order amount for parts ordered through a local HP when the order requires billing and invoicing 3 Prepaid transportation there is a small handling charge for each order 4 No invoicing to provide these advantages a check or money order must accompany each order 6 10 Mail order forms and specific ordering information a...

Page 182: ... clockwise INCL include s SIL silver CER ceramic INS insulation edl OBO order by description SL slide CMO cabinet mount only INT internal OH oval head SPG spring COEF coeficient OX oxide SPL special COM common K kilo 1000 SST stainless steel COMP composition SR split ring COMPL complete LH left hand P peak STL steel CONN connector LIN linear taper PC printed circuit CP cadmium plate LK WASH lock w...

Page 183: ...OTTKY CORE SHIELDING BEAD PC EXTRACTOR PC EXTRACTOR TEST llIMPEll TEST JUMPER NETWORK CNDeT MODULE DIP 16 PINS 1 RESISTOR lK 11 125W F TC 0 100 RESISTOR iK 1 i2SW F TC O iOO RESISTOR iK 1 125W F TC O 100 RESISTDR 1K 1 12SW F TC 0 100 RESISTOR 147 1 125W F TC O l00 RESISTOR 1K 11 125W F Te O IOIl RESISTOR lK 1 125W F Te 0 100 RESISTOR iK 11 12SW F TC O iOO RESISTOR 316 1 125W F TC 0 100 RESISTOR 10...

Page 184: ...AM iSO NS Ie NMOS 641 DYNAMIC RAM iSO NS Ie NMOS 64K DYNAMIC RAM 150 NS IC FF TTL l D TYPE POS EDGE TRIG PRl IN IC GATE TTl LS DR QUAl 2 INP IC FF TTL S D TYPE POS EDGE TRIG Ie MUXR DATA SEL S 2 Tll 1 LINE DRVR Ie MUXR DATA SEl s 2 TO 1 LINE DrlVR IC GATE TTL l f AND OR INV DUAL 2 IN IC GATE T TL S NOR QUAD 2 INP IC FF TTL LS D TYPE POf EDGE TRIG IC FF T TL S I TYPE POS EDGE TRIG Ie DRVR TTL S NAN...

Page 185: ... WITC ING 80V 100MA 2NI 00 35 OIODE PWR RECT OOOV 3A 300NS DIODE PWR RECT OOV JA SOONI DIODr MY RECT IWV SOMA ISONI DIODE WITCHING IOV aOOMA 2N DO 35 DIODE SwITCHING 80V 200MA 2NI DO 35 DIOOE IWITCHING BOV 200MA 2NS OO J5 OIODE TAlleTDR IOV 250MA DIODE ITAIISTOA 10V 2 50MA OIODE_I AIISTOR 10V 50MA DIDDE_eTABISTDR IOV aSOMA OIOOE IWITCHING 80V aOOMA 2NS 00 35 OIOOE_ wITCHING eov 200MA aNa 00 35 DIO...

Page 186: ...UK IX I25W TC O IOO U54 Chl hTO IOU IIU 0751 04113 4 RESISTOR eZ 5K IX 125W Te O IOO 145411 C4 I TO I2U F R33 0757 0280 3 2 RESISTOR lK 1 125W FTC 0 100 24546 C4 1 8 TO l00l F R34 01183 1015 7 RESISTOR 100 51 Z5W FC TC 400 S00 01111 CBIOl5 R35 01 83 2235 5 I RESISTOR ilK 5 25W FC Tc aOO t800 01121 CBia R36 011 18 3450 I RESISTOR 42 2K II 12 5W F TC OhIOO 245a ChI S TO 4UI F R37 011 8 3450 I RESIST...

Page 187: ...SANFORD NC 27330 24546 CORNING GLASS WORKS BRADFORD BRADFORD PA 16701 27014 NATIONAL SEMICONDUCTOR CORP SANTA CLARA CA 95051 27264 MOLEX PRODUCTS CO DOWNERS GROVE IL 60515 27777 VARO SEMICONDUCTOR INC GARLAND TX 75040 28480 HEWLETT PACKARD CO CORPORATE HQ PALO ALTO CA 94304 32997 BOURNS INC TRIMPOT PROD DIV RIVERSIDE CA 92507 50088 MOSTEK CORP CARROLLTON TX 75006 56289 SPRAGUE ELECTRIC CO NORTH AD...

Page 188: ...ANUAL CHANGES 7 4 To adapt this manual to your instrument refer to table 7 1 and make all of the manual changes listed under the serial prefix number for your instrument Perform these changes in the sequence listed Table 7 1 Manual Changes Serial Prefix Make Changes Affects 2210A 1 2 DSP 2212A 1 2 DSP NOTE DSP is the abbreviation for Display Controller and Driver boards MANUAL BACKDATING DSP 7 1 ...

Page 189: ...30 board has 64K x 16 memory locations of RAM while the 64100 66519 board has only 32K x 16 memory locations of RAM The 64100 66519 Display Controller board experiences LMSYN PROBLEMS when several option cards using LMYSYN are loaded into the card cage To correct this problem refer to SERVICE NOTE 64100A 12 Contact the nearest Sales Service Office for additional information Section IV Pages 4 1 th...

Page 190: ...G Model 64100A LIVID I VIDEO LVID DRIVER J CRT V V VY LVSYN VERT SWEEP GEN N LHSYN VERT HOE SWEEP V GEN HIGH VOLTAGE 2 I 1 2 I 30 MOTHER BOARD SIGNALS I Figure 7 1 Display Driver Block Diagram MANUAL BACKDATING DSP 7 3 ...

Page 191: ... A CRII CRI2 u CXI CRIO u CR9 R 5 EJ R29 CI8 R28 R COO t I tD CR8 C2 I f A R32 II II VR4 u u R 3 R34 CI9 B CI7 I C21 II TP2 C22 TI eQI eQ3 QQ7 R49 GQ8 CR7 TP5 QsG T 4 CRI4 CI6 C28 CRI R25 VR2 VR3 L5 R4 R24 R44 R5 R45 CRIG R22 BR46 8Rli R43 GNO EJ R20 H POS R42 CRI7 0 R47 R21 C27 TP3 R23 RI C26 R41 R40 CI B R3 R2 LI C2 DISPLAY DRIVER 64100 66523 PI Figure 7 2 Display Driver Component Locator MANUAL...

Page 192: ...i B I O F I L M E N T C21 1 22 l R24 Uf V R23 lK ri _ 4 I I IU4 _ 10 lK R21 R2l 2 2K 2 2K 5V i CISl 0 011 R20 UF V 2 lK I U4 v 2 R26 lOOK V GIIIN Rl8 lOOK CR8 C2l 2WF RZ5 210 R34 100 C23 n 04 CRS l R31 162K 0 01 CRIO UF 4 CRII J4 11 _ CRIZ r l f 10 R36 42 2K R32 Sl SK C20 l IUF V R33 39 lK llV YR4 6 19 f I R37 4Z ZK WIOTH L3 20 80UH LINEARITY _L2 C24 llOOUF R38 330 C25 33 UF T C9 o TPI R39 3 3 TP ...

Page 193: ... test occurs during PV and has a different error message Use SA table E to isolate a RAM failure Area Tested All RAMs including refresh ability the multiplexed memory Address Data Bus from the CPU motherboard connections between CPU and Display Controller board the demultiplexed Address Data bus to from RAM and the timing and control circuitry Operation a This is a different test than the one perf...

Page 194: ...o error f If there are aren t any errors in either RAM error mask then the system will beep twice But if an error exists then following error sequence occurs 1 Reset the delta timer to prevent auto restart 2 Set the SA latch 3 Write to and read from all of RAM 4 Provide stimulus to CRT controller 5 Output RAM error display header information including refresh error message if refresh error flag se...

Page 195: ... this test occurs during PV Another RAM test occurs during PV and has a different error message Use SA table E to isolate a RAM failure Area Tested All RAMs including refresh ability the multiplexed memory Address Data Bus from the CPU motherboard connections between CPU and Display Controller board the demultiplexed Address Data bus to from RAM and the timing and control circuitry Operation a Thi...

Page 196: ...ed on the analyzer can be compared with the normal signature of that node to determine if the timing relationships are proper With the 64100 Mainframe looping is provided by the PV software program and the normal signatures for various nodes are listed in the tables 4 1 thru 4 13 4 8 SERVICE TOOLS 4 9 SUGGESTED SERVICE TOOLS ARE 1 HP 5004A or 5005A Signature Analyzer 2 Digital Voltmeter 3 Oscillos...

Page 197: ...5A Signature Analyzer is used SA can be taken The reason being this circuitry is run by a 25 MHz signal called DOTCLK and the 5004A will not operate at that speed If the signatures in loop P are good and the circuitry from the shift registers u89 and U90 to the video output check good then check the high voltage the horizontal sync and the vertical sync on the display driver board Waveforms for th...

Page 198: ...ble 4 2 SA Loop B PC Board Display Controller Board Test failure or circuit Power up RAM failure Data writes to RAM Procedure S A hookup Start Pos edge CPU Bd TPlO S A Interval Stop Neg edge CPU Bd TPlO S A Interval Clock Neg edge Disp Controller U21 10 HWRT Vb lOP Probe Blinking Node U d4 1 L l L i 4 5 L i f U 34 U UA 12 U b4 1 4 u i 6 U U4 i B Sig 40 i C F P F C H 7H j O H i H 3P COC tJLCi 3 9t ...

Page 199: ...rval Stop Neg edge CPU Bd TP10 S A Interval Clock Pos edge Disp Controller TP11 HPRAS Vh A6U4 Probe Blinking Node 5ig Node 51g U18 7 0000 U79 5 4HC3 U79 7 PC47 U48 5 VH U79 9 472H U79 11 P1H9 U49 4 CF7U U82 2 H7Hf U49 7 4HC3 U82 4 7128 U49 9 P1H9 U82 5 574F U82 11 A41P U50 4 H7HF U82 12 6158 U50 7 574F U82 14 F7AF U50 9 A41P U50 12 F7AF U79 2 CF7U U79 4 1A8C MANUAL BACKDATING DSP 7 13 ...

Page 200: ...S Vh A6U4 Probe Blinking Node Sig Node Sig U18 7 0000 U84 3 9343 U84 5 2A93 U48 5 0000 U84 7 03FP U84 9 9HOU U49 4 6173 U84 12 008C U49 7 lCPA U84 14 253C U49 9 IF19 U84 16 9316 U84 18 PCPP U50 4 UC32 U50 7 66UP U85 11 A996 U50 9 286P U85 12 2CF3 U50 12 PA39 U85 13 4UIF U85 14 935P U80 2 UC32 U85 15 CPB6 UBO 4 5HF6 U85 16 AOHC U80 5 66UP U85 17 PF69 UBO 7 FOOA UB5 1B 5U76 UBO ll IF19 UBO 12 4FFH U...

Page 201: ...Disp Controller TP15 Vh POOO Node Sig Node Sig U23 14 8AAA U38 14 AH28 U31 3 8AAA U85 11 8AAA U24 14 P444 U39 14 C211 U31 5 P444 U85 12 P444 U25 14 9838 U40 14 APH6 U31 7 9838 U85 13 9839 U26 14 4A2H U41 14 6252 U31 9 4A2H U85 14 4A2H U27 14 PU53 U42 14 CF46 U31 12 PU53 U85 15 PU53 U28 14 4013 U43 14 FF7H U31 14 4013 U85 16 4013 U29 14 5AH3 U44 14 F8AA U31 16 5AH3 U85 17 5AH3 U30 14 A247 U45 14 CU...

Page 202: ...P5H2 Probe Blinking Node Sig Node Sig U17 3 CPll U64 11 A775 U64 12 BH02 U1B 7 P5H2 U64 13 2P42 U64 14 C963 U21 2 5FC1 U64 15 52A2 U4B 5 P5H2 U79 4 5CF3 U79 7 4U2A U49 4 CPll U79 9 ACBF U49 7 AAUB U49 9 4P5P UB2 4 BBUH UB2 7 42A7 U50 4 6H2U UB2 9 6BHO U50 7 A775 UB2 12 FC90 U50 9 BH02 U50 11 1734 U62 11 P2AO U62 12 AAUB NOTE If the signatures of U79 and UB2 U62 13 4P5P are unstable use NEG clock e...

Page 203: ... Disp Controller TP3 Vert Sync Clock Neg edge Disp Controller TP13 Vh P5H2 Probe Blinking Node 5ig Node 51g U1 11 P5H2 U63 11 6CS6 U63 12 SP54 U17 5 P5H2 U63 13 U2P6 U17 6 0000 U63 14 73P7 U1S 7 P5H2 USO 4 SP54 USO 7 6CS6 U47 6 P5H2 USO 9 1734 USO 12 9635 U4S 5 0000 US1 4 P5H2 U49 4 0000 US1 7 P5H2 U49 7 0000 US1 9 P5H2 U49 9 0000 U50 4 6C86 U50 7 8P54 U50 9 U2P6 U50 12 73P7 MANUAL BACKDATING DSP ...

Page 204: ...dge TP14 Stop Pos edge TP14 Clock Pos edge TP2 Vh UP73 Probe Blinking Node Sig Node Sig Ul 3 55H1 U20 6 UP73 Ul 8 UP51 U20 8 H4C1 U2 11 8135 U22 1 0000 U2 12 86F1 U22 4 0000 U2 14 ACA2 U22 13 669P U5 11 8117 U35 1 0022 U9 13 ACA2 U35 4 2275 10 6 UP73 U10 7 55H1 U36 8 UP73 U36 11 HF06 U15 3 7U24 U15 6 UP73 U37 3 7U46 U15 8 UP73 U37 6 UP51 U37 8 7U46 U16 6 UF74 U37 11 7U24 U16 8 UF74 U48 5 7U46 U18 ...

Page 205: ...UAlO U59 3 0000 U5 8 7P31 U59 8 UFF7 U7 11 UA11 U59 9 06H6 U9 1 06H6 U60 2 0000 U60 6 0000 Ul1 8 FHCF U60 10 0000 U60 11 UA11 U12 9 UA11 U74 9 P719 U33 1 34FH U74 10 6FUF U33 2 5F34 U74 11 7260 U33 3 7H30 U74 13 82UA U33 4 990C U74 14 71HU U33 5 8F61 U74 15 AH4F U33 7 049A U74 16 5HFP U33 8 UAI0 U74 17 0000 U33 23 4UU3 U33 24 P635 U75 11 24UU U33 25 3272 U33 26 CIA6 U76 15 7867 U33 27 0000 U33 28 ...

Page 206: ...Controller TP3 Vert Sync Clock Pos edge Disp Controller TP13 Vh P5H2 Probe Blinking Node 5ig Node 5 1 9 U9 10 H5AU U46 2 7328 U46 5 4319 U13 1 74P7 U46 6 307H U13 4 6176 U46 9 OA6C U13 10 4186 U46 12 9135 U13 13 75FH U46 14 6U9U U46 15 84AC U19 3 A6FC U46 16 A454 U19 6 PUC9 U19 8 96AU U49 6 307H U49 9 OA6C U35 13 0000 U49 12 9135 U46 14 6U9U U46 15 84AC U46 16 A454 U49 6 4U2A MANUAL BACKDATING DSP...

Page 207: ...edge Disp Controller TP3 Vert Sync Clock Pos edge Disp Controller Ul ll Vh IF8C Node Sig Node Sig U23 14 F5UO U38 14 OHF9 U24 14 F88P U39 14 IF61 U25 14 260A U40 14 3734 U26 14 HOH7 U41 14 60PF U27 14 6536 U42 14 5448 U28 14 2C74 U43 14 06C6 U29 14 C71P U44 14 U5U9 U30 14 P8PH U45 14 8H26 U32 3 OHF9 U32 5 IF61 U32 7 3734 U32 12 5448 U32 14 06C6 U32 16 U5U9 U32 18 8H26 MANUAL BACKDATING DSP 7 21 ...

Page 208: ... U23 14 U767 U24 14 HA7H U25 14 175F U26 14 355A U27 14 9015 U28 14 210U U29 14 U711 U30 14 2HA7 U46 2 P8PH U46 5 C71P U46 6 2C74 U46 9 6535 U46 12 HOH7 U46 15 260A U46 16 F88P U46 19 F5UO MANUAL BACKDATING DSP 7 22 Comments These signatures are at the RAM outputs When looking at latched data from previous clock they show that the refresh addressing and RAM output is OK and have nothing to do with...

Page 209: ... Pos edge CPU Bd TP1 LSTB Vh AU94 Probe Blinking Node Sig Node Sig U5 3 1021 U78 10 OUUP U78 11 H98H U7 3 51P7 U78 12 9UU9 U78 13 5586 U15 11 4472 U78 14 7F46 U78 15 859U U21 1O PP52 U83 1 AA21 U33 21 90A9 U83 2 UCF6 U83 3 51P7 U35 1O UP73 U83 5 AA21 U83 6 CAOl U47 3 4472 U83 8 PP52 U83 10 0000 U78 1 F99P U83 11 51P7 U78 2 7942 U78 3 5CH4 U78 4 5452 U78 5 5452 U78 6 9C8H U78 7 6855 U78 9 51P7 MANU...

Page 210: ......

Page 211: ...25W F TC 0 100 24546 C4 1 8 TO 1001 F H19 0684 1211 7 1 RESISTOR 12010 25W FC TC 00 600 01121 CB1211 TPl 13 0360 0535 0 20 TERMINAL TEST POINT PCB 00000 ORDER BY DESCRIPTION TPGND 0360 0535 0 TERMINAL TEST POINT PCB 00000 ORDER BY DESCRIPTION Ul 1820 0681 4 3 IC GATE TTL S NAND QUAD 2 INP 01295 SN74S00N U2 1820 1453 0 2 IC CNTR TTL S BIN SYNCHRO POS EDGE TRIG 01295 SN74S163N U3 4 1820 1917 1 2 IC ...

Page 212: ... 32 SOCKET IC 16 CONT DIP SLDR 28480 1200 0607 XU23 30 1200 0607 0 SOCKET IC 16 CONT DIP SLDR 28480 1200 0607 XU33 1200 0654 7 1 SOCKET I C 40 CONT DI P SLDR 24840 1200 0654 XU34 1200 0607 0 SOCKET IC 16 CONT DIP SLDR 28480 1200 0607 XU38 45 1200 0607 0 SOCKET IC 16 CONT DIP SLDR 28480 1200 0607 XU51 58 1200 0607 0 SOCKET IC 16 CONT DIP SLDR 28480 1200 0607 XU65 72 1200 0607 0 SOCKET IC 16 CONT DI...

Page 213: ...OSC VH9 ICS ON THIS SCHEMATIC REF DES HP PART NO U6 1820 1453 U7 lB20 06Bl U10 lB20 0629 U11 lB20 1449 U14 1B20 0683 U61 1B20 0697 U73 0960 0534 MFG PART NO 745163 74500 745112 74532 74504 74S140 0960 0534 I PARTS ON THIS SCHEMATIC I L___P_l_ _ TP4 9 IC POWER SUPPLY CONFIGURATIONS U6 10 5 5 U7 11 14 US1 73 MANUAL BACKDATING Model 64100A VH7 PIO P1 I L5CLKli 10 5 11 3 J 1 C VH7 4 K 48 1 VHB R U10B ...

Page 214: ...3 E2 ell r6 7 CB C9 lO ell 888BBBBBBBB 00 BBB BBBBBBBB 8 BEJ B m 30 e32 e34 35 e37 C39 U eZI e31 C33 36 OS 40 8BBBBBBBBBB 8nB 8 C42 T N RlG cu C45 Col 7 C 9 50 C52 C54 E4 ES E6 R 3 R12 R15 44 46 C04a C51 53 C55 56 BBB B B B B B B B 8 j BB0 GND Rl7 R 8 e14 C66 e12 76 GND BmB Q B B O 0 B 8 BB B L P 85 r Display Controller Component Locator MANUAL BACKDATING DSP 7 28 ...

Page 215: ......

Page 216: ...8 B JZ B El T N U19 E3 E2 CI2 C6 7 C8 C9 C10 ell 88BBBBBBBBB B B8G 0 _ GGBBGGBG 8 BB B U ell 31 e33 36 38 colla BBBBGBBGBBG B G B C4Z T N R16 C43 C45 47 C49 eso C5Z 54 E tI E5 E6 R9 RlZ R15 C4 1 C46 C48 CS1 53 C55 C56 9B 0 0 B B D D B D 8 BB liND RU RI C7 B Bg8 BB BB BB B rn I PI 5 Display Controller Component Locator MANUAL BACKDATING DSP 7 30 ...

Page 217: ...ff Zv Z v Z v ff 1 v 1 v ff IV iENI 19 16 15 lZ 9 6 5 14 _ 1EN2 RM8 17 ff v 3 RM10 2 V RMI Z V RM1Z 8 ff Z v RMI3 1 v l4 RM14 4 ff 1 v U RM15 1 v 8 LO LD MANUAL BACKDATING Model 64100A J I2 LO LOOI LOOZ L003 0 L004 LO lDCA Z 40 4B 4D I4B P O PI N ttt ft 65 L ___L W RrrT_____________________________I 0 R7 _____ r i ZI 1 I ICS ON THIS SCHEMATIC P O P4 T NOTE LC U7B r iM 8 4 A A 40 I r U88C r REFOE5 ...

Page 218: ... 1 6 1 7 C8 1 9 C10 e11 BBBB B B B B B B 6 B B BGB 6m B 6 BB Bm B 6 B BBB U CZ9 e31 e33 e36 38 C4D B66 6BBBB6B6 B 6 B C41 T N Rl6 C 3 C45 C47 1 49 C50 C52 C54 E04 E5 E6 1 9 A1Z Rl5 C404 C46 C48 CS1 53 CSS C56 BB6 B B 6 6 6 B 6 B J 66 R18 C704 C1i6 en e76 GNO 6 6 0 6 BmB 6 B6 6J C6I I CR3 C75 PI 85 Display Controller Component Locator MANUAL BACKDATING DSP 7 32 ...

Page 219: ...4 1820 0683 74504 U17 1820 1211 74L586 U19 182 0 1197 74L500 U33 1820 2191 827SA U59 77 1820 1112 74L574AN 5LT U60 87 1820 1191 745175 U74 1816 1496 1816 1496 U75 76 18Z0 14 Z 74LS16 U86 1820 1451 7451l1N U88 18Z0 0685 74510 U89 90 18Z0 1 03 745195 PIIRTS ON THIS SCHE TIC CI 76 CRI 4 L1 P Rl 9 16 19 TP Ul 3 5 9 11 14 17 19 33 59 60 74 77 86 91 S IC POWER SUPPLY CONFIGUAATIONS Ul 5 9 11 14 5 2D U3 ...

Page 220: ...ng high performance 8 7 Data is stored in the HM4864 in single transistor dynamic storage cells The storage cells require refresh for data retention Refreshing is accomplished by performing a memory read cycle at each of the 128 row addresses every 2 milliseconds There are actually 256 row addresses 8 bit but the RAMs are internally configured to 128 row 7 bit addresses to be compatible with the I...

Page 221: ...e functions by means of the arbitration and sequencer circuitry and then presenting the data to be stored on the data bus The arbitration and sequencer circuitry is responsible for gating the address through to the RAM address lines Since the RAM address lines are multiplexed into two 8 bit segments the sequencer must also control the byte select function U50 U49 8 13 RAM READ FUNCTION The process...

Page 222: ...n two or three of the fifteen lines in each row of characters When the input buffer is filled the CRT Controller U33 no longer requests RAM When the CRT Controller reaches the end of the row of characters the filled input buffer becomes the output buffer and the CRT Controller does 80 more RAM requests 8 19 Every time a 80 character CRT controller buffer is reading the RAM for display information ...

Page 223: ...O LA15 from the address select circuit The address lines LAO 1S are input to the byte select circuit and the upper or lower byte is selected by a gating signal from u48A pin 5 to produce output address lines LMAO 7 to the RAM 8 29 ADDRESS LINES The CPU addresses RAM over 17 address lines LAO 15 and LMAP1 The upper 32K x 16 memory locations of RAM are addressed using LAO 14 with LA15 pulled low The...

Page 224: ...deo drive circuits The character generator ROM circuit then parallel loads the display information into the shift register circuit U76 and U77 The character dot patterns are shifted to the output circuitry in serial form one row at a time 8 35 DISPLAY DRIVER The Display Driver Board provides the video drive voltage sweeps and bias voltages to drive the CRT 8 36 Display Controller U33 on the Displa...

Page 225: ...ent through the yoke for horizontal deflection CR4 and c4 form the rectifier filter for the 4ov supply The 12KV supply is internally rectified by the flyback T2 with the aquadag of the CRT acting as the filter The 4ov supply is rectified and filtered by CR6 and C11 aided by clamp VR1 The intensity and focus voltages are formed by voltage divider networks supplied by CR5 8 43 When low Vertical Sync...

Page 226: ...ow CPU Cycle this signal enables the address selectors and is used in strobing the display RAMs High BPC Row Address Strobe active high processor accessing RAM used only for Signature troubleshooting indicates Analysis High CPU Write Enable active high enables write operation either into RAM or CRT controller High System Clock 1 Used in arbitrator sequencer circuitry to make LCPURQ signal Low 25 M...

Page 227: ...ler to Display Driver circuitry that horizontal electron beam retrace function Arbitrator from display enables the Low Inverse Video active low signal from display con troller to Display Driver circuitry that enables half bright dot on CRT screen Low Load Display Counter active low address of display memory into the counters loads the first display address Low Memory Sync active low indicates memo...

Page 228: ... signal is high indicates lower eight bits being used LUPB is gated by LBYTE Low Video active low signal from Display Controller to Display Driver that enables full bright dot on CRT screen Low Vertical Sync active low signal from display con troller to Display Driver circuitry that enables the vertical electron beam retrace function Low Write active low microprocessor writes to addressed device R...

Page 229: ...NKED DISPLAY ROW F9FO 1 F9EF COOO BFFF 8002 8001 8000 7FFF 4000 3FFF 0020 00lF 0000 DSP 8 10 HOST RAM 15 216 HOST RAM 16K DISPLAY CONTROL MEMORY MAPPED I O SLOT SELECTED 16K HOST ROM 16K BPC REGISTERS INTERNAL THE LOWER 32K OUT OF 64K IS ACCESSED AS AN EXPANDED MEMORY MODULE THE LOWER 32K IS LOCATED ON THE DSP I CONTROLLER BOARD AND IS 1 ADDRESSED OVER THE MEMORY 1 MAPPED I O USING LSSEL 10 1 1 1 ...

Page 230: ...ce Model 64100A 5 4 2 I 2 14 18 22 uSEC 26 30 34 38 40 6 10 HORIZONTAL SYNC Pl PIN 55 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 MILLISECONDS VERTICAL SYNC Pi PIN 56 Figure 8 1 Horizontal and Vertical Sync Waveforms DSP 8 11 ...

Page 231: ...R 64110AI LOWER I LMAPl ADDRESS ILD1 LD10 ENABLE L__ I 1 __ J I I t LATcH LSB A SEE NOTE D Q l1 V 64K x 16 NOTE There are 64K 16memory locations of RAM Each RAM has 64K g DYNAMIC x 1 bit of memory The upper 32K 16 memory locations of RAM are RAM addressed over the Memory Address Bus The lower 32K x 16 memory locations of RAM are addressed by the Memory Address Bus and Memory Mapped I O DADDRESS B ...

Page 232: ......

Page 233: ......

Page 234: ......

Page 235: ......

Page 236: ......

Page 237: ......

Page 238: ...S 1I 051 L _ _ _ f U78B 1 r l i II _ VH 4 t f 11 4 VH4 13 R NC E4 2 S l 0 I C U83B t CTR DlY 18 P O P1 I T 3 0 13 C USSB 8 SJ VH4 1S A II NC YH4 11 g R 01 1 16 L _ _ V_H SR v VH4 1 C uss 6 VHS R I IU 1R l IL 5 E g MC L SCY iS 15 lOS 1a SCT iS NC 1 h_ UtilJ 4 7 93 I YH4 2 S3 VHo4 L__ G4 14A01 JHC HA ______ _____tr_________ 1 L tS4 2 3 4 1CS c s I I v I 3 r l U8 I DO g c m I I 48 C VR TC _t VV HH Ji...

Page 239: ...vice Model 64100A LIVID I VIDEO LVID DRIVER J CRT V VVY I LVSYN VERT SWEEP GEN N LHSYN VERT HOE SWEEP I GfN HIGH VOLTAGE 2 1 2 I I 30 MOTHER BOARD SIGNALS I Figure 8 5 Display Driver Block Diagram DSP 8 21 ...

Page 240: ...t It u 8 CRIG Rli CRI7 o C27 RI R47 C26 RSO R41 R40 CR2 CR19 VR5 C29 B DISPLAY DRIVER 64100 66527 HGAIN RI9 L3 0 GNO TP3 It C9 CR7 II oJ II CIG R25 R4 R5 R22 B CIS I C I U R38 V R39 TPI GNO C I GAIN I J R26 R36 R37 R27 Q4c J c JQ5 iO CRII CRI2 CRIO R31 CR9 EJ R35 R29 CI8 R28 R O C20 eR8 C23 VR4 R32 R33 R34 CI9 CI7 TP5 R24 R20 R21 R23 C21 1 29 PI Figure 8 6 A7 Display Driver Component Locator DSP 8...

Page 241: ... H Y L H L H FUNCTION NORMAL BRIGHTNESS HALF BRIGHTNESS OFF 40V CR15 4 VERTICAL SWEEP GEN R21 AU 2 2K 2_ 21 5V C16 CIS 4700 0 011 RZO UF V 2 2K RZ6 200K GAIN RZ7 lOOK L5 10 UH C16 lUF CR14 R49 3 9ZK tCI9 33uF R29 10K R2B lOOK 3 R30 2 B2 SK 30VOC CZ6 0 01 UF TP2 RZS R31 162K R3Z BZ SK 2Z0 R33 lK CRB CZZ 2WF R34 100 R 5 UK CR R37 R36 42 2K R4B 100 L4 22UH C24 2200UF R3B 330 0 TPI J2 25 33 uF 4Z ZK L...

Page 242: ...A INPUT OUTPUT FUNCTIONS COPYRIGHT HEWLETT PACKARD COMPANY 1981 1982 1983 LOGIC SYSTEMS DIVISION COLORADO SPRINGS COLORADO U S A All Rights Reserved Manual Part No Part of Mainframe Manual Microfiche Part No See Mainframe Manual ...

Page 243: ......

Page 244: ... 3 1 IV PERFORMANCE VERIFICATION 4 1 4 1 PV Theory 4 1 4 3 I O Write Test Procedure 4 1 4 4 I O Read Test Procedure 4 2 4 5 Time Interrupt Test Procedure 4 3 4 6 Keyboard Test Procedure 4 4 4 7 System Bus Test Procedure 4 6 4 8 RS 232 Test Procedure 4 6 4 9 Troubleshooting Using Signature Analysis 4 7 4 10 Service Tools 4 7 4 13 SA Tables 4 8 v ADJUSTMENTS 5 1 5 1 General 5 1 VI REPLACEABLE PARTS ...

Page 245: ...tch Functions 3 2 IV 4 1 I O Write Signature Analysis 4 9 4 2 I O Write Signature Analys is 4 11 4 3 I O Read Signature Analysis 4 12 4 4 I O Bus Signature Analysis 4 13 4 5 I O RS 232 Signature Analysis 4 14 4 6 I O Keyboard Signature Analysis 4 15 VI 6 1 List of Manufacturers Codes 6 2 6 2 Reference Designators and Abbreviations 6 4 6 3 Replaceable Parts List 6 5 VIII 8 1 I O Internal Addresses ...

Page 246: ... and Functions 8 9 8 2 Rear Panel Switch Locations and Functions 8 10 8 3 I O Block Diagram 8 11 8 4 HP IB Signal Lines 8 20 8 5 HP IB Handshake Timing 8 21 8 6 RS 232C and Current Loop Schematic 8 22 8 7 Terminal as a Talker 8 24 8 8 Terminal as a Listener 8 25 8 9 Modem as a Talker 8 26 8 10 Modem as a Listener 8 27 8 11 RS 232 Data Format 8 28 8 12 Typical Sequence of Events for RS 232C Data Tr...

Page 247: ......

Page 248: ...yboard PC boards contain circuits required by the Mainframe CPU board to 1 process data and instructions sent to and received from remote peripheral equipment e g disc drives printers modems etc via various buses 2 process interrupts from remote peripherals and internal Mainframe circuits 3 decode card select signals 4 decode Keyboard status signals and 5 generate a beeper tone when certain events...

Page 249: ......

Page 250: ...ear Panel PCB b Remove two studs holding System Bus connector J1 on Rear Panel c Remove two studs holding each RS232C connector J2 and J4 on Rear Panel d Remove four screws holding Rear Panel PCB to rear of Main frame 2 3 REMOVING THE KEYBOARD PC BOARD a Tilt front panel bezel forward and disconnect keyboard ribbon cable from Motherboard connector J15 b Remove PROM Programmer Module and remove two...

Page 251: ...ector before seating the board Be sure that the component side of the PC board is facing the front of the Mainframe CAUTION The I O PC board is ALWAYS installed in the forward most slot in the Mainframe card cage identified as the I O slot on the slot identification label 2 6 INSTALLING REAR PANEL AND KEYBOARD PCB S 2 7 To re install the Rear Panel and Keyboard PCB s perform the removal steps in r...

Page 252: ...DE FUNCTION Selects appropriate current level of 20 mA or 60 mA for peripherals such as a teletype TTY Selects either internal or external clock source for asynchronous operations The internal clock fre quency is determined by the baud rate dip switch S5 on the I O PCB Selects current loop or RS 232 operation modes In the current loop operation a logic 1 is 20 mAl 60 mA while a logic 0 is 0 mAo In...

Page 253: ...n on the location and function of the I O PCB dip switches Sl S5 I O 3 2 SWITCH S2 Be S3 Sl Table 3 2 Rear Panel Switch Functions NAME SYSTEM BUS CONTROL SOURCE FUNCTION S2 and S3 are both 8 bit dip switches which control the main frame as a controller or as a non controller see the 64100A operating manual for description of how to set S2 and S3 Sl is a 7 bit dip switch which controls the boot up ...

Page 254: ...32 0 2 I BAUD RATE EVEN ODD PARITY E 0 3 I 0 RS 232 TRUTH TABLE FOR 55 PARITY ENABLE 0 4 I 0 MODE 55545352 RATE 0 5 I SEL 0 0 o 0 50 CHAR LENGTH 0 6 I 84 0 0 o 1 75 0 0 1 0 110 BAUD RATE FACTOR X16 0 7 I X1 0 0 1 1 134 5 1 o MODEM 0 8 I TERMINAL 0 1 o 0 150 0 1 o 1 300 0 1 1 0 600 0 1 I HALF DUPLEX 0 1 1 1 1200 FULL DUPLEX 1 0 o 0 1800 0 2 I 1 0 o 1 2000 0 3 I 1 0 1 0 2400 BAun 1 0 1 1 3600 RATE 0...

Page 255: ... TO TtRMINAL BOOT UP SOURCE ADDRESSES MSB LSB CONTROL a a SYS BUS D ISC J2 a LOCAL MASS STORAGE TALK ONLY J4 NOT J3 MAINFRAME ADDRESSES USED MSB LSB ADDRESS 00 a a a a 00 a a NOT VALID a LOCAL MASS STORAGE ADDRESSABLE PERFORMANCE VERIFICATION 00 a a 2 00 a 1 1 3 VALID 00 a a 4 MAINFRAME 00 a 1 5 ADDRESSES 00 a 6 00 7 Figure 3 2 Rear Panel Switch Locations and Functions I O 3 4 ...

Page 256: ... register addresses accessess the interrupt masks cycles the slot select lines and stimulates the four Rear panel BNe connectors Use SA loops A and B for trouble isolation Area Tested This test is not of the pass fail type It provides stimulus signature analysis for the following cicuitry Option slot select lines on the Motherboard all connections from option slots to the Rear panel BNC connectors...

Page 257: ...isplays the following in inverse video I O READ TEST ADDR XX BOOT XX M X RS 232 XXXXXXXX HC XX ADDR XX BOOT XX is the HPIB address O lF as set by the Rear panel switches is the boot source set by the Rear panel switches as follows Bit 1 Bit 0 Control Source 0 0 System Bus 0 1 Local Mass Storage Talk only 1 0 Local Mass Storage Addressable 1 1 Performance Verification M X X l for CONTROLLER MASTER ...

Page 258: ...CPU via the delta time interrupt Area Tested The LINE SYNC a 50 to 60 Hz signal from the power supply the delta time interrupt circuitry on the I O board and interrupts to the CPU Operation a Upon initiation the PV test counts and displays line sync interrupts to the CPU The display will show the amount tests that have passed or failed NOTE Since LINE SYNC is asynchronous with the CPU timing SA ca...

Page 259: ...cific sequence Furthermore even if all keyswitches and the decoding circuitry are working a key that is pressed out of sequence will cause a FAILED TEST message and end the test d The order in which the keys are pressed is given on figure 4 1 e There is a second test that involves observing if the correct character is displayed on the CRT each time a key is depressed while the system is in the PV ...

Page 260: ...Model 64100A Performance Verification I Figure 4 1 Keyboard Test Sequence I O 4 5 ...

Page 261: ...PHI chip off line and reads and writes to various registers in the PHI chip b The transceiver lines and the cable to the Rear panel HP IB connector are not presently being checked c If an error occurs it may take up to 2 minutes to be detected 4 8 RS 232 TEST PROCEDURE Purpose NOTE I O switch S5 must be set to return to sender grant aknowledgement RTS right position The baud rate select switches S...

Page 262: ...TING USING SIGNATURE ANALYSIS 4 10 Signature Analysis SA offers a good method of isolating hardware logic failures down to the component level The basic concept is to utilize a known set of start stop and clock signals that constantly repeat loop with the same timing relationships When a suspect logic node is probed with a Signature Analyzer while using the start stop and clock signals as control ...

Page 263: ...st set up is proper This signature is very important since it verifies that the start stop and clock signals are normal If this signature is good proceed with the signatures listed in the table while referring to the appropriate schematic for guidance If an improper signature is noted check on both sides of the device to determine if it is causing the problem or if the problem has its origin furth...

Page 264: ...6 0021 U2 6 PP8H U5 7 0858 U2 7 H72H U5 8 52F5 U2 8 5A37 U5 9 5A9H U2 9 3FC8 U5 11 5A9H U2 11 AHOA U5 12 52F5 U2 12 FC85 U5 13 0858 U2 13 469U U5 14 0021 U2 14 7U3U U5 15 9A2U U2 15 8A5P U5 16 P405 U2 16 U952 U5 17 91C2 U2 17 5A44 U5 18 A14H U2 18 F9C5 U5 19 0000 U2 19 0000 U6 2 91C2 U4 1 0021 U6 9 0000 U4 2 5C53 U6 11 0021 U4 3 F54C U6 18 0000 U4 4 9CCP U4 5 P947 U7 3 OC8U U4 6 U639 U7 6 91C2 U4 ...

Page 265: ... 12 9265 U44 2 AU70 U17 15 91C2 U44 5 F7HF U44 6 CUIF U1S 7 91C2 U44 9 HHU6 UlS 10 91AO U44 11 FOC2 UlS 13 91C2 U44 16 7HUO UlS 14 91C2 U44 19 C927 UlS 15 OCSU U45 1 0000 U22 12 91C2 U45 2 30UU U45 3 HU55 U23 2 0000 U45 4 S5FF U23 3 91C2 U45 5 FC2C U23 5 0000 U45 6 24S1 U23 6 91C2 U45 7 UCH4 U23 S 91C2 U45 9 9193 U23 10 0000 U45 10 FSH9 U23 11 91C2 U45 11 91C2 U23 13 0000 U45 12 91C2 U24 2 0000 U5...

Page 266: ...may be jumpered base to emitter S A hookup START POS EDGE 1 0 BD TP2 S A INTERVAL STOP NEG EDGE I O BD TP2 S A INTERVAL CLOCK POS EDGE CPU BD TPI LSTB VH 7468 Node Sig U43 8 C79A U43 9 CU6P U53 1 P291 U53 2 U197 U53 3 U4Al U53 4 CUOP U53 5 AC3A U53 6 C265 U53 7 H018 Node Sig U53 8 53P5 U53 9 FACI U53 10 4AFC U53 11 6H3U U53 18 C79A U53 19 CC65 U53 20 APH6 U53 21 3UOP U53 22 OU77 U53 23 8UHP I O 4 ...

Page 267: ...U4 6 0007 U35 12 0007 U4 7 0003 U35 14 0003 U4 7 0007 U35 14 0007 U4 8 0003 U35 16 0003 U4 8 0007 U35 16 0007 U4 9 0003 U35 18 0003 U4 9 0007 U35 18 0007 IMMATERIAL HOW S3 OR S4 ARE SET U5 3 000 UI4 2 0007 U22 12 0007 U5 5 0006 UI4 5 0000 U5 7 0001 UI4 6 0000 U23 2 0000 U5 8 0004 UI4 9 0000 U23 3 0007 U5 9 0001 UI4 12 0000 U23 5 0000 U5 11 0001 U14 15 0000 U23 6 0007 U5 12 0004 UI4 16 0000 U23 8 0...

Page 268: ...U2 l3 llAF U2 l4 3CF6 U7 2 9029 U18 7 9A4A U2 l5 4966 U7 3 HU64 U18 10 9A4A U2 l6 FU03 U7 4 OA63 U18 l3 9A4A U2 l7 H4C7 U7 6 9A4A U18 l4 9A4A U2 l8 H62F U7 9 452U U18 l5 0001 U7 ll HU64 U4 2 C4l5 U7 l2 HU65 U22 l2 9A4A U4 3 98A3 U7 l3 0001 U4 4 3A12 U23 2 0000 U4 5 3C9P Ull l 9A4A U23 3 9A4A U4 6 3C9P Ull 2 2427 U23 5 0000 U4 7 3C9P Ull 4 C4l5 U23 6 9A4A U4 8 ACC6 Ull 5 3A12 U23 8 9A4A U4 9 ACC6 U...

Page 269: ...005U U18 10 OOUF U2 4 OOlH U18 l3 009A U2 5 OOlH U18 l4 00P6 U2 6 OOlH U18 l5 007U U2 7 OOlH U2 8 003H U22 l2 OOUp U2 9 005H U2 11 00A3 U23 2 U2 l2 00F3 U23 3 OOUP U2 l3 00P3 U23 5 0000 U2 l4 00P3 U23 6 OOUp U2 l5 00P3 U23 8 OOUP U2 l6 00P3 U23 l0 0000 U2 l7 OOAI U23 11 OOUp U2 l8 00P7 U23 l3 0000 U5 3 0000 U24 2 0000 U5 5 OOUU U24 3 OOUP U5 7 0003 U24 5 OOUH U5 8 OOIA U24 6 OOUP U5 9 0065 U24 8 O...

Page 270: ...board Test S A hookup START POS EDGE I O BOARD TP7 STOP POS EDGE I O BOARD TP7 CLOCK POS EDGE I O BOARD TP8 VH 8P54 Probe Blinking Node Sig Node Sig U25 6 C4FP U38 I 84H4 U25 8 3A9A U38 4 I8A5 U38 8 2046 U34 3 0863 U38 10 API2 U34 4 HH53 U38 I3 A492 U34 5 HIOF U34 6 3A9A U39 1 0000 U34 8 FCF2 U39 5 HH89 U34 9 2946 U39 6 53HH U34 10 F6IC U39 7 29PP U34 11 0108 U39 9 A7CA U40 5 FCF2 U40 6 OA80 U40 8...

Page 271: ......

Page 272: ...5 1 GENERAL SECTION V ADJUSTMENTS Model 64100A Adjustments 5 2 The I O Keyboard and Rear Panel PC boards have no adjustments I O 5 1 5 2 blank ...

Page 273: ......

Page 274: ...pital letters and two partial or no capitals This occurs because the abbreviations in the parts list are always all capitals However in the schematics and other parts of the manual other abbreviation orms may be used with both lowercase and uppercase letters 6 5 ORDERING INFORMATION 6 6 To order a part listed in the replaceable parts list See table 6 3 quote the Hewlett Packard part number and che...

Page 275: ...Dallas Tx 75234 19701 Mepco Electra Corp Mineral Wells Tx 76067 20940 Micro Ohm Corp EI Monte Ca 91731 24546 Corning Glass Wks Bradford Pa 16701 26654 Varadyne Inc Santa Monica Ca 90404 27014 National Semicond Corp Santa Clara Ca 95051 27777 Varo Semicond Inc Garland Tx 75040 28480 Hewlett Packard Hq Palo Alto Ca 94304 30983 Mepco Electra Corp San Diego Ca 92121 32997 Bourns Trimpot Div Riverside ...

Page 276: ...rder forms your local HP office this manual and specific ordering information are available through Addresses and phone numbers are located at the back of 6 11 PARTS LIST 6 12 Table 6 3 lists the replaceable parts for the I O Rear panel and Keyboard PC boards and is organized as follows 1 Electrical assemblies and their components in alphanumerical order by reference designation 2 Miscellaneous pa...

Page 277: ...ter clockwise INCL includels SIL silver CER ceramic INS insulation ed OBD order by description SL slide CMO cabinet mount only INT internal OH oval head SPG spring COEF coeficient OX oxide SPL special COM common K kilo 1000 SST stainless steel COMP composition SR split ring COMPL complete LH left hand P peak STL steel CONN connector LIN linear taper PC printed circuit CP cadmium plate LK WASH lock...

Page 278: ...0VOC CER 28480 Oillo aon CI2 011l0 Z055 q CAPAC ITOR FXO OIU 80 201 100VOC CER 28410 OloOdOS cn 0Iso_01 l7 I 3 CVAC ITOR FXO 2 2UF IOI 20VOC TA sun 1500225X OZOAZ C Q 01bO 20S5 q CAPACITOR nO OIUF 80 201 IDOVOC CER 28480 01110 2055 CI5 OIOO Olbi 4 I CAPACITOR XO OIUF 101 200VOC PO V UQ80 oIllO OIU CIb 01110 2055 I CAPACITOR nO OIUF 80 201 100vOC CER UUO 01 00 2055 cn ouo oln 8 CAPACITOR no 2 2UF I...

Page 279: ...O RISISTOR IK II I25W TCIOt IOO RESISTOR 20M II I15W F TCIOt IOO R IISTOR 11K II I25w TCIO IOO RESISTOR S IIK II I25W F TCIO IOO WITC S OPOT OIP S IOE ASSY IA 50VDC SWITC 8 a SPOT OIP_aLIDE_AISY IA SWITc a OPOT OIP SLIDE AISV l5A 30 DC IwtTCM IL e IA OIP I ID ASIV IA 50VOC SWITC 8L 5 IA OIP I IDE AS8Y IA 50VOC TERMINAL TE8T POINT pca NITWORK_RES 10 SIPI 5K OH X 9 IC IIC TT 8 NETwOR RES 10 aIPI K O...

Page 280: ...TRIG TTL LI NAND DUAL 4 INP OIl S INUL8UN U43 1120 1197 9 IC GATE TTL LS NAND QUAD a INP 01291 IN74LUON U44 IIlIO H30 I Ie TTL LI D TVP POI EDaE TRIG CD olltS SNULII7JN U45 1820 1281 iI IC DCDA TTL LS 2 TO 4 LI E DUAL 2 INP 01191 IN74LIU N U4 1820 0990 8 IC RCVR DTL NAND LINE QUAD 0 7U MCtG AL U47 110 021 2 NETWORK_RE8 10 SIPt IM OHM x 9 01121 OAIII U48 t8U OUI 4 I Ie GEN DUAL IU KUllA UG9 IUO 14U...

Page 281: ...OOMHZ U4IO 1851 001 Q I 854 0ill 5 I 2 TRANIUTOR N N 1 PO JSO w n_JOOMHZ 047U INUO_ Q4 185 0215 I TUNaUTOR N at pD_nOMW UlOOIolHZ 04711 INI R1 0757 0389 5 I RESISTOR 33 2 1 125W F TC 0 100 28480 0757 0389 R2 on1 0U I REatlTOR 10K II I21W TC O IOO 1 C4 III TO IOU RS 0751 0401 0 I RES STOR 100 IX I2SW TC Ot IOO C4 III To 101 R4 0757 0280 3 StSTOR 1M IX I W TC_O _IOO 24 C4 I I TO 100I RI on1 0UO 3 RE...

Page 282: ... eAlCI 21 0 OJ7hlioU 0371 1631 I I KEV Cl L T lCI UUO OJn IU7 OUI IUI I KEV Cl QUEI K nuo OJ7I IUI 0171 161 0 I KEV Cl CO MA 21410 0171 61 0371 1600 3 I KEV Cl UIOD nuo 0371 ilo oJ7I IUI I I KIV Cl 2UIO 0371 1 03f1 1 K V Cl 7 nuo 0171 1i42 0171 US KEV Cl n410 OJ71 43 oJ7I I 1 KEV Cl S nuo 0371 11044 0371 1 1 I KEV Cl 21410 0171 I S 0371 1 I KEV CA za4l0 0 71 IU OJ7I 1 7 0 I MIV ClP 2 nuo 0371 7 oJ...

Page 283: ...4 C4_I I TO IORO R4 oU7 014 I UUTOR 10 II 12SW TCaO IOo 24546 C4 III tO 1 ORO itS 07lhOJ46 2 RUUTOR 10 II 12SW TCaO IOO IU46 e4 1 TO IORO II 07 7 0346 I RElUTOR 10 II lUll TCaO 100 4 46 C4_I a_TO_IOII0_ R7 0717 OJ46 2 RUreTOR 10 II lUll TC_0 100 14546 C4 I To IORO RI 0717 0346 2 RElInOR 10 II 125W TC_O JOO 24 14 C4 I tO IORO R9 07 l7 OJ46 2 R l nOIl 10 II I2 1W Teao JOO 14 46 C4_l hTo_IORO 1110 07...

Page 284: ...Model 64100A Manual Backdating SECTION VII MANUAL BACKDATING 7 1 INTRODUCTION 7 2 There is no backdating information for the I O chapter at the publication of this manual I O 7 1 7 2 blank ...

Page 285: ......

Page 286: ... circuits 2 Driving the beeper 3 Allowing the CPU to select and interchange data with any of the sev ral PC boards in the card cage 4 Monitoring line sync and power fail status and providing such information to the CPU 8 5 The I O circuits are divided into four major functional areas on Figure 8 3 1 I O Control upper left on the block diagram 2 Keyboard Control lower left 3 HP IB Control upper rig...

Page 287: ... Address Sets Interrupt Mask Latch Address Power Fail Set Address 8 10 BEEPER SA INTERVAL CARD ID ENABLE AND DISPLAY ENABLE In addition to the nine peripheral addresses there are two interface control addresses LIC1 and LIC2 that the CPU uses to control the beeper the signature analyzer start stop signals SA INT and the card ID address decoder This latter circuit produces the ID enable signal LIDE...

Page 288: ...below where it serves as a reset pulse 1 SA Latch 2 High Priority Interrupt Latch 3 Power Fail Latch 4 Delta Time Counters 5 Slot Select Address Latch 6 Interrupt Mask Latch 7 PHI Address Latch 8 14 HIGH PRIORITY INTERRUPT LATCH Whenever power is about to fail the Power Supply sends interrupt request signal LIR15 to the high priority interrupt latch This produces high priority interrupt request LI...

Page 289: ... are the only peripheral devices that can be driven from the HP IB bus 8 21 CONTROL LOGIC ADDRESS LATCH AND STATUS BUFFER The Control Logic decodes four control signals LICI LIC2 LDOUT and LBEEP and produces a set of outputs that control the selection of Status Buffer U12 Address Latch U11 and PHI chip U20 Address latch U11 stores I O bits 8 11 which are used to select specific registers internal ...

Page 290: ... GENERAL This circuitr y allows the CPU to communicate over the RS 232C serial interface bus to peripheral devices that require this type of interface In addition this section also allows selecting the current loop mode of operation for interfacing with teletypes and other peripherals that require this type of electrical interface 8 26 RS 232C STANDARD Most voltage interfaces in North America conf...

Page 291: ...RT chip U28 The dual SPDT dip switch S2 selects independently for TX and RX whether the clock for the USART is supplied by the internal baud rate generator or from an external remote terminal or modem type equipment The following is how the switch and jumpers must be configured to take advantage of this option a When the RXCLK switch is set for internal clock the E1 jumper does the following 1 If ...

Page 292: ...ctor a jumper is not required to receive TXCLK from J4 pin 15 NOTE The E1 jumper corresponds with the RX clock switch The E2 E2 jumper corresponds with the TX clock switch E1 E2 EXT INT S2 r J I I I I L TX clock A A B C B C r1 0 I I I I 1 J RX clock 8 30 MODE SELECT AND DRIVE The RS 232C transmit and receive data passes through the mode select switches and drive circuitry The mode select switches ...

Page 293: ...e keyboard which in effect reads the status of a specific key for each step of the address code This status information i e key up or key down is encoded in signal HKYDN which is sent to the interrupt latches where it is stored momentarily The chip select signal from the state Machine causes the present state key status to be stored in the RAM in a specific location that is a function of the addre...

Page 294: ...3 NO STOP BITS 0 1 I RS 232 0 2 I BAUD RATE EVEN ODD PARITY E 0 3 I 0 RS 232 TRUTH TABLE FOR S5 PARITY ENABLE 0 4 I D MODE S5 S4 S3 S2 RATE 0 5 I SEL 0 0 o 0 50 CHAR LENGTH 0 6 I S4 0 0 0 1 75 0 0 1 0 110 BAUD RATE FACTOR X16 0 7 I X1 0 0 1 1 134 5 1 O MODEM 0 8 I TERMINAL 0 1 o 0 150 0 1 0 1 300 0 1 1 0 600 0 1 I HALF DUPLEX 0 1 1 1 1200 FULL DUPLEX 1 0 o 0 1800 0 2 I 1 0 0 1 2000 0 3 I 1 0 1 0 2...

Page 295: ... TO TtY 1 SAt RTN ISACRfN I J3 MAINFRAME ADDRESSES BOOT UP SOURCE MSB LSB CONTROL NOT USED MSB LSB ADDRESS a a SYS BUS DISC a 1 LOCAL MASS STORAGE TALK ONLY a LOCAL MASS STORAGE ADDRESSABLE PERFORMANCE VERIFICATION 00 00 00 00 00 00 00 00 a a a a a a 1 a a a a NOT VALID a 2 1 3 VALID a 4 MAINFRAME 1 5 ADDRESSES a 6 7 Figure 8 2 Rear panel Switch Locations and Functions I O 8 10 ...

Page 296: ...OLUMN I SELECT I r U1 2 7 HKYONJ ROil A I KEYBOARD DRIVE SELECT 8 MATRIX PID I U7 1 8 X 16 U5 I I I LKBCLK JCURRENT RIIMP I I I l GENERIITOR Ql 2 3 4 I 1 I REIIR REAR PANEL PC BOARD PIINEL CIIBLE STIITUS kB J REIIR PIINEL I BUFFER R TS An 7 SWITCHES U12 I I I I 1 I HPIB CONTROL I I I I t CPU DATil HPIB HPIB REG DATil DATA r l _ I SELECT v J I I d REG 0 0 BUFFERS 4 0 IIOOR u INVERTERS BIT 8 1 I u 1...

Page 297: ... TTL VOLTAGE LEVELS BINARY QUANTITY Input 0 Input 1 Output 0 Output 1 VOLTAGE LIMIT o 8v 2 0V o 4v 2 4v 8 41 MNEMONICS Signals in the 64100A have been assigned mnemonics that describe the active state and function of the signal line see table 8 12 A prefix letter H or L or superscript bar is used to indicate the active state of the signal and the remaining letters indicate its function A H prefix ...

Page 298: ...R30 and C35 The output of U41 controls Q5 which in turn modulates the five volts appearing across R27 with the 2500 Hz tone signal 8 47 DISPLAY ENABLE LATCH U42 Latch U42 is set simultaneously with the activation of the Beeper Start Pulse Generator When U42 is set the Display On signal HOE is produced which is sent to the Display Driver PCB to activate the CRT display U42 is reset whenever system ...

Page 299: ...the Decoder En able Logic LIOSB o X Table 8 4 Decoder Enable Logic Truth Table LDOUT o X LINT X 1 LDOUTD X 1 U31D 13 OUTPUT o o U31D 13 1 for all other combinations 8 52 PERIPHERAL ADDRESS DECODERS U17 u18 Decoders U17 and U18 decode one of eight lines each for a maximum capability of 16 lines depending on the states of the three binary select inputs pins 1 2 and 3 and the three enable inputs pins...

Page 300: ... 1 1 1 1 1 0 1 LBEEP 1 1 0 1 1 1 1 1 O LKYBD 1 1 1 1 1 1 1 1 8 54 INTERRUPT BUFFER ENABLE LOGIC u16 U30 Inverters u16F and u16D together with gates U30A and U30B decode LPA3 LINT and LDOUTD to produce the Interrupt Buffer Enable signal LIBE Table 8 6 is the truth table for LIBE Table 8 6 Interrupt Buffer Enable Truth Table LPA3 LINT LDOUTD LIBE 1 o 1 o LIBE 1 for all other combinations 8 55 HIGH P...

Page 301: ...gh due to the D input of U29B being tied to 5 Vdc The Q output of U29B is interrupt signal HIR Delta It is routed to the Low Priority Interrupt Logic and causes a low priority interrupt LIRL to be sent to the CPU via the I O bus After a nominal delay the CPU responds with peripheral address L Delta T which resets latch U29B which in turn causes HIR Delta T to go low and reset counters U37A and U37...

Page 302: ...d by means of peripheral address LlMASK from U11 Latch u14 is cleared by LPOP 8 65 The unmasked interrupts are routed to Interrupt Data Buffer U21 and also are ORed by U22 to produce low priority interrupt signal LIRL This signal is routed to the CPU and causes the CPU to initiate an interrupt poll to determine which peripheral device requested the interrupt The interrupt poll consists of the CPU ...

Page 303: ... be latched at the positive going edge of LLSEL 8 68 SLOT SELECT DECODER U53 Address bits 8 11 from latch u44 serve as the address input to Slot Select Decoder U53 Address bits 12 and 13 from u44 are combined with CPU addresses LA14 and LA15 to provide the chip select function of U53 as shown in truth table 8 8 Table 8 8 Slot Select Decoder 053 Enable Truth Table I O Bits CPU Address Bits 13 12 LA...

Page 304: ...gether with the four bipolar tri state transceivers U5 U8 on the Rear panel the PHI chip provides the complete logical and electrical interface between the CPU and the HP IB In addition it provides buffering for inbound and outbound data transfer through two First In First Out FIFO registers which can be addressed by the host CPU 8 76 The following I O signals are provided by the PHI chip for CPU ...

Page 305: ...DAC IFC ATN SRQ REN EOI Figure 8 4 HP IB Signal Lines 8 79 Devices connected to the bus may be talkers listeners or controllers The controlling Mainframe dictates the role of each of the other devices disc or printer by setting the ATN Attention line true and sending talk or listen addresses on the data lines 8 80 Addresses are set into each device by switches built into the device While the ATN l...

Page 306: ...ANSFER ENDS ACCEPTOR 8 83 The ATN line is one of the five bus management lines When ATN is true addresses and universal commands are transmitted on only seven of the data lines using the ASCII code When ATN is false any code of 8 bits or less understood by both the talker and listener s may be used The IFC Interface Clear line places the interface system in a quiescent state via the abort message ...

Page 307: ... W1 J5 12 14 17 16 1 TXD RXD RTS CTS 1 RBI 1 TXO RYil R rc rs J11 I 5 7 1 2 15 9 10 3 19 20 21 22 7 B 5 13 11 6 I I I I J I I I S GNIIl GRO NO I S GNAI GROL NO I DSR R4 10 ERMJXClK TERMRXCLK I DTR RTf 10 CARDET Nt IP D CHASSlt I 5 5 5 7 j UJZa I C5 a u C1 4 LVI 11 UF r O 01UF I GND R7 1 n I GND F ff2 10 II 7 Rln 10 I R6 10 R9 1 J MODTXCLK HDDRXCLK iRCSC RCVSINK II II I I TXSC TXSINK LL __ Figure 8...

Page 308: ... 232 interface involves bi directional data flow both half duplex and full duplex it is important to know which device is acting as the DCE and which is acting like the DTE In RS 232 all of the signal names are from the DTE s point of view i e the DTE transmits on the Transmitted Data line TXD pin 2 and receives on the Received Data line RXD pin 3 The DCE on the other hand is just the opposite Sin...

Page 309: ... DEVELOPMENT J STATION I MODEM 2 MODEM 1 I TX 1i V 2 I RTS 4 5 CTS it I DSR NC I DTR DTE 20 7 GND t t TRAMSMISSION BUS LINK TERMINAL TALKER TIMING DIAGRAM R E T U R To T1 Tn N I I I I I I DTR J I L I I I I RTS J I L I r A I I I CTS I I I I I I TX I I XMIT DATA L Figure 8 7 Terminal as Talker I O 8 24 ...

Page 310: ...ION 1 12 V 2 3 MODEM 2 TX RX DeE USER SUPPLIED EQUIPMENT I MODEM 1 NC 1 DSR 8 _I CARDET 20 I DTR 7 GND 1 1 TRANSMISSION BUS LINK DTE _ R E DEPRESSED T U R N To I I T1 I I CARDET I I I I RX I REC DATA Figure 8 8 Terminal as Listener Tn I I I O 8 25 ...

Page 311: ...STATION DeE 12 V 3 6 J 20 I I RX 8 i CARDET I 7 I USER SUPPLIED EQUIPMENT DTE 3 6 20 8 7 R E T U R N DEPRESSED To DSR 12 V i r 1 Tn I I L I I I____________ INTERNALLY I I HARDWIRED L 1 I LDTR _ __ I_ _ _ _ _ _ _ _ _ I 1 DATA Figure 8 9 Modem as Talker I I L ...

Page 312: ... 1 I I I I _I I I I RX TX DSR DTR RTS CTS GND 3 2 6 20 4 5 7 Model 64100A Service USER SUPPLIED EQUIPMENT DTE R E T U R N DEPRESSED DTR 01 Y Tf I I 1 r J L UJ 0 I I I I I I I I t I J DATA 1 Slg I I L I DSR 12 V I 1 I I t L_ ET ___1 INTERNALLY HARDWIRED Figure 8 10 Modem as Listener I O 8 27 ...

Page 313: ...y the stop bites Note the use of negative true logic in which the negative level represents a logic one the positive level a logic zero Figure 8 12 shows the typical timing sequence when a terminal is talking to a modem I O 8 28 ONE BIT TIME t 1 0 START BIT o 0 0 DATA BITS STOP BIT S o P PARITY BIT Figure 8 11 RS 232 Data Format TERMINAL TALKING TO MODEM DIRECTION TO TO TERMINAL MODEM TERMINAL REA...

Page 314: ...on of these switches are described in table 3 1 and on figure 8 1 8 92 SIGNAL MNEMONICS Signals Mnemonics are listed on table 8 12 Table 8 12 I O Signal Mnemonics NOTE This table is divided into the following groups Overall Mnemonics Internal I O Address Signals Interrupt Signals Low Priority Interrupts I O Data Bus PHI I O Signals USART I O Signals Rear Panel I O Signals Keyboard I O Signals MNEM...

Page 315: ...ndicates to the addressed peripheral device that the CPU is ready to receive data used by I O to select peripheral address decoders to control the I O data transceivers and select the keyboard data Initiates direct memory access from CPU to PHI chip Enables Interrupt Buffer U21 Used in conjunction with each other to 1 control the beeper 2 generate the S A start stop interval 3 select the PHI chip ...

Page 316: ...alizes CPU resets Interrupt Enable Latch u44 resets S A Interval FF U32A enables Pwr On Pulse One Shot U52 and generates high priority interrupt LIRH via FF U29 Low Goes to each causes each unique code present of 9 card slots and card to generate it s LIDEN must also be INTERNAL I O ADDRESS SIGNALS HP IB Address Interrupt Mask Address Keyboard Address Power Fail Low Low Low Low Used in conjunction...

Page 317: ...elect Address Latch P O U44 and Card ID Latch p O U44 When low resets Delta Time Interrupt Latch U29B as response to the CPU answering HIR Delta T Interrupt Enables the Interrupt Buffer U21 The CPU pulls this line low in response to LIRH or LIRL to allow polling the I O bus to determine which peripheral device requested the interrupt Generated by Power Supply to indicate that a power failure is em...

Page 318: ...s high when RS 232 USART is ready to receive see RXRDY under USART Signals Goes high on first neg to pos transition of LINE SYNC sent to Low Priority Interrupt Logic Gate u24B Goes high when RS 232 USART is ready to transmit see TXRDY under USART signals Goes low when Emulators are in need of service Goes low when TACO is in need of service Not Assigned Same LIODO 15 16 bit bidirectional I O bus u...

Page 319: ...l PHI registers Carry bi directional data during to or writes from PHI chip by CPU Indicates acceptance of data by all devices Ties to HPIB DAV line via transceiver chip indicates availabilty and validity of data on data bus Connected to HP IB I O lines via transceiver chips When asserted enables the Data I O transceivers Used to request direct memory access cycles to transfer data to the out boun...

Page 320: ...r device clear Not applicable for PHI synchonous mode used in When low causes a read from or write to a specific register in PHI When high causes internal circuits to be initiated Ties to HP IB REN Line via transceiver Enables alternate devices to provide programming data Indicates that devices are ready to accept data Ties to HP IB NRFD line via transceiver chip Resistor load that controls intern...

Page 321: ...ve Controls internal timing of USART must be at least 30X TXC or RXC A Low enables the USART chip Enables USART to external peripheral high send serial data to if TXEN is also Parallel input output data or control words to and from CPU Used for testing status of modem data status Controlled by CPU used for external peripheral control e g data terminal ready or rate select A Low informs the USART t...

Page 322: ... external RS 232 peripheral device Tells CPU that USART is ready to accept a data character Serves as an inter rupt See HIRTX A Low informs the USART that the CPU is outputting data or control words i e writing to the USART REAR PANEL I O SIGNALS Modem Receive Clock Modem Transmit Receive Source Current Receiver Current Sink Terminal Receive Clock Terminal Transmit Clock Modem receive clock to or ...

Page 323: ...for transmit source current KEYBOARD I O SIGNALS Key Addresses Key Down Strobe Key Address Keyboard Clock Strobe High High High Low Low Low Key address bits HKAO HKA3 and LKA3 see below select one of the 16 vertical columns of keys Address bits HKA4 HKA6 select one of the 8 horizon tal rows of keys When high indicates that a key is depressed Same as LSTB see HKAO 6 above Clocks the Current Ramp Ge...

Page 324: ...Model 64100A Service I O 8 39 ...

Page 325: ... w U U8 U9 I II I r B 11l tlL D I B 55 a cr J I I I U19 S3 i I UH III J 5g a a 1 EJ N 1J 1 1 I E __ TP1 DIB J D U26 n n o D I i i J1 49 1 I is r 10 D Dr BiD DOl TP6 U20 I I I I It U c o a a a a I I I I 81 1 I P1 I TPGND U28 I 1 0 1 1 I Figure 8 13 I O Component Locator I O 8 40 J2 B I I G I I C50 85 ...

Page 326: ... GROUNDED TO PROVIDE CONSTANT ENABLE U5 6 5V 4 U29 32 37 42 43 50 52 55 5 NOTE PINS 1 19 ARE 5BA ZlL f lGROUNDED TO PRO VI DE CONSTANT ENABLE r U54 5V 20 10 U44 45 5BA 14 7 U32 42 43 51 52 ICs ON THIS SCHEMATIC IC REF DES HP PART NO MFR PART NO U5 54 U6 U17 18 U29 32 U30 U31 U33 U37 U41 U42 U43 50 U44 U51 U52 U55 U45 1820 2024 1820 1917 1820 1216 1820 1112 1820 1208 1820 1144 1820 1423 1820 1989 1...

Page 327: ... t I I I I B c B C I J __ lo L __ II I CJ Q 4 a a I I I I Bl BUIEJ U8 a U9 I a jl liE 1 11 llJBH B a a a Ie U 0 Y t I U19 S3 j i lULl IN HHI El El E3__ TP7 D D 0 0 8 til 1 I u I fZ U33 I I I I O 8 42 uu I I I I i ifi D o 1 P1 J1 49 85 Figure 8 13 I O Component Locator J2 ...

Page 328: ......

Page 329: ...I I CO CD B B B 1 I U3 U3 U40 HHr I III I U U U I I I B N M M U46 f 7 J1 TPGND TPS I l I 49 1 r J2 L I II a II B H 3fi Q Model 64100A Service REAR PANEL PC BOARD 64100 66524 C2 49 J5 C _ J 1_ R9 RH J2 J4 R5 R4 R7 R6 R8 R10 R12 Figure 8 13 I O Component Locator Figure 8 15 Rear Panel Component Locator I O 8 44 J3 ...

Page 330: ... Il u TIlT RTL RS U20 PROCESSOR TO HPIB INTERFACE VOO a PHIl VOC f VCC a GNO ll 4 6 5 U51B I I I 6 I 15 16 I 5 I to 18 FA I I I I I I I I I I I I I I I 1 I I I I I I I I I I I I 1 _J 29 25 5 2 2 2 2 2 1 2 2 2 30 B 7 4 3 9 o 1 2 1B A8WI Model 64100A Service r PIO REAR PANEL I us I 5 I WJI 4 3 7 41 Jl I i 0101 I 1 0102 2 t j 42 43 DI03 I 3 0104 4 44 45 jU 46 I nTno I I 13 nTnJ lTn7 I 14 0105 14 13 _...

Page 331: ... BU7 U6 I a If J u I Model 64100A Service REAR PANEL PC BOARD 64100 66524 r U1 I us II R1 r U2 I 82 I U6 R2 I U7 I I U8 I I U9 49 J5 r U3 r U4 II S3 r Sl J1 I I I J2 I J4 rl I r I II II I _ I II II I I II I I II II I _ I II II I L __ J L __ J L __ J Figure 8 13 I O Component Locator Figure 8 15 Rear Panel Component I O 8 46 J3 ...

Page 332: ... 16 1111 153KHZ GENERATOR 11 12 EXT B 4 SEE NOTE 1 15 161 I L U9 13 R12 11K PIO S5 HIILF OUPLEX RT5 7 2 TERMTXCl K I I 6 4 TERMRXCLK I 9B _ NOTES 1 Sl S3 SWITCHES ARE EACH GANG TYPE SWITCHES 2 THI5 CHIP S VCC IS SWITCHED ON ONLY WHEN S3 OS SET TP RS232 _ _ r I PIO REAR PANEL BOARD J5 64100 66524 I PV LOOP BliCK 16 15 Kl 2 3 3 NC NORMIIL RS 10 CTS J2 5 4 f _ 1 ______ 1 _ R 1 1 iY l_0__ 0lB J4 20 R6...

Page 333: ...J EJ EJ B B C2 J1 I I I mi to G 01 0 I U LINE CALL LOCK SET ll to I C I M u l ua I G a a a I I I 02 0 I I U1 b 0 C3 03 04 8 D D J D D D D D 8 0 IBACKI SPC CHAR G CHAR ITAB I 0 D D D D 0 8 G 8 G GJ EJ IROLL I QJ ICONTI c J D G D G 0 D D J J 2 UP PAGE TURN IS FT I D D D D 0 0 D D D IS FT B EJ IROLL I QJ IPREY I DOWN PAGE ISPC I BE lED I R11 I C8 R8 C13 C9 C14 U3 G C10 C1S C11 C16 NOTE I C12 ALL PART...

Page 334: ......

Page 335: ...100A POWER SUPPLY COPYRIGHT HEWLETT PACKARD COMPANY 1981 1982 1983 LOGIC SYSTEMS DIVISION COLORADO SPRINGS COLORADO U S A All Rights Reserved Manual Part No Part of Mainframe Manual Microfiche Part No Part of Mainframe Manual ...

Page 336: ......

Page 337: ...tion 2 2 OPERATION 3 1 3 1 General 3 1 PERFORMANCE VERIFICATION 4 1 4 1 Required Equipment 4 1 4 3 Power Supply Voltages 4 1 ADJUSTMENTS 5 1 5 1 Introduction 5 1 5 3 Current Limit Adjustment Procedure 5 1 REPLACEABLE PARTS 6 1 6 1 Introduction 6 1 6 3 Abbreviations 6 1 6 5 Ordering Information 6 1 6 8 Direct Mail Order System 6 3 6 11 Parts List 6 3 MANUAL CHANGES 7 1 7 1 Introduction 7 1 PS iii ...

Page 338: ...t Operation 8 3 Safety Considerations 8 4 Secondary Board 8 4 Operation 8 4 Safety Considerations 8 5 Control Board 8 5 Operation 8 5 Safety and Handling Considerations 8 6 Mnemonics 8 7 LIST OF ILLUSTRATIONS Page Bottom Cover Screw Locations 2 3 Motherboard Screw Locations 2 4 Locations of J1 J2 and LED Indicators 2 5 Rear Panel Screw Locations 2 6 Access Port Location 5 2 Current Limit Pot Locat...

Page 339: ...cations of MP1 MP2 and MP3 heatsink assemblies 8 16 MP1 MP2 and MP3 Heatsink Assembly Removal 8 16 Separate MP1 assembly 8 16 LIST OF TABLES Page Specifications 1 1 Power Supply Voltages on Motherboard Pins 4 2 Troubleshooting Guide 4 2 Reference Designators and Abbreviations 6 2 Replaceable Parts List A1 6 4 Replaceable Parts List A2 6 6 Replaceable Parts List A3 6 9 Replaceable Parts List A4 6 1...

Page 340: ......

Page 341: ...02 is a 400 watt power supply that contains three switching supplies three linear supplies and one unregulated supply All of these are on four PC boards within the 64100 62602 container These are a Filter board and primary wiring b Primary board c Secondary board d Control board A1 A2 A3 A4 64100 66514 64100 66515 64100 66517 64100 66528 1 4 In addition the power supply provides three control sign...

Page 342: ...nt d Supply Voltage Current Ratings Type 5 at 45 Amps max switching 5 25 at 25 Amps max switching 3 25 at 30 Amps max switching 12 at 1 Amp max linear 12 at 1 Amp max linear 40 at 25 Amp max linear 1 6 Amps peak 17 at 1 Amp max unregulated PS 1 2 ...

Page 343: ...etely remove the 12 screws and lockwashers that connect the power supply to the Motherboard see Figure 2 2 e Completely remove the two screws and washers that connect the bottom of the power supply to the main chassis see Figure 2 2 f Carefully lay unit on its bottom CAUTION Be sure area under unit is clear of screws or other matter which could damage the Motherboard or other circuitry CAUTION Dis...

Page 344: ...e four screws that secure the power supply to the Rear panel see Figure 2 4 m Move power supply about half an inch toward the front of instrument and lift supply from chassis 2 2 INSTALLATION PS 2 2 a Place the power supply into the chassis and secure it to the back panel b Slide the Display driver board into the Motherboard slot just in front of power supply c Connect CRT cables to J1 and J2 on t...

Page 345: ...Model 64100A Installation and Removal Figure 2 1 Bottom Cover Screw Locations PS 2 3 ...

Page 346: ...Model 64100A Installation and Removal PS 2 4 REMOVE THESE 14 SCREWS TO SEPARATE THE POWER SUPPLY FROM THE UNDER DECK Figure 2 2 Motherboard Screw Locations it 1 ...

Page 347: ...Model 64100A Installation and Removal TROUBLE INDICATOR LEOS 11 J1 J2 Figure 2 3 Locations of J1 J2 and the LED Indicators PS 2 5 ...

Page 348: ...Model 64100A Installation and Removal __ I I _ 2 ___ j t II i Ill JlOtIll I 0 REMOVE THESE SCREWS TO SEPARATE THE POWER SUPPLY FROM THE REAR PANEL Figure 2 4 Rear Panel Screw Locations PS 2 6 ...

Page 349: ...that the AC voltage select switch is in the proper setting for the available line voltage 110V 220V 3 3 The internal power supply fan must be operating after the mainframe has been tuned ON The supply will overheat and cause permanent damage to components if the fan is not operating Turn OFF mainframe if fan is not operating PS 3 1 3 2 blank ...

Page 350: ......

Page 351: ... following procedure 1 Set the power switch to the OFF position 2 Remove the five screws that secure the top cover Lift and remove top cover 3 Remove all the boards in the card cage Refer to Section II for the proper method to remove the Display driver board CAUTION This supply does not need a minimum load to operate Failure to remove all option and mainframe boards from the card cage could result...

Page 352: ...F ON OFF If the 12V or the 5REF voltages are completely off then the following conditions will not exist If the 5V LED is OFF check the 5V switching circuitry Refer to paragraphs 8 20 thru 8 29 The 5V supply must be working for this LED to be on If this LED is ON the 5V supply has crowbarred try a power reset Check the 5V level and or the 5 OV circuitry Repeated firing of the SCR can damage the SC...

Page 353: ...DOWN Check other failure LED s Refer to paragraph 8 47 Primary Current Limit detects an unlinear surge of current internal to the supply If PCL comes ON reseat the boards to get rid of possible intermittant connections Check for unusual loading of the supply and or the PCL circuitry Check to see that the screws connecting the supply to the Motherboard are tight Refer to paragraph 8 30 If the 3 2SV...

Page 354: ......

Page 355: ...removed Use extreme caution while servicing unit with the top cover removed d Remove access port on the bottom cover and apply a 45 amp load use the ET19705 on the 5V supply see figure 5 1 e Locate the 5V current limit 5CL pot R2 as shown in Figure 5 2 f Turn ON the supply g Monitor the voltage on the 5 volt supply and turn the pot clockwise until the 5 voltage just begins to drop Turn the pot cou...

Page 356: ...Model 64100A Adjustments PS 5 2 I I I I I I I I I I I I I I I I I I I I I 11111 fONIN VMt NOlln V ACCESSPORT COVER ACCESS PORT ATTACH SCREWS Figure 5 1 Access Port Location ...

Page 357: ...2 _ CR10 RS3 1 R 54_ _R5S_ Model 64100A Adjustments P2 39 _ _ 64100 66515 PRIMARY SUPPLY BOARD T7P TBP T9P P310 0 0 I P4 fo 001 psJoo 01 C36 C37 C3B C39 C40 C41 C43 RS9 R5B 5 CR20 D R69 R24 R2S R26 CB C44 C9 C52 U2 U3 _CS4_ R28 R70 R30 R31 C11 C47 U4 R 4 4 U6 C22 _C23_ C24 C2S_ C53 R4S C51 _ U10 R46 C26 R37 C27 R38 C2B C29 R47 U7 I_ U11 R48 _ __ C30 CS5_ C31 C56 C32 R39 C33 C15 R 4 9 L Figure 5 2 ...

Page 358: ......

Page 359: ... partial or no capitals This occurs because the abbreviations in the parts list are always all capitals However in the schematics and other parts of the manual other abbreviation forms may be used with both lowercase and uppercase letters 6 5 ORDERING INFORMATION 6 6 To order a part listed in quote the Hewlett Packard part required and address the order Sales Service Offices listed at the replacea...

Page 360: ...nter clockwise INCL includels SIL silver CER ceramic INS insulation ed OBD order by description SL slide CMO cabinet mount only INT internal OH oval head SPG spring COEF coeficient OX oxide SPL special COM common K kilo 1000 SST stainless steel COMP composition SR split ring COMPL complete LH left hand P peak STL steel CONN connector LIN linear taper PC printed circuit CP cadmium plate LK WASH loc...

Page 361: ...vide these advantages a check or money order must accompany each order 6 10 Mail order forms and specific ordering information are available through your local HP office Addresses and phone numbers are located at the back of this manual 6 11 PARTS LIST 6 12 Table 6 2 lists the replaceable parts for the power supply 6 13 The information given for each part consists of the following a Hewlett Packar...

Page 362: ... FOR 110V OPERATION HPI 64100 62101 3 1 POloJER SUPPLY FAN ASSEMBLY 28480 64100 62101 HI 2 9135 0143 8 1 FILTER L INE 28480 9135 0143 MP 1 2110 0565 9 1 FUSE CARRIER 84BO 2i 1 O OS6S HP4 2110 0566 0 1 FUSE HOLDER BODY Z 8480 2j l0 OS66 MPS 64100 04707 3 1 SUP porn PC BOARD 28480 64100 04707 H1 64100 04115 7 1 TOP COVER 28480 64100 04115 H2 2110 0569 3 i NUT FUSE HOl DEll 28480 liO OS69 81 3101 042...

Page 363: ...H I K IN lI T ND III 19 i IN lD sc rlEI4 MAf 1I 4 40 1 12 5 IN I G PAN IID POll f r nEW MAC I 6 3 37 j Ii I r PtlN 11 pnZI SCRFW MACH 6 32 375 IN LG PAN HD POZ SCREW AC 1 10 32 312 JN I_G PAN HD POZI SCREW MACH 10 3 312 JN U PAN HD PUll SCRl l MACH 1 3 31 IN 1 rf N Hn POll SCREW MACH 10 32 312 INU PAN I IJ I4Ar Hr rl I NM NO b 141 IN 11 WASHCR rl NM N i o 141 IN lD o IAf Hr R FL NrI NO b 141 IN TD...

Page 364: ...PACITOI FXO 1500PF 2X 300V C MICA 72 1 56 DM19Fl i2GIJ 0 GW ll CR C44 0140 01 16 5 CAPACITOR F X1 15i10PF f 2X 500vliC Ml A 72136 DMI9F152C0300WV1CR C45 0180 1743 3 CAPACITOR FXD IUF 10 35VDAC TC 5t B9 150Dl05X9035A2 C46 0180 0229 7 CAPAr ITDR FXD 33UFi l0X 1 DVJ C TA 5626 1 15 OD336X90 10112 C47 0180 0291 3 CAPACl rOR FXD 1I IF l0 35VDC Til 5 289 150Dl05X9035A2 C4B otil 0 4832 4 CAPAr ITClR f XI ...

Page 365: ...R 3 PIN M POST TYPE CONNECTOR 4 PIN M POST TYPE CONI IECTI1R 4 PIN M POST TYPE lRANSISH R PNP 81 PD 31 OMW FT 2 i0I1H Z TRANSISTOll NPN 51 TO 2211AB PD 1 OIlW lRM 1IS10R NPN 51 TO 220AB PD l00W TRANSISTOI NPN 81 TO 220AR PD I00W TRANSISTDR NPN HI TO 22DAI PD IOOW TRANBJHTO NPN HI TO 220AB PD l COW TRANSI8TOR NPN 81 lO c2DAl PD l now RESlSTllIl TIlMR 201 10 C SIDE ADJ I TPM RESISTDR TRMR DK 10 C St...

Page 366: ...7 0394 0 RESISTOR 51 1 1 125101 F TI 0 1 00 24546 C4 1 IB T 0 51R I F R63 0757 0394 0 RESISTOR 51 1 Ill 125101 F TC 0 100 24546 C4 I B TO 51 R1 r R64 0751 0394 0 RESISTOR 51 1 1lr 125101 F Te 0 100 24546 C4 I B TO 51R I F I R65 0757 0394 0 RESISTOR 51 1 n 125101 F TG 0 100 24546 C4 1I9 TO 51FI F Riolo 0757 0280 3 RESISTOR lK 1 1 12 W F TC O IOO 24546 C4 I B TO l001 F Rf 7 0757 02BO 3 RESISTOR IK 1...

Page 367: ...W MACH 4 40 312 1N I G PAN ID P07 l SCREW MACH 4 40 31 IN LG PAN HD POZI SCREW MACH 4 40 5 1N U PAN ID OZI SCREW tlACH 4 40 5 IN I G PAN Hll POZ 1 SCREW MACH 4 40 1 1 S l N I G P NM HD POZI SCREW MACfl 4 40 1 125 IN L G PAN HD POZI llCREW MACH 4 040 1 lc 1N LG PAN HD P JZI SCREW MACI 4 40 I 1 5 IN L G PAN HD POl I l CRLW MACH 4 411 t 3 15 YN I G PAN lD I Oll CREW MACH 4 40 I 375 IN L G PAN flD POl...

Page 368: ...11 125W F Te 0 l00 RESISTOR 10 51 lW MO TC 0 200 SHUNT DMB 25M RESISTOR lK II 125W F Te O IOO RESISTOR 750 1 125W F TC O 100 RESISTOR 316 II 125W F Te 0 l00 RESISTOR lOOK II 125W F Te O IOO REST BTnR 75 1 7 5W F TC O 100 RESISTOR 261 II 125W F TC O IOO RESlSTOR t 21K 1X 125W F TC O lno RESISrDR 10 57 I I tiC TI 0 200 SHUNT DMS 2 e M RESISTOR 51 1 II 5W TC O IOO SHUNT DMS 5M RESISTOR 750 1 125W F T...

Page 369: ...N flD POZI SCRE W MACH 32 25 IN LG PAN HD POZI SCREW MACH 6 32 25 IN LG PAN Hll POZI NUT HEX DBL CHAM 6 32 THD 094 IN TliK NIJT HEX DBL CHAM 6 32 Trm 094 IN THK WASI IER fL NM NO 6 141 IN ID 375 IN OD WASHER FL NM NO 6 141 IN ID 37S IN OD WASHER FL NM N 6 141 IN ID 375 IN OD INDUCTOR 120 OIJH INDllCTOR 6BnUH INDUCTOR b80IJI t fir AT SINK SGL PLSTC PWR CS HEAT SINK SGL PLSTC PWR CS TRANSISTOR PNP S...

Page 370: ...46 C4 1 8 TO l 003 F R35 0757 02Bl 4 1 RESISTOR 2 74K n 125W F TC O IOO 4546 C4 IB TO 2741 1 R36 0757 0448 5 1 RESISTOR HI K a 125W F TC O IOO 24546 C4 1 IB T 0 t82 F R37 0698 0085 0 1 RESISTOR 2 6H a 125111 f Te O IOO 245 46 C4 1 B TO 2 tl F R3B 0757 0472 5 RESISTOR 20DK IX 125W F TC Ot l00 24546 C4 1 8 TO 2003 F R39 0757 0442 9 RESISTOR 10K n 125111 F TC 0 100 24546 C4 1 IB TO 1 0C2 F R4D 0757 0...

Page 371: ...s Tx 75234 19701 Mepco Electra Corp Mineral Wells Tx 76067 20940 Micro Ohm Corp El Monte Ca 91731 24546 Corning Glass Wks Bradford Pa 16701 26654 Varadyne Inc Santa Monica Ca 90404 27014 National Semicond Corp Santa Clara Ca 95051 27777 Varo Semicond Inc Garland Tx 75040 28480 Hewlett Packard Hq Palo Alto Ca 94304 30983 Mepco Electra Corp San Diego Ca 92121 32997 Bourns Trimpot Div Riverside Ca 92...

Page 372: ......

Page 373: ...Model 64100A Manual Changes SECTION VII MANUAL CHANGES 7 1 INTRODUCTION 7 2 There is no backdating information for the power supply as of the pUblication of this manual PS 7 1 7 2 blank ...

Page 374: ......

Page 375: ...ubleshooting references on the Primary board 8 6 SECONDARY BOARD A3 rectification and feedback secondary board provides the Motherboard The secondary board is responsible for filtering for the DC power supplies Furthermore the 5 25V 5V 3 25V 12V and GND outputs to the 8 7 CONTROL BOARD A4 LED failure indication and failure execution are the main functions of the control board However this board al...

Page 376: ...urrent from the output for output current limiting and a predetermined switching frequency The PWMs control the switching transistors that alternate the current through the primary side of the switching transformers TID T15 Since all three PWMs are similar in operation the 5V PWM will be explained 8 21 OPERATION 8 22 The PWMs modulate the output pulse width according to the demands of the system I...

Page 377: ... to turn off the outputs And U5 pin 4 DEADTIME control must be held low It is forced high by several error states to turn off the outputs The 20 KHz switching frequency of the PWMs is determined by a Ric time constant on pins 5 and 6 of u4 The 20 KHz clock is tied to all three PWMs to switch them syncronously 8 25 PRIMARY PCB CONTROL CIRCUIT OPERATION 8 26 As soon as the filter board is switched O...

Page 378: ...circuitry on the Primary board has to do with the 5 25 CL which is slightly different than the other two PWMs One of the considerations of this supply is that when the 5 25 supply is down the others are also disabled This is done to protect the Dynamic RAMs So when 5 25 CL exceeds the limits set for it pin 1 U12 goes high This generates SHUTDOWN and also forces the FEEDBACK control high on all thr...

Page 379: ...al hazard to life even with the supply off 8 42 CONTROL BOARD Figure 8 10 8 43 OPERATION 8 44 u4 U5 and U7 are overvoltage protectors OVP that wlrk in the following manner when the voltage at pin 2 exceeds the voltage at pin 7 by 2 6v the output pin 8 latches high to turn on the failure LEDs and in the case of the 5 and 5 25 volt supplies to supply current to crowbar the respective circuits Also w...

Page 380: ... of pin 2 LED and in turn produce of the the ratio voltages 8 48 CR9 is the rectifier for the 40 VDC supply Q4 is the regulator Q5 and R29 form the high level current limiter that turns Q4 off if the current is too large U3 is the overvoltage sensor that will turn Q4 off if the voltage formed by the voltage divider R36 37 goes too high U3 and C13 form an integrator that limits the average current ...

Page 381: ...used by the supply to determine the voltage drop of the high current carrying control ground due to the parasitic resistance of the Motherboard Then this voltage drop is used to adjust the 5V REF regulator LINE SYNC is processed from the line input and used for timing throughout the mainframe This signal is used as a power fail indicator which is sent to the I O board LPOP is generated shortly aft...

Page 382: ...DOWN is generated in several places and is responsible for turning off the PWMs by pulling U2 u4 U5 pin 3 high AC line frequency and sync are the same Thermal TH and TH2 all relate to the thermal switch located on the secondary board The switch will open when the internal temperature of the supply is greater than 105 degrees C Also the TH LED will be indicating a problem This signal is used throug...

Page 383: ...5eB 5 3 r PON 1 I 1 PIO Pl 1 1 1 I UR15 1 1 1 LPOP I r rl GSEN 1 l f f f f f I i I 1 SYNC I LlNESYNC RAILS a D 10 5 t PRl SWITCHER 1 1 12C CD I 3 25 t PRl SWITCHER 12C CONTROL N l U 10 I 5 25 SWITCHER Z 3 o o I l c I U N 10 N c I PRIMARY BOARD AZ Z o n u Z I I 12R I I 1 I 1 1 1 I 12 I 1 12 1 1 I I 17R I I I I I 1 I 1 17 I I I I 1 17 1 I 40A 8 I I 1 I 40 I I I I I I 1 40 1 I THERMAL 1 I I 1 L _____...

Page 384: ... X 3CL 12 X X 3A 13 X X 12 14 X X X RETURNGND 15 X X 3B 16 X X X RETURNGND 17 X X 5CL 18 X X RETURNGND 19 X X 12 20 X X SHUTDOWN 21 X X X TH2 22 X X 5CB 23 X X THERMAL 24 X 5 25 X X X 12B 26 X X CUR SEN GND 27 X X 12A 28 X X 3 29 X X X 30 5 2 31 X X X 40B 32 X X CONTROLGND 33 X X X 40A 34 X X PON 35 X X 5B 36 X X SYNC 37 X X 5A 38 X X 39 5CL 40 X X NOTE An X on a given Pin Number denotes a line co...

Page 385: ...ered stars on the schematics Figures 8 7 and 8 10 Note that the same signals can be seen on the corresponding parts on the 5 25V and 3 25V supplies 1 rTop waveform The primary of T7 with the 5V supply loaded this signal 320V p p t rMiddle waveform The signal shown is the output of U5 pin 8 at 12V p p Bottom waveform This signal is the other output of U5 pin 11 at 12V p p 1 1ToP waveform The signal...

Page 386: ... DESIG LOC DESIG LOC DESIG LOC DESIG LOC DESIG LOC DESIG LOC I I 1 I I 1 1 1 I Cl C 8 C30 C 2 C50 A 6 CR18 8 6 MP7 F 2 R8 8 8 R30 A 2 R59 F 5 T13U 0 2 C2 A 7 C31 C 2 C51 8 3 CR19 C 6 Pl E l R9 8 8 R31 A 2 R60 E 4 T14L 0 2 C4 A 6 C32 C 1 C52 A 4 CR20 C 5 P2 E 8 Rl0 E 8 R32 8 7 R61 E 3 T15U 0 1 C5 A 5 C33 C l C53 8 3 CR21 E 5 P3 0 7 R11 8 8 R37 8 3 R62 E 2 Ul A 7 C6 A 5 C34 C 7 C54 8 3 CR22 E 4 P4 E...

Page 387: ......

Page 388: ...ndary 64100A Model Service 7 PS 8 14 R14 C3 R10 CR10 R11 C2 R2 R3 Cl RS C13 R33 R34 C16 R31 39 CONTROL BOARD 64100 66528 _ R6 _ _ R3B _ U9 R1B C4 C7 R16 R1S D R23 a2 R24 RB R4 __ CR2 R20 R21 R9 R7 R12 CR4 C10 I I a1 U2 I I Ul L2 e CRB C6 CR3 CB R39 In U Oas 8 R30 o C9 V R40 ra3 R2S i cs CR1 R19 R3S MP2 Figure 8 9 Contro t Locator 1 Board Componen R14 R15 R16 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27...

Page 389: ......

Page 390: ...MP2T9 MP1 MP2 MP3 MP1 T7 7 MP3 T8 SECONDARY POWER SUPPLY BOARD Figure 8 11 Locations of MP1 MP2 and MP3 heatsink assemblies ...

Page 391: ...d or nut and lockwasher that go with the faulty MP assembly Also the faulty assembly must be ordered as a complete assembly Each assembly PiN is given in section VI table 6 2 Figure 8 12 MP1 MP2 and MP3 Heatsink Assembly Removal ...

Page 392: ...Model 64100A Service CR8 HEAT81NK 5 P3 81 CR9 C4 Note The MP1 and MP3 assemblies are nearly identical in component locations Figure 8 13 Separate MP1 Assembly PS 8 16 ...

Search results

Summary of Contents for 64100A

Reviews:

Related manuals for 64100A

Brands by name

Popular brands

HP 64100A, Service Manual

Search results

Summary of Contents for 64100A

Reviews:

Related manuals for 64100A

Brands by name

Popular brands