HP 27130A Technical Reference Manual Download

Page: 1 / 134

Summary of Contents for 27130A

Page 1: ...ETT PACKARD COMPANY Roseville Networks Division 8000 Foothills Boulevard Roseville California 95678 Technical Reference Manual Flin HEWLETT I I PACKARD Card Assembly 5061 4929 Date Code A 2301 Manual Part No 27132 90006 Printed in U S A June 1983 ...

Page 2: ...anual will contain new information as well as updates First Edition June 1983 NOTICE The information contained in this document is subject to change without notice HEWLETT PACKARD MAKES NO WARRANTY OF ANY KIND WITH REGARD TO THIS MATERIAL INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE Hewlett Packard shall not be liable for errors contai...

Page 3: ...2 14 Section III Page PRINCIPLES OF OPERATION Functional de5cription 3 1 System C1oc k5 3 3 Memory Addre55 Space 3 3 110 Address Space e e 3 6 Z 80B Microproc e550r CPU 3 6 Z 80 510 2 Serial liD Controller 3 6 CTC Counter Timer Circuit 3 19 Interfac ing to the BIC 3 19 Memory Interface Circuit MIC 3 24 Regi 5ter 0 MI C Configurat ion 3 24 Regi5ter 1 DMA B Upper Byte of Memory Addre55 3 24 Regi5ter...

Page 4: ...Termination End On Count Text Termination Alert 1 Mode Type Ahead and Echoing Receiving Transparent or Binary Data Read Request Length Host Initiated Text Termination Transmit Character Processing Automatic Output Separators Appendage Transmitting Transparent or Binary Data Buffer Flushing Programming the Receiver and Transmitter Parity in Transmitted or Received data Break Detection Handshake Tim...

Page 5: ...unction 12 Number Of Stop Bits 4 34 Subfunct ion 13 Pari ty 4 34 Subfunction 18 Character Handshake Timer 4 35 Subfunct ion 21 Host Interrupt Mask 4 35 Subfunction 22 Host X ON X OFF Characters 4 36 Subfunction 23 Device X ON X OFF Characters 4 37 Subfunction 24 Host ENQ ACK Characters 4 37 Subfunction 25 Host ENQ ACK Pacing Counter 4 37 Subfunction 27 Single Text Terminator for Echoing CR LF 4 37...

Page 6: ...Section V Page MA I NTENANCE 5 1 Section VI REPLACEABLE PARTS Page Replaceable Parts 6 1 Ordering Information 6 1 Section VII Page SCHEMATI C DIAGRAMS 7 1 Appendix A Page ASCII CHARACTERS AND BINARY CODES A 1 vi ...

Page 7: ...Figure 1 1 HP 27130A MUX 1 0 ...

Page 8: ...S 232 C RS 423 A RS 422 A type devices not including modems Figure 1 2 shows a Hewlett Packard computer system using CHANNEL I O and the MUX CHANNEL I O is a Hewlett Packard standard defining the physical and electrical characteristics for an I O system consisting of an I O channel an I O channel adapter and I O cards The MUX is one of the I O cards Note that the computer system CPU and memory com...

Page 9: ...HP 27130A I O CARD I o CHANNEL ADAPTER I O CARD I O CARD MUX CARD I O DEVICE o UP TO o e o DEVICES I O DEVICE Figure 1 2 MUX in a Typical Hewlett Packard Computer System 1 2 ...

Page 10: ...roducts The five digits identify the product the letter indicates the revision level of the product Printed Circuit Card The printed circuit card supplied with the HP 27130A product is identified by a part number marked on the card In addition to the part number the card is further identified by a letter and a four digit date code e g A 230l This designation is placed below the part number The let...

Page 11: ...al update record Reprint dates for the Installation Manual are printed on the title page SPECIFICATIONS Table 1 1 lists the specifications of the MUX Table 1 1 Specifications FEATURES Eight full duplex asynchronous serial lID ports EIA RS 232 C RS 423 A compatible Simplex echoplex half duplex or full duplex mode operation Asynchronous baud rates from 110 baud to 19 2K baud Programmable character s...

Page 12: ...y 0 645 inches Weight 283 5 grams 0 625 pound lID Channel Interconnects 80 pin connector J1 Device Interconnects 72 pin connector J2 POWER REQUIREMENTS Current amps Power Dissipation watts Voltage typical 2 sigma typical 2 sigma SV 1 672A 1 890A 8 36W 9 4SW 12V 0 052A O 062A O 62W 0 74W 12V O 075A O 08SA O 90W 1 02W 1 5 HP 27130A ...

Page 13: ......

Page 14: ...ower requirements entry of table 1 1 Current requirements for all other I O cards can be found in the appropriate Technical Reference Manuals FIRMWARE EPROM INSTALLATION ICAUTION I SOME OF THE COMPONENTS USED IN THIS PRODUCT ARE SUSCEPTIBLE TO DAMAGE BY STATIC DISCHARGE REFER TO THE SAFETY CONSIDERATIONS INFORMATION AT THE FRONT OF THIS MANUAL BEFORE HANDLING THE CARD OR REMOVING OR REPLACING COMP...

Page 15: ...HP 27130A CPU SIC SID CTC MIC SID CTC EPROM SID CTC EPROM SID JUMPER Figure 2 1 Component and Jumper Locations 2 2 ...

Page 16: ... jumpers are shown on figure 2 1 Memory Configuration Jumper The Memory Configuration jumper WI is an internally connected IS pin dual in line package DIP shunt network The jumper is used to configure the two memory sockets U64 and U74 to ac comodate different kinds of EPROMs and static RAMs The pin diagram of WI is shown in figure 2 2 pin functions are listed in table 2 1 18 17 18 15 14 13 12 11 ...

Page 17: ...talled only when a 16K byte EPROM is used in socket U64 Position D connects A13 of the address bus to pin 24 A13 of the 16K byte EPROM Installed only when an 8K byte EPROM is used in socket U74 Position E connects 5V power to pin 27 VPP of the 8K byte EPROM Installed only when an 8K byte static RAM is used in socket U74 Position F connects WR of the Z 80 CPU to pin 27 WE of the static RAM thus ena...

Page 18: ... a connection panel RS 232 C Connection Box part number 12828 60001 and from there via eight separate connectors and eight cables to the peripheral devices A connection diagram for the connection box is shown in figure 2 4 Connector J2 pin assignments are shown in table 2 3 Pin assignments for J2 and the connec tion panel are shown in table 2 4 Note that in table 2 4 there are eight pairs of Send ...

Page 19: ... PIN CONNECTOR RECEIVED PINOUTS RECEIVE CH NNEL PIN I SEND CHoINNEl PIN RDO JJ R04 2 500 34 S04 26 R01 J1 RD5 23 501 32 505 24 RD2 29 RD6 21 SD2 3O 506 22 ROJ 27 R07 1 503 28 SD7 20 PROTECTIVE GROUND M TRAN5MIlTED OATA SA RECEIVED DATA 89 REQUEST TO SEND CA CLEAR TO SEND ca o t TII SET AEADY CC SIGNAL GROUND t B CARRIER OETECT CF ON 12V OFF 12 0 OATA TERt lINAL READy CO PERIPHE I W DEVICE Figure 2...

Page 20: ...a Bus Bit 0 A13 GND Ground A14 AD2 Address Bus Bit 2 A15 ADO Address Bus Bit 0 A16 GND Ground A17 DOUT Data Out A18 BPO Bus Primitive Bit 0 A19 CEND Channel End A20 SYNC Synchronize A21 GND Ground A22 CCLK Corrmon Clock A23 GND Ground A24 BR Burst Request A25 DBYT Device Byte A26 MYAD My Address A27 GND Ground A28 Not used A29 Not used A30 Not used A31 RES Not used A32 PFW Power Fail Warning A33 P...

Page 21: ... GND Ground B14 AD3 Address Bus Bit 3 B15 AD1 Address Bus Bit 1 B16 GND Ground B17 UAD Unary Address B18 BP1 Bus Primitive Bit 1 B19 CBYT Channel Byte B20 PoLL Poll B21 GND Ground B22 10SB lID Strobe B23 GND Ground B24 ARQ Attention Request B25 DEND Device End B26 IFC Interface Clear B27 GND Ground B28 Not used B29 Not used B30 RES Not used 831 ISPU Not used 832 NMI Non Maskable Interrupt B33 SPoN...

Page 22: ... CA RxD1 A26 SG1 B7 RD1 CB A27 SD1 CB B28 SD2 CA TxD2 AS RD2 CA RxD2 B29 SG2 B30 SD2 CB B8 RD2 CB A28 SD3 CA TxD3 A8 RD3 CA RxD3 A29 SG3 A30 SD3CB B9 RD3 CB B31 SD4 CA TxD4 A10 RD4 CA RxD4 B32 SG4 B33 SD4 CB 810 RD4 8 A31 SD5 CA TxD5 A12 RD5 CA RxD5 A32 SG5 A33 SDS 8 811 RDS 8 B34 SDG CA TxOO A14 ROO CA RxOO B35 SGS B36 SOO 8 B12 ROO CB A34 SD7 CA TxD7 B15 RD7 CA RxD7 A35 SG7 A36 SD7 CB 813 RD7 8 ...

Page 23: ... MNEMONIC MNEMONIC PIN NO MNEMONIC MNEMONIC A17 SDO TxDO A21 SD4 TxD4 B17 SCO B21 SC4 A1B SD1 TxD1 A22 SDS TxDS B1B SC1 B22 SCS A19 5D2 TxD2 A23 500 TxOO B19 5C2 B23 5C6 A20 5D3 TxD3 A24 5D7 TxD7 B20 5C3 B24 SC7 A3 HOOD_ON CT5AO B14 SG B3 HLED A16 GND A2 12V B1 SV B2 12V A1 GND PWR 2 10 ...

Page 24: ... 13 A22 SD5 24 SD J5 LT VIOLET 14 B22 SC5 6 SG J5 BLACK 14 A23 SOO 22 SD J6 BROWN 15 B23 SC6 4 SG J6 BLACK 15 A24 SD7 20 SD J7 DK RED 16 B24 SC7 2 SG J7 BLACK 16 B4 RDO A 33 RD JO NATURAL 1 B6 RDO B 15 SG JO BLACK 1 A4 RD1 A 31 RD J1 WHITE 2 B7 RD1 B 13 SG J1 BLACK 2 A6 RD2 A 29 RD J2 YELLOW 3 B8 RD2 B 11 SG J2 BLACK 3 A8 RD3 A 27 RD J3 ORANGE 4 B9 RD3 B 9 SG J3 BLACK 4 A10 RD4 A 25 RD J4 TAN 5 B1...

Page 25: ... ALWAYS ENSURE THAT THE POWER TO THE COMPUTER IS OFF BEFORE INSERTING OR REMOVING THE MUX CIRCUIT CARD AND CABLE FAILURE TO DO SO MAY RESULT IN DAMAGE TO THE MUX ICAUTION I SOME OF THE COMPONENTS USED ON THE PRINTED CIRCUIT CARD ARE SUSCEPTIBLE TO DAMAGE BY STATIC DISCHARGE REFER TO THE SAFETY CONSIDERATIONS INFORMATION AT THE FRONT OF THIS MANUAL BEFORE HANDLING THE CARD Install the MUX as follow...

Page 26: ...orm the following 1 Turn on computer system power 2 A self test is contained on the card The host computer system determines if the self test is run automatically at power on or must be invoked by the user Refer to the appropriate manual for your system for a description of self test initiation a If the diagnostic test hood is not installed when the self test executes the LED located on the card s...

Page 27: ...ipment Include the part number of the MUX Pack the card in the original factory packing material if available If the original material is not available good commercial packing material should be used Reliable commercial packing and ship ping companies have the facilities and materials to repack the item BE SURE TO OBSERVE ANTI STATIC PRECAUTIONS 2 14 ...

Page 28: ...d peripheral device panel frontplane connectors The heart of the MUX card is the Z SOB CPU U33 see D24 7 1 which through a program stored in EPROM controls the functions of the card The Backplane Interface Circuit BIC U41 see A14 7 1 is a custom gate array integrated circuit which controls the communication and handshaking with the I O channel backplane The BIC is accessed by the Z SOB CPU as an I...

Page 29: ...HP 27130A SERIAL LA I O Q 0 LA 0 a DATA 0 8 IAJ S J a l 0 z II 0 AIlOR C 4 g 16 J Z 80B PU SERIAL I o Figure 3 1 MUX Functional Block Diagram 3 2 ...

Page 30: ...en this socket is configured for the 16K byte EPROM The address space is from OH to IFFFH when the socket is configured for 4K or 8K byte EPROMs The address space of U74 is fixed between 2000H to 3FFFH The following types of EPROMs can be installed in socket U64 4K by 8 Intel 2732 8K by 8 Intel 2764 16K by 8 Intel 27128 The following types of EPROMs and static RAMs can be installed in socket U74 4...

Page 31: ... of the sockets pins 1 2 27 and 28 are not used Tables 3 1 and 3 2 show the settings of WI for different types of EPROMs RAMs 64K FFFFH I DFFFH 48K 64K 8FFFH DYNAMIC RAM 9FFFH 48K USED 32K 7FFFH 5FFFH 16K 3FFFH 4K 8K EPROM 8K 2K 8K STATIC RAM 1FFFH 4K 8K EPROM OOOOH MEMORY MAp Figure 3 2 Memory Map 3 4 ...

Page 32: ...l U74 mU 5t 16K 27128 be empty Table 3 2 Memory Configuration Jumper W 1 Settings for Socket U74 SETTINGS ADDRESS SOCKET SPACE E F G H U74 COttMENTS 2000H DON T OPEN OPEN CLOSED 4K x 8 4K byte 2FFFH CARE Intel EPROM 4K configuration 2000H CLOSED OPEN OPEN CLOSED 8K x 8 8K byte 3FFFH Intel EPROM 8K 2764 configuration 2000H OPEN CLOSED CLOSED OPEN 2K x 8 2K byte 27FFH Hitachi static RAM 2K configura...

Page 33: ...s include the stack pointer program counter and two index registers The Z 80B CPU provides the intelligence for the MUX card to function as a preprocessor for the I O devices thus relieving the host computer of a considerable amount of processing The functions of the Z 80B CPU signals are shown in table 3 4 Z 80 S10 2 Serial 1 0 Controller The MUX card uses four Z 80 S10 2 controller circuits U43 ...

Page 34: ...C 0 Channel 0 1 1 0 1 0 0 0 0 DO H CTC 0 Channel 1 1 1 0 1 0 0 0 1 D1 H CTCO Channel 2 1 1 0 1 0 0 1 0 D2 H CTC 0 Channel 3 1 1 0 1 0 0 1 1 D3 H CTC 1 Channel 0 1 1 0 1 0 1 0 0 D4 H CTC 1 Channel 1 1 1 0 1 0 1 0 1 D5 H CTC 1 Channel 2 1 1 0 1 0 1 1 0 OOH CTC 1 Channel 3 1 1 0 1 0 1 1 1 D7 H CTC 2 Channel 0 1 1 0 1 1 0 0 0 D8H CTC 2 Channel 1 1 1 0 1 1 0 0 1 D9H CTC 2 Channel 2 1 1 0 1 1 0 1 0 DA H...

Page 35: ...ta 0 1 1 1 0 1 0 0 74 H SID 1 Channel A Control 0 1 1 1 0 1 0 1 75 H SID 1 Channel B Data 0 1 1 1 0 1 1 0 76 H SID 1 Channel B Control 0 1 1 1 0 1 1 1 77 H SID 2 Channel A Data 0 1 1 1 1 0 0 0 78 H SID 2 Channel A Control 0 1 1 1 1 0 0 1 79 H SID 2 Channel B Data 0 1 1 1 1 0 1 0 7A H SID 2 Channel B Control 0 1 1 1 1 0 1 1 7B H SID 3 Channel A Data 0 1 1 1 1 1 0 0 7C H SID 3 Channel A Control 0 1 ...

Page 36: ...ri state input output active high DO D7 are an a bit bidirectional data bus used for data exchanges with memory and I O devices Output active low Indicates that the current machine cycle is the OP code fetch cycle of an instruction execution Tri state output active low Indicates that the address bus holds a valid address for a memory read or write Tri state output active low Indicates that the low...

Page 37: ...lds valid data for the addressed memory or lID device Not used by the MUX card Not used by the MUX card Input active low Indicates to the Z 808 CPU that the addressed memory or lID devices are not ready for a data transfer This signal allows memory or lID devices of any speed to be synchronized to the Z 808 CPU Input active low Generated by liD devices A request will be honored at the end of the c...

Page 38: ...tive low 110 devices and memory use this signal to request control of the CPU address bus data bus and tri state control signals Output active low Asserted by the CPU to grant the requesting device control of the CPU address bus data bus and tri state control signals Single phase CMOS level CPU clock input Maximum input frequency is 4 MHz This clock is driven at 3 6864 MHz PHI signal in the MUX ca...

Page 39: ...2 Interrupt vector channel B only WR3 Receive parameters and controls WR4 Transmit receive miscellaneous parameters and modes WR5 Transmit parameters and controls WR6 Synchronization character or SDLC address field WR7 Synchronization character or SDLC flag READ REGISTERS FUNCTION RRO Transmit recieve buffer status interrupt status and external status RR1 Special receive condition status RR2 Modif...

Page 40: ... into bit 1 of SID 0 channel A register 5 On power up reset EN_SED is unasserted i e the transmission lines SDs of the single ended drivers are in a MARK condition o DTRB EN_DD Active HIGH When asserted the RS 422 A differential drivers are enabled OtherWise the transmission lines SD A SD B of the differential drivers are held in a high impedance state OUTPUT To assert the EN_DD signal a 0 must be...

Page 41: ...parallel to shunt the current and turn off LED The control circuit of the LED is shown in figure 3 3 In order to avoid a large current being sunk by only one of the two SID control signals for a long period of time thus damaging one of the SIOs the time between programming the two SID signals should be kept as short as possible Active LOW Whe asserted the self test loop back circuits are activated...

Page 42: ... up reset LOOP is unasserted i e no loop back HOOD_ON If the diagnostic hood is not installed the HOOD_ON signal is pulled to 5V by a 3 3K ohm resistor on the MUX card If the diagnostic hood is installed the state of HOOD_ON is the complement of the state of the HLED signal i e 0 1 1 0 HLED HOOD ON Figure 3 4 shows the circuit used to sense the diagnostic hood This circuit is also used to turn the...

Page 43: ...To the MIC s DMA controller DMA2 indicates that channel A of SID 0 is ready to transfer data to or from memory By using the MIC s DMA capability channel A of SID 0 channel 0 of the MUX card can support very high data rates On power up reset DMAO is floating Active LOW DMAO is tied to the IRQO input of the MIC When RDYB is programned as RDYB READY it is a DMA handshake Signal To the MIC s DMA contr...

Page 44: ...diagnostic hood i5 on To assert the HLED signal a 1 must be be written into bit 7 of SIO 1 channel B regi5ter 5 On power up reset HLED is unasserted i e the LED on the diagnostic hood is off No modem control lines or modem status inputs are used SIO 10 422 RTSB IfIN o 5V LED SIO 61 RSTB ON BOARD LED c GND Figure 3 3 Control Circuit for the MUX Card LED 3 17 ...

Page 45: ...HP 27130A SIO 11 DTRB MUX CARD DIAGNOSTIC HOOD HLED S05 HLED 220 SIO 10 CTSA 3 3K HOOD_ON JVVVI O 5V HOOD LEO 220 W O GND Figure 3 4 Diagnostic Hood LED Control Circuit and Hood Sense Circuit 3 18 v ...

Page 46: ...TCs are driven by the I S432 MHz clock PHI_CTC clock generated by U24 see A22 7 1 The functions of the CTC timer outputs are shown in table 3 7 Note that the CTCs are I O addressable ports to the Z SOB CPU their addresses are defined in table 3 3 Interfacing to the BIC The Backplane Interface Circuit BIC see A14 7 1 provides the half duplex data path to the I O channel backplane As used by the MUX...

Page 47: ...CB rate clock 0 2 BRGO SID 0 MUX card channel o baud RXCA TXCA rate clock 0 3 INTERNAL Cause zero Real time clock for count interrupt firmware to Z 80B CPU 1 0 BRG2 SID 1 MUX card channel 2 baud RXCA TXCA rate clock 1 1 BRG3 SID 1 MUX card channel 3 baud RXCB TXCB rate clock 1 2 BRG4 SID 2 MUX card channel 4 baud RXCA TXCA rate clock 1 3 Not avai lable Counter value can be read polled by Z 80B CPU...

Page 48: ...NPUT NO CH MNEMONIC MNEMONIC FUNCTION 2 0 BRGS SID 2 MUX card channel S baud RXCB TXCB rate clock 2 1 BRGS SID 3 MUX card channel 6 baud RXCA TXCA rate clock 2 2 BRG7 SID 3 MUX card channel 7 baud RXCB TXCB rate clock 2 3 Not available Counter value can be read polled by Z 80B CPU 3 21 ...

Page 49: ...ter Address Bit 0 Register Address Bit 2 Z 80B Write Asserted by BIC when ready for data transfer Not used Not used BIC Interrupt Non Maskable Interrupt Interface Clear Poll In conjunction with DE determines data bus drivers mode of operation Data Out specifies data bus direction Bus Primitive Bit O With BP1 specifies bus primitive operation Unary Address latches BIC channel address after a PPON o...

Page 50: ...th an odd byte I O Strobe Data Bus Bit 1 Data Bus Bit 3 Data Bus Bit 5 Data Bus Bit 7 Ground Register Address Bit 1 BIC Select enables the BIC to to read or write Z 80B Read Data Transfer Request Reset Attention Request 5 V Synchronize signals that an addressed bus operation is to occur My Address Bus Primitive Bit 1 With BPO specifies bus primitive operation Address Bus Bit 1 Address Bus Bit 3 Ch...

Page 51: ... MIC Configuration The functions of the bits of register 0 read write are as follows Bit 7 DM2 Bit 6 XNT Bit 5 DEND Bits 4 through 0 are not used Selects whether IRQ1 or IRQ2 is the DMA request sensed by DMA channel B If DM2 1 IRQ2 is sensed If DM2 0 IRQ1 is sensed External Interrupt Enable When XNT 1 the IINT line will be sensed as an interrupt by the MIC interrupt control When this bit 1 the DEN...

Page 52: ... Register 4 Lower Byte of Transfer Byte Count Channel B Register 4 read write contains the lower byte of the transfer byte count for channel B This register is not affected by reset Register 5 DMA B I O Port Address Register 5 read write contains the DMA B I O port ad dress This register is not affected by reset Register 6 DMA A Upper Byte of Memory Address Register 6 write only contains the upper...

Page 53: ...Byte Count Channel A Register 9 read write contains the lower byte of the transfer byte count for channel A This register is not affected by reset Register A DMA A I O Port Address Register A read write contains the DMA A I O port address This register is not affected by reset Register B Interrupt Vector Register a read write contains interrupt vector information Bits 3 through 7 of register B con...

Page 54: ...pt priority structure is as follows Highe5t Priority 510 2 Number 0 Channel A 510 2 Number 0 Channel B 510 2 Number 1 Channel A 510 2 Number 1 Channel B 510 2 Number 2 Channel A 510 2 Number 2 Channel B 510 2 Number 3 Channel A 510 2 Number 3 Channel B BIC CTC Number 0 Channel 0 MIC D 1A Channel A Lowe5t Priority MIC DMA Channel B Wait State Circuits for Interrupt Acknowledge On the MUX card six d...

Page 55: ...ed half a T state after ZIORQ at the rising edge of the following T state At the same time WAIT is also asserted for one full T state to add an additional wait state 10RQ follows ZIORQ on the rising edge de asserting edge The timing diagram of the wait state circuit is shown in figure 3 6 DIAGNOSTIC HOOD FOR EXTERNAL LOOP BACK A diagnostic test hood part number 0950 1659 can be ordered and used to...

Page 56: ...27130A 5V s Q Ne f D LS7 M PHI eLK r t R r W T 5 1 s o NO 5V D LS74A eLK fl o V 422 5V LSJ2 LSJ2 ____________________ IORQ ____________ ______ _ ORQ M1 Figure 3 5 Wait State Circuit Schematic Diagram 3 29 ...

Page 57: ...lW T3 eLK INT M1 I ZIORQ I IORQ I W 4JT I TW W 4JT STATE CENERATEO BY Z 80B CPU AUTOMAnCALLY DURING AN INTERRUPT ACKNOWLEDGE CYCLE TW W 4JT STATE GENERATED BY WAIT STATE CIRCUIT Figure 3 6 Wait State Circuit Timing Diagram 3 30 ...

Page 58: ...RXDA SIO 0 TXOA SIO 0 DIAGNOSTIC HOOD 1 1 1 5V SD A 511 RO S SO 8 HP 27130A 61 422 1 4W __ f rv 12 1 RO A OND Figure 3 7 Diagnostic Test Hood Schematic Diagram 3 31 ...

Page 59: ... in a high impedance state and they will not affect the single ended drivers When the single ended drivers are disabled all the SD lines will be in a MARK condition 4 volts and the D 1 diodes will be reverse biased The reverse biased D1 will isolate the single ended drivers and let the differential drivers drive the receivers The 511 ohm resistors are used to protect the U9636 single ended drivers...

Page 60: ...ures and options of the MUX which can be controlled programmatically are as follows Number of Data Bits Per Character 7 or 8 Number of Stop Bits lor 2 Transmission Mode asynchronous only in simplex half duplex full duplex or echoplex Parity none odd even 0 or 1 Automatic Detection of Baud Rate by Command baud rate defaults to 9600 Baud rate is programmable from 110 baud to 19 200 baud Break Detect...

Page 61: ... Logical Channel CLC request block from the host computer The CLC request is in response to an SRQ signal requesting the next order from the MUX CONNECT LOGICAL CHANNEL CLC REQUEST FORMAT The Connect Logical Channel CLC request block has the following format 7 6 5 4 3 2 1 0 byte 0 high byte log channel 10 1 low byte log channel 10 2 S BLK F res request code 1 L 3 subfunction code I I I I I 4 po rt...

Page 62: ...flushed before a read is begun ROD requests only request code 0 Reserved 1 Read Device Data RDD 2 Write Device Data WDD 3 Not used 4 Read Card Information RCI 5 Write Card Configuration data WCC 6 Control Card CC 7 Not used 8 15 Reserved subjunction code The content of this field is dependent on the type of the request port ID The port ID is the logical port to which the request is directed The ma...

Page 63: ...XOFF is enabled If so process the character and discard it 4 If the character is a signal character and signal character detection is enabled generate the ap propriate event and discard the character 5 If the character is quotable and quoting is enabled check the previous character for the quoting character If the quoting character is present replace it with the received character and skip the edi...

Page 64: ...e the paragraph Asynchronous Event for additional details Receive Error Conditions The firmware will terminate the current receive record when any error condition is sensed If the Do Not Terminate On Error option is set the firmware will not terminate the record Instead a user specified replacement character will replace the bad incoming character see the Additional Options paragraph for further d...

Page 65: ...E key or by typing CNTL H In addition you can programmatically change the backspace character to any desired character by using the WCC SF 6 Three options are available to indicate that a backspace has occurred when the card is in echoplex mode The first option is backspace echo This option echoes a backslash character 5C hex followed by the character that was deleted from the input buffer The sec...

Page 66: ...d to the device to prevent the device from losing any data due to its slow internal processing speed The firmware sends an ENQ character after the pacing counter has counted down to zero The card then waits for an ACK character before proceeding to transmit more characters from the transmit buffer This will ensure that buffer space in the device is available You can program the pacing counter by u...

Page 67: ...y received character to restart a transmission which was suspended because of a received XOFF This is useful when communicating with a terminal where the user may press XOFF to suspend output The MUX firmware will stop data transmission as soon as the X OFF character is received however up to two characters may be transmitted before the stoppage due to the SIO FIFO buffer If the handshake is disab...

Page 68: ...erminated with the message type indicating an end on count The End On Count option should not be confused with the internal card end on count which is set by the MUX firmware to 252 bytes This internal count is used to manage the receive buffers on the card When this count is exhausted the current record will be terminated and will be made available to the host The termination type will be set to ...

Page 69: ...eive text before the host has posted a read for the text The card has enough RAM space to buffer several text lines This will allow the device to send many lines before stopping If the receive buffer should become full any new incoming data will be lost If echoplex is en abled you will notice this when the typed character is not echoed NOTE If you should change any of the read termination para met...

Page 70: ...ined to be data read with no processing by the firmware The data is always terminated by using the End On Count option All special processing such as soft ware handshake edit mode and single text termination should be disabled This may be done by changing the read configuration in WCC SF 27 or by setting the read device data request sub function bits IItoggle editll IItoggle signalll and IItoggle ...

Page 71: ...r by timing out A control card request with subfunction 4 allows the host to terminate the frontplane receive record with the host initiated text termination termination code If no read request is active a receive record will be generated and it mayor may not contain any data However no record is generated if there is no buffer space TRANSMIT CHARACTER PROCESSING If echoing or software handshaking...

Page 72: ...ING THE RECEIVER AND TRANSMITTER The selection of the transmission mode is programmed by using the wee SF 5 Simplex receive and simplex transmit are provided to turn off the transmitter and receiver respectively The character size for the receiver and the transmitter may be specified at 7 or 8 bits per charac ter not including an optional bit for even or odd parity On transmit the user data will b...

Page 73: ...E _ I_D_n A l_p_o_r 1 MARKING UNE I ____ LEAST SIGNIFICANT DATA BIT START BIT MESSAGE FLOW L N R T S 81T WHICH MAY OR MAY NOT BE PRESENT n 6 OR 7 FOR 7 OR 8 DATA BITS RESPECTIVELY Figure 4 1 Asynchronous Message Format 4 14 ...

Page 74: ... respectively of the character will be clear or set before the character is transmitted On incoming characters the force parity bit will be stripped with no checking The parity option is programmed by using the WCC SF 13 BREAK DETECTION The firmware notifies the host of receiving a break from the device by sending an unsolicited event status if enabled HANDSHAKE TIMER After sending an ENQ the firm...

Page 75: ...be echoed if echoing is enabled The buffer however will be marked bad when eventually terminated and sent to the host Under normal operation the incoming text is terminated when any error is encountered Furthermore the character causing the error is added to the text record for the host This allows the host to detect undesirable error conditions If the lido not terminate text record on error optio...

Page 76: ...TUS CODE SET ERROR BIT IN THE TERMINATION CODE REPLACE RECEIVED CHARACTER WITH THE REPLACEMENT CHARACTER CONTINUE NOR Al RX PROCESSING Figure 4 2 Error Handling Flow Chart 4 17 HP 27130A EXIT IGNORE CHARACTER TERMINATE THE CURRENT RX RECEIVE ...

Page 77: ...he firmware will ex amine every outgoing character for the user specified record separator which has a default value of the linefeed character If the user supplied record separator is found the firmware sends the output separators in place of the record separator If the Automatic Output Separators Appendage option is enabled the output separators are also added to the end of each message Speed Sen...

Page 78: ...rupt is enabled by setting the corresponding mask bit and disabled by clearing the bit If the interrupt mask for an event is disabled you may poll for the event by using Read Card Information RCI Subfunction SF 254 See the paragraph Event Block Description for a detailed description of the event block format returned to the host If all interrupt conditions are disabled no asynchronous interrupts w...

Page 79: ...uck at faults in the data lines system control interrupt control except CTC 1 and 2 which have no interrupt capability and the four channel signals for each CTC BIC test Checks the Backplane Interface Circuit BIC for functional faults Checks for some stuck at faults in internal BIC registers The BIC circuitry is tested using the internalloopback functionality built into it Testing of I O channel d...

Page 80: ... 1 0 second Card Self test begun Successful Set PST Turn off lED Unsuccessful Hal t Z80 t2 3 seconds if RES or 15 seconds if DCl DEN may be less CONNECT LOGICAL CHANNEL REQUEST DEFINITIONS The following paragraphs describe the subfunction options that are available for each Connect Logical Channel CLC request See the paragraph Connect Logical Channel CLC Request Format for a description of the dat...

Page 81: ...erved toggle character quoting toggle echo toggle character editing toggle signal character detection toggle character handshakes X ON X OFF and ENQ ACK see CAUTION under Host ENQ ACK Handshake paragraph Write Device Data Request Code 2 Subfunction code I 7 I 6 I 5 I 4 I 3 I 2 I 1 1 0 1 automat1c output separators appendage 4 22 ...

Page 82: ...mation defined in subfunctions 0 through 33 of the write card configuration respectively Subfunction 249 Read Data Status Returns a byte which indicates the presence of any receive data terminated or not on the MUX for the indicated port Received data exists on either the backplane or frontplane if the returned byte is non zero The data block returns the following byte 0 data on frontplane or back...

Page 83: ...n the data block Data block byte 0 transmit buffet is empty reserved signal character 1 received signal character 2 received signal character 3 received signal character 4 received byte 1 171615141312111 1 handshake timeout This status will be cleared each time it is read 4 24 ...

Page 84: ...ption of the type of validation performed on the parameter passed in the data block will be given If the parameter is not valid an illegal configuration parameter value error will be returned Subfunction O This subfunction sets all of the configuration data defined in subfunctions 1 through 32 The data is position dependent according to each subfunction code This subfunc tion allows one call to co...

Page 85: ...21 reserved 22 host interrupt mask first byte 23 host interrupt mask second byte 24 host X ON character 25 host X OFF character 26 device X ON character 27 device X OFF character 28 host ENQ character 29 host ACK character 30 host ENQ ACK counter 31 reserved 32 reserved 33 a single text terminator character for echoing CR LF 34 number of output separators 35 1st output separator character or null ...

Page 86: ...nal character 2 48 quotable single text terminator 49 number of single text terminators 50 1st single text terminator character 51 2nd single text terminator character 52 3rd single text terminator character 53 4th single text terminator character 54 5th single text terminator character 55 6th single text terminator character 56 7th single text terminator character 57 8th single text terminator ch...

Page 87: ... end on count terminate on single text terminator reserved reserved echo on edit mode on reserved enable character handshake Validation If the echo bit is set the transmission mode must be full duplex The transmission mode must be programmed first before setting the read option 4 28 ...

Page 88: ...gth Data block 7 6 5 4 3 2 1 0 byte 0 high byte end on count length I 1 low byte end on count length Validation none Subfunction 3 Alert 1 Read Mode Data block byte 0 I7 I6 I5 I4 I3 121 1 1 0 1 L enable alert 1 read mode Validation none 4 29 ...

Page 89: ...e transmission mode must be set before setting the read option Note that the echo bit will be reset if the trans mission mode is not full duplex Subfunction 6 Backspace Character The character specified in the data block will be used as the backspace character for the edit mode Validation none Subfunction 7 Line Delete Character The character specified in the data block will be used as the line de...

Page 90: ...ions Data block byte 0 Validation none backspace echo 1 backspace over wri te 2 backspace only handshake timer is for X ON X OFF or ENQ timer 1 0 respectively reserved reserved reserved strip single text terminators reserved 4 31 HP27130A ...

Page 91: ...a block byte 0 I7 I6 I5 I4 I3 121 1 I0 I 1 reserved L host ENQ ACK ______ device X ON X OFF ______host X ON X OFF echo single text terminators send message after ENQ timer times out echo CR LF for a specified single text terminator Validation none 4 32 ...

Page 92: ...0 reserved 11 2400 12 reserved 13 4800 14 reserved 15 9600 16 19200 8 reserved 17 31 reserved Validation The value must be within the range 0 through 16 inclusive Subfunction 11 Character Length Data block byte 0 I 7 I 6 I 5 I 4 I 3 I 2 I 1 1 0 1 1 reserved reserved 7 data bits 3 8 data bits Validation The value must be within the range 0 through 3 inclusive 4 33 HP 27130A ...

Page 93: ... stop bit 1 reserved 2 2 Validation The value must be within the range of 0 through 2 inclusive Subfunction 13 Parity Data block byte 0 none 1 odd 2 even 3 0 4 1 ___ignore parity errors ___discard characters with errors Validation The value of bits 0 2 must be within the range 0 through 4 inclusive 4 34 ...

Page 94: ...ecause there is only one timer per port the handshake for which the timer is used is selected by WCC SF 8 If the timer selected by WCC SF 8 is not the handshake enabled by WCC SF 9 no timer will be used Subfunction 21 Host Interrupt Mask Subfunction 21 enables the specified unsolicited interrupt to the host Data block byte 0 transmit buffer is empty reserved signal character 1 signal character 2 s...

Page 95: ... timeout reserved reserved reserved reserved reserved reserved Validation None The data is not checked Subfunction 22 Host X ON X OFF Characters Data Block byte 0 character for host X ON function byte 1 character for host X OFF function Validation Two bytes must be given 4 36 ...

Page 96: ...rs to transmit before sending an ENQ and waiting for an ACK count should be 1 to 255 Validation One byte must be given Subfunction 27 Single Text Terminator for Echoing CR LF Anyone of the single text terminator characters may be specified to cause the echoing of the CR LF characters However only one character may be used for the special echoing function This character is specified in the data blo...

Page 97: ...the text record on receive data error enable signal character detection insert a null character into the receive buffer when a break is detected r eplacement charac t e r fo r the bad incoming character quoting character record separator character to invoke sending the output separators signal character 1 signal character 2 byte 6 quotable single text termintor byte 7 signal character 3 byte 8 sig...

Page 98: ...le text terminator Validation From one to eight characters may be specified Subfunction 33 Card Write Register This subfunction is used for on line diagnostics capability Data Block byte 0 I 7 I 6 I 5 I 4 I 3 I 2 I 1 1 0 1 7 6 byte 1 0 1 1 reserved differential drivers off ___single ended drivers on _____loopback hood LED on __ Self test mode on card LED off reserved reserved 5 4 3 2 1 0 0 1 0 0 1...

Page 99: ... logical port ID except that it should not duplicate any other ID Validation The data must be between 0 and 7 inclusive Control Card Request Code 6 See the paragraph Buffer Flushing for additional details on this request code A summary is shown below SUBFUNCTION DESCRIPTION o 2 3 4 5 6 7 No operation Flush the current receive buffer Flush all the queued receive buffers Flush all the queued transmi...

Page 100: ...number LCN RTS description Nothing to do The LCN field is not used Swi t ch tot he transaction given in the LCN field 1 0 WTC description Not used Resume the transaction given in the LCN field 2 Terminate the data Terminate the data 3 4 transfer for the transaction given in the LCN field Abort the trans action given in the TID field Event sensed The event block as defined below is returned to the ...

Page 101: ...ed 1 data message received Message length and type are given in the information field 7 6 5 4 3 2 1 0 byte 3 high byte length 4 low byte length I 5 not used E message type _I 6 text term for message type 1 message type 1 text terminated on single text terminator The text terminator which terminated the message is given in byte 6 4 text terminated by count 5 text terminated by parity error 6 text t...

Page 102: ... record contains an error Parity Error PE Framing Error FE Overrun Error OV break received from the device t ransmi t buffer is empty signal character 1 received signal character 2 received signal character 3 received signal character 4 received reserved character handshake timeout 253 reserved speed sense completed 7 6 5 4 3 2 1 0 byte 3 where baud rate is as defined baud rate for wee SF 10 HP 27...

Page 103: ...t request status 1 length of data transfer 2 3 length of data remaining in 4 cur re nt record for the read 5 not used E message type 6 text terminator for mess type 1 card dependent request status 0 no error 1 illegal subfunction 2 illegal configuration parameter values 3 illegal configuration parameter length Amount of useful information END here for all control requests Amount of useful informat...

Page 104: ...y termination initiated by the host For ex ample if the host started a host read request of 200 bytes and the card is able to send 200 bytes the card will return the length as 200 even if the host invoked END to terminate the transfer early message type 1 text terminated on single text terminator The text terminator which terminated the message is given in byte 6 4 text terminated by count 5 text ...

Page 105: ...t s 1 7 I I 6 max requests port 1 2 I I 7 maximum guaranteed 8 data blocking size 252 END MPX 1 for in channel multiplexing MOD 2 for both byte and word mode data transfers DEFAULT MUX CONFIGURATION Upon a reset or power up condition the MUX will be set to the configuration states defined below enable software handshake no edit mode disabled echoing disabled terminate on single text terminator dis...

Page 106: ...N X OFF handshake disabled host ENQ ACK handshake disabled baud rate 9600 character length 8 bits character number of stop bits 1 parity none host ENQ ACK timer 5 seconds host interrupt mask all cleared to disable interrupts host X ON character DC1 host X OFF character DC3 device X ON character DC1 device X OFF character DC3 single text terminator for echoing CR LF CR host ENQ character ENQ host A...

Page 107: ...aracter for bad incoming character DEL quoting character record separator to invoke sending output separators LF signal character 1 OFF hex signal character 2 OFF hex signal character 3 OFF hex signal char cter 4 OFF hex quotable single text terminator character EOT Control D number of single text terminators 1 single text terminator character CR SUBFUNCTION ASSIGNMENT SUMMARY A summary of all sub...

Page 108: ...he request Write Device Data SUBFUNCTION bit 0 0 no output separator appendage 1 append output separators SUBFUNCTION 0 through 33 see write card configuration 249 get receive buffer status 250 get the card RAM 254 get the card status Write Card Configuration SUBFUNCTION 0 configure subfunctions 1 through 32 1 configure the read option 2 end on count length 3 configure alert 1 mode 4 not used 5 tr...

Page 109: ...shake timer 19 not used 20 not used 21 host interrupt mask 22 host X ON X OFF characters 23 device X ON X OFF characters 24 ho t ENQ ACK characters 25 host ENQ ACK pacing counter 26 not used 27 single text terminator for echoing CR LF 28 output separator 29 not used 30 not used 31 additional options 32 single text terminator 33 card write register 34 set port ID 4 50 ...

Page 110: ...ive buffer 2 flush all the queued receive buffers 3 flush all the queued transmit buffers 4 host initiated frontplane receive text termination 5 force restart of transmitter if waiting for handshake 6 enter speed sense mode 7 abort speed sense mode 8 suspend transmitter 4 51 ...

Page 111: ...hen specifically invoked by you 4 Turn on computer system power 5 When the self test executes the LED located on the test hood and the LED located on the MUX card both should light briefly and go out if the card passed self test If the LEDs do not light at all the card is defective If the LEOs stay lit the card did not pass self test If desired isolation to a defective part may be performed Please...

Page 112: ...ckard part number 3 Part number check digit CD 4 Total quantity QTY 5 Description of the part 6 A five digit manufacturer s code number of a typical manufacturer of the part Refer to table 6 2 for a cross reference of the manufacturers 7 The manufacturer s part number ORDERING INFORMATION To order replacement parts or to obtain information on parts address the order or inquiry to the nearest Hewle...

Page 113: ... in the replaceable parts table specify the following information 1 Identification of the kit containing the part refer to the product identification information supplied in Section 2 2 Description and function of the part 3 Quantity required 6 2 ...

Page 114: ...80 CAPACITOR FXD 0tuF 107 100VDC CER 28480 2 DIODE SM SIG SCHOTTKY 28480 DIODE SM SIG SCHOTTKY 284BO 1 DIODE ZNR 2 37V 5 DO 7 PD 4101 TC 074 28480 1 LED LAMP LUM INT lMCD IF 20MA MAX BVR 5V 28480 3 FUSE 5A 125V NTD 281 X 093 28480 FUSE 5A 125V NTD 281X 093 28480 FUSE 5A 125V NTD 2B1X 093 28480 1 CONN POST TYPE 100 PIN SPCG BO CONT 2 8480 1 CONN HDR 72 PIN 2B4BO 2 CONNECTOR 16 PIN M POST TYPE 28480...

Page 115: ... 01295 1 IC DRVR TTL l S LINE DRVR OCTL 012_95 BURNIN 181B 1425 84BO 2 IC RCVR TTL LS LINE RCVR QUAD 2 INP 28480 4 IC DRVR TTL LINE DRVR DUAL 07263 IC DRVR TTl LINE DRVR DUAL 07263 DURNIN lB18 1425 28480 IC MUXR DATA SEl_ TTL LS 2 TO l LINE QUAD 01295 2 ICD 75174 DRIVER 8480 ICD 75174 DRIVF R 284f 10 IC RCVR TTL LS LINE RCVR QUAD 2 INP 284BO IC DRVR TTL LINE DRVR DUAL 07 3 IC DRVR TTL LINE DRVR DU...

Page 116: ...any Mi lwaukee Wi 53204 01295 Texas Instruments Inc Dallas Tx 75222 Semiconductor Components Div 07263 Fairchild Semiconductor Div Mountain View Ca 94042 24546 Corning Glass Works Bradford Bradford Pa 16701 28480 Hewlett Packard Co Palo Alto Ca 93404 Corporate HQ 56289 Sprague Electric Co North Adams Ma 01247 6 5 ...

Page 117: ...0 U33 N U41 a U43 U55 8 U54 U65 IF U53 U51 I Ip5 I IE U85 U64 U63 U61 U95 I t Ii I U105 U74 U73 U71 12 U115 I 2 12 W1X1 U84 U83 U82 1 U125 R18 U92 N 2 12 12 a U97 U96 U95 a U102 a a J CR4 0 ill F2 F3 Figure 6 1 HP 27130A Parts Location Diagram 6 6 ...

Page 118: ...SCHEMATIC DIAGRAMS 1 This section contains schematic logic diagrams for the MUX card 7 1 7 2 ...

Page 119: ...________________ t H 13 I lSt 51 5 1 5 2 53 54 55 HP 27130A 5 6 5 7 58 u97 r F4P J 2 t 75114 3 5001 I V 2 SOOIB 1 5 50 1 50 11 25 2 1 II 5021 I 2 1 0 SD2 1 130 3 5031 50311 130 5 0 U98 561 26 EN 562 12 563 EN2 29 75tH 3 SD4IA I 1 2 SD4 B 13 1 133 5 5DS A 31 5051 33 9 II SOS A I 2 1 0 50 1 I 2 1 lli 13 S01 A 13 50 11 13 5GO I I 565 3 3K I 8 RI 6 5 12 5 21 5K 12Y Itlj y 35 67 l 35 2 J I 0 4 9838 t 0...

Page 120: ...S t A2 A3 AI2 RI3 AND All AU 10 PIN SIPS EACH SIP CONTAINS I IDENlleH RESIS10RS HleH HAVE CUllOM Pili I S 31 14 cc PPOI I sue POLL OSS eEIO CIYT UIO IS 01 101 102 ADI BPO BPI DOUT EHD 2 SEl DYA 050 051 DO 01 02 OS 01 05 DB 01 U4 I BI C AST BA DEND DIYT DE BIOOl BlOOt BII02 BI003 BlOOI a1005 Bl008 81007 alOOI alOOI 110010 BIOOII BIOOI2 alOOII BI0014 BI0015 ARI IIUD NU BlNI AYD DTUK 0 0 15 16 17 ___...

Page 121: ... 13124 ce W6 u 8I X SH 2 1 E2I 2 XI2 0 pO 2 W7 21 SH 23 E2 EH 5 5 1XI3 III X I E RO 8 112 I l 01 H I 0 0 1122 111121 23 XII W 4 v 7 II IU 0 0 112 I IEH IX II 11 1111 II 00 ul H _ I BI X PROI 1111 1 EH 2 2 1 XII It v II 1221 r BI X SH 19 221 1 IEH 2 O lXII Ne r C E O II 1231 1141 o l W B III II 1231 1 5 2 1 18 OENO I ausRI v 11 III 113103 13 L V H II 1 r IIII DlUS I I J V II 121 Itt 02 F EH 1 II 21...

Page 122: ... _ _ _ ___ _ _ _ J f L ___ _ r c HCB AXeR AlDR elSB DCDR TXDB 1 8 _ _I X D 7 _CJID ROU r IlC RTSB NC DTAa r He A B c C RXD2 ___ I c C R X O r r I r Ir r r r j H _r _ _ _ H _r l _ 7 D __I _ _r r II___I_ _I_ I_ ___IH X O_ _ _r I___I_ _I__r I___I _ _I_ 17XO c o E E O Da r i 1 i a i I I t r i E5I _ I_ t _I_ _ _I_ _r_ _r__I E a R XDc 8 r_r _ I_r _I_ _ _I_ _r_ _ r__I E a R lD _ _ I_ t _I_ _ H r IH_ ___i...

Page 123: ...33 25US ACCESS TIllE It Tt5V r R ES Ec _ ____________ 1f _ t f RESET VOO e3 t t IT N _ Q D J L t f U3 4 8 U S R9 4 O 0 INT NMt BUSHQ CLOSE JUMPER AFlER SIGNATURE ANAlYSIS TEST CLK f g 5V 2 3 3 3 3 1 11 3 3 R2 R2 RI R2 0 U25 1 o 6 I so P 3 U3 4 5 0 t I i T P A L _______ IC TEST V 5 U25 MI 27 RD f i R r_ _i_ _ r c ________ D R9 J 4 lSOB 6 RD IIIe RD MR MREIJ HALl NC B Hio N C 3 I 00 07 ZBOA 115 I 3 ...

Page 124: ...LE sp 0 p P 1 SOH DCl 1 A Q a q 2 STX DC2 2 B R b r 3 ETX DC3 3 C S c s 4 EOT Dc4 4 D T d t 5 ENQ NAK 5 E U e u 6 ACK SYN 6 F V f v 7 BEL ETB 7 G W g w 8 BS CAN 8 H X h x 9 HT EM 9 I Y i y A LF SUB J Z j z B VT ESC K k C FF FS L 1 I D CR GS M m E SO RS N n F S1 US 0 0 DEL A I ...

Page 125: ...9 Backspace 4 6 BIC 3 19 Binary data 4 11 Break detection 4 15 Buffer flushing 4 12 c Cable 1 3 Capabilities alert 1 read mode 4 9 appepding automatic output separators 4 12 appending conditional output separators 4 18 backspace 4 6 buffer flushing 4 12 device X ON X OFF handshake 4 8 echoing 4 10 edit mode 4 6 end on count text termination 4 9 error handling 4 16 host ENQ ACK handshake 4 7 1 1 IN...

Page 126: ...ry data 4 12 type ahead 4 10 Capabilities 4 4 Checkout 2 13 Conditional output separators appendage 4 18 Configuration default settings 4 46 Connect Logical Channel CLC request format 4 2 Connect Logical Channel request subfunction definitions 4 21 Connection box 1 3 Control card request code 6 4 40 Control cardsubfunction 4 51 Counter timer circuit 3 19 CPU 3 6 CTC 3 19 Current requirements 2 1 o...

Page 127: ... 1 3 Equipment supplied 1 3 Error handling option 4 16 Event block description 4 42 Extension cable kit 1 3 F Firmware installation 2 1 Functional description 1 1 3 1 H Handshake timer 4 15 Host ENQ ACK handshake 4 7 Host initiated text termination 4 12 Host X ON X OFF handshake 4 8 INDE X 1 3 ...

Page 128: ...ation 1 3 Identity Information Block Definitions 4 46 Installation EPROM 2 1 firmware 2 1 manual 1 4 MUX 2 12 Installing the MUX 2 12 Interface I O channel 2 5 peripheral device 2 5 to the BIC 3 19 to the MIC 3 24 Interruptackno ledge 3 27 Interrtiptstr ctu e f 27 J Jumpers 2 3 L Line deletion 4 6 1 4 ...

Page 129: ...A A I O port address register 3 26 MIC DMA A lower byte of memory address register 3 25 MIC DMA A upper byte of memory address register 3 25 MIC DMA B configuration register 3 24 MIC DMA B I O port address register 3 25 MIC DMA B upper byte of memory address register 3 24 MIC interrupt vector register 3 26 Microprocessor 3 6 MIC Register 0 3 24 Register 1 3 24 Register 2 3 24 Register 3 3 24 regis...

Page 130: ...mmable features 4 1 Programming the receiver and transmitter 4 13 Q Quoting character mode option 4 18 R RAM installation 2 1 Read card information subfunction 4 49 Read card information write control request 4 23 Read device data subfunction 4 49 Read device data write control request 4 22 Read request length 4 11 Read status request 4 44 Receive character processing 4 4 Receive error conditions ...

Page 131: ...ister A 3 26 Register B 3 26 Repair 5 1 Replaceable parts 6 1 Reshipment 2 14 RTS and WTC block definitions 4 41 s Serial I O Controller 3 6 Service 5 1 Signal character 4 5 Signature analysis jumper 2 3 Single text termination 4 9 SIO 2 3 6 Software handshake 4 7 Solicited events 4 19 Specifications 1 4 Speed sense capability 4 18 Subfunction assignment summary 4 48 Subfunction definitions 4 21 I...

Page 132: ...shake timer 4 35 21 host interrupt mask 4 35 22 host X ON X OFF characters 4 36 23 device X ON X OFF characters 4 37 24 host ENQ ACK characters 4 37 25 host ENQ ACK pacing counter 4 37 27 single text terminator for echoing CR LF 4 37 28 output separator 4 37 31 additional options 4 38 32 single text terminator 4 39 33 card write register 4 39 34 set port ID 4 40 249 read data status 4 23 250 get c...

Page 133: ... 12 Transparent data 4 11 Type ahead 4 1 0 w Wait state circuits for interrupt acknowledge 3 27 Write card configuration request code 4 25 Write card configuration subfunction 4 1F Write control requests read card information 4 23 read device data 4 22 write device data 4 22 Write device data subfunction 4 49 Write device data write control request 4 22 z z 80B CPU 3 6 1 9 INDEX ...

Page 134: ...MANUAL PART NO 27132 90006 Printed in U S A June 1983 rli HEWLETT t PACKARD HEWLETT PACKARD COMPANY Roseville Networks Division 8000 Foothills Boulevard Roseville California 95678 ...

Search results

Summary of Contents for 27130A

Reviews:

Related manuals for 27130A

Brands by name

Popular brands

HP 27130A, Technical Reference Manual

Search results

Summary of Contents for 27130A

Reviews:

Related manuals for 27130A

Brands by name

Popular brands